• RELEVANCY SCORE 5.05

    DB:5.05:Fir Compiler With 2 Channel ... 7s





    Hi.


    Anyone has ever used the FIR Compiler 3.2 or Fir Compiler 4.0 with 2 input channels ? I have some problem with 2 channel.

    You have an example working model ?Thanks. Kappa.

    DB:5.05:Fir Compiler With 2 Channel ... 7s


    Hi.


    Anyone has ever used the FIR Compiler 3.2 or Fir Compiler 4.0 with 2 input channels ? I have some problem with 2 channel.

    You have an example working model ?Thanks. Kappa.

  • RELEVANCY SCORE 4.72

    DB:4.72:Fir Design 31




    could you please provide fir compiler block design..

    i am facing problem with connecting FIR Compiler to zynq processor

    i dont know what in between them (fifo, dma, interconnect....)







    Solved!
    Go to Solution.

    DB:4.72:Fir Design 31


    Hi

    Check below link

    http://forums.xilinx.com/t5/Embedded-Processor-Sys​tem-Design/FIR-compiler-and-PS/m-p/549433#M13650




    Regards,Satish--------------------------------------------------​--------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful.--------------------------------------------------​-------------------------------------------

  • RELEVANCY SCORE 4.51

    DB:4.51:Fir Compiler Problem: Output Channels Getting Swapped m8





    Hello,

    I am facing this peculiar problem with the FIR compiler v 5.0 (ISE 11.2, Virtex SXT95). I am implementing a 6-channel decimation-by-5 FIR filter using this core. The outputsare get decimated as expected. However, in every cycle, the outputs get swapped in the sequence and appear on different channels (in the functional simulation in ModelSim XE 6.4b). I rely on chan_out signal to separate the outputs and the sequence is different in every cycle.

    While debugging this design, I performed the following checks:

    - I checked my input stream to see if the channels get swapped at the input stage itself. But they don't.

    - I checked if the nd signal is any way different in the other cycles. It is same.

    Has anyone encountered the similar problem?

    Regards,

    Kumar Vijay Mishra.







    Solved!
    Go to Solution.

    DB:4.51:Fir Compiler Problem: Output Channels Getting Swapped m8


    I resolved the problem of outputs getting clipped. Turns out I was using SCLR (deterministic behavior) option for the FIR core. When this happens, the core forces output to be zero initially till it flushes out the internal values. Some portion of my valid input was in this time period and hence its corresponding output was forced to zero. I delayed my input and could then see the full output.

    Regards,

    Kumar Vijay Mishra.

  • RELEVANCY SCORE 4.46

    DB:4.46:Cross-Correlation And Auto-Correlation Using Fir Compiler... ak



    Hi,

    I am trying to implement two functions in my 802.11a OFDM Receiver implementation (Time Synchronization) using FIR Compiler:

    1) Cross-Correlation to find LTS (Long Training Sequence) of length 64

    To do this I am using FIR Compiler with 64 Coeffients (With Reverse Sequence of LTS values) and implemented matching filter which is working fine to find peak for LTS. So this part is working find using FIR Compiler.

    2) Auto-Correlation of 16 Symbol STS (Short Training Sequence) with it's delayed value by 16 Symbols

    How can I implement Correlation STS with 16 Symbol delayed version of itself using FIR Compiler?

    Can someone provide an example?

    If this is not possible by using FIR Compiler Block, Can someone provide me information as how this can implemented using Xilinx System Generator blocks.

    Thanks

    Rajan

    DB:4.46:Cross-Correlation And Auto-Correlation Using Fir Compiler... ak


    Hi,

    I am trying to implement two functions in my 802.11a OFDM Receiver implementation (Time Synchronization) using FIR Compiler:

    1) Cross-Correlation to find LTS (Long Training Sequence) of length 64

    To do this I am using FIR Compiler with 64 Coeffients (With Reverse Sequence of LTS values) and implemented matching filter which is working fine to find peak for LTS. So this part is working find using FIR Compiler.

    2) Auto-Correlation of 16 Symbol STS (Short Training Sequence) with it's delayed value by 16 Symbols

    How can I implement Correlation STS with 16 Symbol delayed version of itself using FIR Compiler?

    Can someone provide an example?

    If this is not possible by using FIR Compiler Block, Can someone provide me information as how this can implemented using Xilinx System Generator blocks.

    Thanks

    Rajan

  • RELEVANCY SCORE 4.41

    DB:4.41:System Generator 10.1 - Fir Compiler V4.0 - Error:Coreutil:424 dk



    Greetings,

    Target: Virtex xc4vsx35_10ff668

    I am loading a Fir Compiler v4.0 block with 3073 coefficients and when try to generate a bit file I get a generic error from system generator(unspecified error). The "compilation status" never gets past "Running Netlister". Looking at the forums and other xilinx answer sites I have found that that multiple things can be the cause.

    The Coregen log specifies "Error:coreutil:424 - An error occurred while running Java."

    Possible causes:

    http://www.xilinx.com/support/answers/29430.htm

    http://www.xilinx.com/support/answers/23614.htm

    http://www.xilinx.com/support/answers/32300.htm

    1) My path may be to long.

    ----I have placed the model file and target location in the root directory (c:/) and did not have any results

    2) The Java memory option is incorrect in coregen

    ----I went into coregen and changed it from the default (1024MB) to lower (512MB) and it did not make a difference.

    3) To many coefficients----Found that the limit may be 1024 so I broke up my filter into 4 parts with 768 coefficients each, no difference.

    I have an additional filter (Fir Compiler v4.0) with 40 coefficients and when I remove all but this filter it compiles just fine.

    System Ram: 3.45GB

    Windows XP 32-bit

    While compiling system ram does get close to maximum (3.45GB)

    Any ideas? Thanks in advance,

    -Jose

    DB:4.41:System Generator 10.1 - Fir Compiler V4.0 - Error:Coreutil:424 dk


    Update:

    I happen to run the compilation again with the split method (using 4 Fir Compiler v4.0 blocks instead of one with 3073 coefficients) again and it made it through the "Running Netlister" stage. It took 2 hours!

    However, it errors out during the "Xflow" process. These are the two errors:

    1) Pack:2310 - Too many comps of type "DSP48" found to fit this device.

    2) Map: 115 - The design is too large to fit the device.

    I guess this is hard to believe since I only have 25 blocks in the entire model. (5 are Fir Compiler v4.0 blocks).

    If there are any suggestions for implementing a filter of this size it would be greatly appreciated.

    Also, if anyone believes that I have design errors that are creating the errors please reply.

    Thanks,

    Jose

  • RELEVANCY SCORE 4.30

    DB:4.30:Transposed Multi-Mac Fir pz



    I do not understand the functionality of the Transposed Multi-MAC FIR

    on page 9 datasheet "FIR COMPILER v4.0". Can some one tell me what

    happens each clock cycle, I do not understand the control mechanism.

    Regards

    DB:4.30:Transposed Multi-Mac Fir pz


    What happens is that the MACC engines actually run for 4 clock cycles as a MAC, and on the 4 cycle, they change from a MACC to a MACC and the mux selects from the adjacent MACC at this time. So each one runs independently for 3 cycles and then the structure turns into more of a Systolic structure for 1 cycle to pass the intermediate results on, and then changes back to a MACC.

    For more information on this and other filter structures, I would recommend taking the DSP Implementations Techniques class offered by the Xilinx Customer Education.

    http://www.xilinx.com/support/training/abstracts/d​sp-implementation.htm




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 4.16

    DB:4.16:Fir Coefficients And Design Sampling Rate For Fractional Rate Decimation ca



    Hello everyone,

    Here is my current design situation:

    I am designing an FPGA to down-sample a 160MHz input signal to 51.2MHz using the fixed-fractional rate decimator in the FIR compiler. This requires interpolation by 8, filtering, and decimation by 25. The process has been simulated in Matlab with the upfirdn() function and by designing a lowpass filter being sampled at 8*160MHz = 1.28GHz.

    My question is this:

    For the FIR compiler in fixed-fractional rate down-sampling mode, should the filter coefficients be designed at the input sampling rate (160MHz) or post-upsample rate (1.28GHz)? I didn't find clear wording in the data sheet to help me understand the correct filter design, but I'm assuming the filter coefficients should be provided with respect to the input sampling rate.

    Thanks!

    -Steve

    DB:4.16:Fir Coefficients And Design Sampling Rate For Fractional Rate Decimation ca

    Disclosure: I've never used any of the Xilinx FIR tools/models. (I have designed multi-rate filters using Xilnx FPGAs).

    You design your low-pass filter at the interpolated rate (for you 1.28 GHz). I can't see how the Xilinx software could do this for you. Specifying the filter at the input sample rate makes no sense.

    One assumes the Xilinx FIR compiler does the polyphase filtering implementation correctly.

    Regards,

    Mark

  • RELEVANCY SCORE 4.15

    DB:4.15:Designing Fir Compiler 7.1 fj



    I designed a decimation(Low pass FIR) to decimates 3MHz to 17.8571KHz.( Filter cut offs are 27KHz pass band,40KHz stop band freq.pass band ripple is 2dB and stop band atteunuation is 45dB )with the help of MATLAB and loaded the "coe" while generating FIR compiler 7.1 IP core. But when i compared Frequency response of both MATLAB and FIR compiler i found a difference in Magnitude(dB),i noticed a column called Filter analysis i)pass band ii) stop band,But the range is upto 1dB??

    But my Requirement is (pass band ripple is 2dB and stop band atteunuation is 45dB). Is it possible to generate a Decimation filter with this IP core???

    pls find the snapshots










    Attachments:




    DB:4.15:Designing Fir Compiler 7.1 fj


    Oh no, not necessarily.

    Take an example. Say you have generated 8 bit coefficients (from FDATool) with 1 integer bit and 7 fractional bits. Say you have a (signed) coefficient value of 0x2F, which corresponsds to 0.3671875 in our FIX_8_7 notation.

    Now say we have set the FIR compiler to interpret coefficients as having 5 integer bits and 3 fractional bits (FIX_5_3). 0x2Fwould be 5.875. This is off by a factor of 2^-4 exactly.

    What does this matter? The bits are the same?

    Yes, that is true, but the key is how the arithmetic is performed with a giveninput bit format as well (FIX_X_Y). The binary points will be lined up first and then then the math is computed. This is where the perceived scaling may come from because thisimplies a shift (which is equivalentto 2^n multiplication)




    www.xilinx.com

  • RELEVANCY SCORE 4.08

    DB:4.08:Issue With Fir Compiler 3.2 And Interpolation Filter k8



    Hi everyone,

    I'm currently using a design with a 5 /4 interpolation Filter used to convert a signal sampled @ 80 MHz to 100 MHz.

    For this purpose we have used a 33-tap filter. The filter works well however there is an implementation difference between Matlab and the Xilinx core. I used a step response to characterize both systems and I obtain slightly different results. There is a slight phase delay between the Matlab implementation (with upfirdn function) and the interpolation FIR filter compiled with FIR Compiler 3.2.

    I have run some tests to understand better the problem and it seems to be related with the decimation process. Let me explain :

    Assuming

    X : original signal sampled @ 80 MHz

    X_up : signal stuffed with 4 zeros for every sample @ 400 MHz (only used for explanation purposes)

    Y : X_up filtered by our 33-tap FIR filter @ 400 MHz

    Z : Decimated version of Y Signal @ 100 MHz

    X = X0, X1, X2, X3,... Xn, ... Xm,...

    The complete resampling process would look like this

    X_up = X0,0,0,0,X1,0,0,0,0,X2,0,0,0,0,X3,0,0,0,0,X4,0,0,0​,0,....,Xn,0,0,0,0,....

    Then X_up is filtered by the FIR filter to obtain the "Y signal".

    Y = Y0, Y1, Y2, Y3, Y4,, Y5, Y6, Y7, Y8 .... @ 400 MHz

    By decimating by 4, we take only 1 sample out of 4. However it seems that Matlab and Xilinx do not take the same sample

    In Matlab, with the upfirdn function, I obtain the following results

    Z_matlab = Y0, Y4, Y8, Y12, ... @ 100 MHz

    Z_xilinx = Y1, Y5, Y9, Y13,... @ 100 MHz.

    Basically, the Xilinx output signal is shifted by one sample @ 400 MHz, or one quarter of a sample @ 100 MHz. Am I the only one that got this problem? Is there a way to control the decimation process by selecting which sample out of N is selected? This is an important issue since the decimation process influences the phase of the signal.

    I am also aware that with the polyphase implementation, the implementation does not compute all samples in the Y sequence @ 400 MHz, I only added these intermediate signals to be clearer.

    Thanks

    Benjamin Couillard

    DB:4.08:Issue With Fir Compiler 3.2 And Interpolation Filter k8

    I think the implement of factional interpolation filter of Xilinx and Matlabshould be the same.

    For Xilinx fractional interpolation filterimplementation, we have documented how it is built on the FIR Compiler data sheet. It is illustrated in a diagram.

    But I do not know if Matlab has the same document to elaborate its implementation.

    For Xilinx fractional interpolation filter, we do not have a option to control which sample out of N should be sampled, as its implementation is fixed since you are trying to design a 5/4 interpolation filter.

    If you have any further questions, I would recommend you open a new webcase at Xilinx Technical Support.

  • RELEVANCY SCORE 4.02

    DB:4.02:Fir Filter Code In Vhdl f8



    this is my code in vhdl for fir filter 4 tap using transpose form.i have a problem .the output is not getting verified with the formula of fir filter plzzz help










    Attachments:







    fir.doc ‏44 KB

    DB:4.02:Fir Filter Code In Vhdl f8


    Hi ,

    I saw the code attached with your post . I have few comments for you .

    1) You have not used the clock in your design

    2) All the assignment statements in the code = is not clock sensitive which means . They act like combinatorial logic

    x= y;

    z=x+a ;

    in this case the value of y is not stored in x hence the value of x at instance when the z = x+a will be 0 or unknown

    if (clk'event and clk = '1' ) then

    x=y ;

    end if

    z = x + a ;

    in this case x would work like a register and store the data at every clock tick .

    Thats the reason you dont fine any output The code you have typed out is not a synthesizable code .

    With regards

    Vintu

  • RELEVANCY SCORE 3.93

    DB:3.93:Programmatic Placement Of Fir Compiler 7.1 With Interpolation Filter Results In Erroneous Output 9m



    I have a reproducible issue with programmatically adding anFIR Compiler 7.1block to a masked subsystem. Most operations work just fine but I found an issue that is perplexing. Specifically, I add anFIR Compiler 7.1block using mask initialization code via an external matlab function (as specified in the system generator documentation). Everything gets placed and connected correctly and the block simulates with no error messages. However, the output is incorrect based on my calculation of the input convolved with the coefficients.

    This problem has plagued me until I decided to descend into the masked subsystem and edit the FIR Compiler manually. After I do this and save, the output is correct. I have verified and reverified that the parameters are the same both before and after I do the edits. I have tried to add the FIR using multiple methods including with xBlock as well as add_block.

    At this point this problem limits my ability to do programmatic creation of system generator subsystems. Additionally, I have only found this issue withFIR Compiler in interpolation filter mode.

    Here is my setup:

    System Generator 2014.2

    Matlab 2014a

    Any advice would be greatly appreciated.

    DB:3.93:Programmatic Placement Of Fir Compiler 7.1 With Interpolation Filter Results In Erroneous Output 9m


    Hi

    Can you check with latest version of Vivado 2014.4 and Matlab2014a or 2014b.

    Also attach a test case and script files if possible to look into the issue.




    Regards,Satish--------------------------------------------------​--------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful.--------------------------------------------------​-------------------------------------------

  • RELEVANCY SCORE 3.89

    DB:3.89:About Fir V5.0 1x



    When I use the Fir Compiler V5.0 , the output of the fir is ofen zero.

    I use one signal which is generated in DSP as the sclr of Fir,and I can see it in chipscope.

    thank you .

    DB:3.89:About Fir V5.0 1x


    You need to provide actual data for anyone to be able to help you.

    I.e. chipscope plots, .xco files, code, testbench, pictures, etc




    www.xilinx.com

  • RELEVANCY SCORE 3.87

    DB:3.87:Fir Compiler With Ise14.4 And Xinq ca



    Hi all,

    according to given link FIR compiler for v7.1 is based on vivado 14,1 it means we can't use ISE 14.4 with this??

    I want a solution for FIR compiler with 14.4 ISE, which version i should use for this??

    Secondly anybody has an idea to integrate this IP in zynq (zed) device??

    Thanks,

    Umair







    Solved!
    Go to Solution.

    DB:3.87:Fir Compiler With Ise14.4 And Xinq ca

    Thanks vanitha. . . Now I m goinf to post discussion about way to import IP into xps project from core generator. . .

  • RELEVANCY SCORE 3.87

    DB:3.87:Super Sample Filter Implementation (Fir Compiler 7.2) x9



    Recently installed Vivado 2014.3 system edition, because I was interested in the newly added support for Super Sample Filters.

    Running Vivado 2014.3 with Matlab R2014a.

    I am having trouble changing the FIR compiler to be configured as a Super Sample Filter. I can't seem to find the setting anywhere in the options. Anyone try this yet?

    DB:3.87:Super Sample Filter Implementation (Fir Compiler 7.2) x9

    Clarification for my understanding (putting it into my words). The impulse train, is essential an impulse at each of the vector outputs to obtain the coefficients used in each leg of the polyphase filter?If my assessment is correct, wouldn't I expect that the impulse response to be phase independant (as seen in the manual implementation)? Since it is essentially a single rate filter in parallel. And the output should be recombined.

  • RELEVANCY SCORE 3.81

    DB:3.81:Problem With Reloadable Fir Filter 88



    Hi every one. I have a problem with reloadable FIR in sysgen. I have 2 RAM, one for input of filter and one for coefficient of FIR filter. My sampling period is (1.09375e-7). When I add ceff_WE and coeff_LD with same sampling period, sysgen give me error which is:

    ERROR: Incorrect rate on coefficient reload port: COEF_DIN, COEF_LD, COEF_WD must all be at the core operating rate (1).Error occurred during "Rate and Type Error Checking".

    Basically I don`t know how to specify the sample rate of FIR filter.

    Would you mind help me?

    Regards,

    Arash







    Solved!
    Go to Solution.

    DB:3.81:Problem With Reloadable Fir Filter 88

    First, you should make sure to use normalized rates when working with sysgen.Anyway, you can specify the rate of the filter when you configure the core. But you need to make sure you drive each of the interfaces with the appropriate sampling rate. To see the rate of each port, open the sysgen token, go to the general tab, and select 'Normalized Sample Periods' for the block icon display.



    www.xilinx.com

  • RELEVANCY SCORE 3.80

    DB:3.80:Importing .Coe File Into Fir Compiler kj



    I need to pass the coefficients I have generated using fda tool to the fir compiler 5.0 in system generator.

    I have already generated the .coe file but dont know how to import it into the fir compiler.

    Please help

    Thank you.

    DB:3.80:Importing .Coe File Into Fir Compiler kj


    The first page of the coregen GUI allows you to specify either a coefficient vector right into the GUI or point to a .coe file.




    www.xilinx.com

  • RELEVANCY SCORE 3.79

    DB:3.79:Unable To Implement A Hilbert Filter With Fir Compiler cj



    I am trying to generate a Hilbert filter using the FIR compiler in coregen. I have created my coefficients using matlab and generated my coe file. But under coefficient structure all I have for options are inferred, Non-symmetric, and negative symmetric. What am I doing wrong?

    DB:3.79:Unable To Implement A Hilbert Filter With Fir Compiler cj


    It's in the 'Filter Type' dropdown, not the architecture:




    www.xilinx.com

  • RELEVANCY SCORE 3.68

    DB:3.68:Problem With Aero In Windows 8 d1


    at fir

    DB:3.68:Problem With Aero In Windows 8 d1

    Hi,

    Due to this is Windows 7 forum, please post a new thread in
    Windows 8 forums.

    Regards.If a post solved your problem, click “Mark as Answer” on the post. If a post helped you, click Vote As Helpful on the left side of post.

  • RELEVANCY SCORE 3.66

    DB:3.66:Fir Compiler Doubt p3



    Hi,

    I am using FIR compiler V5.0 in reloadable coefficient mode.

    In the core options, I use 1.15 representation for data and 1.15 for coefficients (given as 16 bits for coefficients with 15 fractional bits). I need to develop a FIR filter with 72 coefficients.

    I see that the number of output bits is 39 -- [38:0], but when we accumulate 72 values, logically it seems 38 bits are sufficient with 8 bits for integer and 30 bits for fraction.

    Also the core shows 30 bits for fractions after choosing the options.

    If I need to truncate my output to 16 bits, which bits should I choose.

    Can someone explain what am I missing ?

    Any help is highly appreciated ..

    Thanks in advance

    DB:3.66:Fir Compiler Doubt p3

    the compiler is not as using all the information. 16x16 gives you 32 bits + 7 bits for the accumulation = 39 bits.



    ---------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.---------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.65

    DB:3.65:Fir Ip Core Testing kx



    Hi ,

    I am using the Interpolation feature of the FIR IP compiler . We tested few patterns to verify the working of the FIR for interpolating a signal from 10 MSPS to 80 MSPS , PBand = 2 MHZ and SBand = 10 MHz . Do let me know a good test pattern to test this kind of application and and expected output pattern .

    I tried testing the system by using a constant value as the input , What I got as the output is a contant value with some bumps (small oscillations near the constant value ). I have attached the figure along wiht this mail . Do let me know if this output looks alright to say that the module is working fine .










    Attachments:







    14_7ZEROS.pdf ‏16 KB

    DB:3.65:Fir Ip Core Testing kx

    Noting that FIR = Finite Impulse Response, useful results can be got when inputting an impulse into the filter.



    ------------------------------------------"If it don't work in simulation, it won't work on the board."

  • RELEVANCY SCORE 3.65

    DB:3.65:Fir Compiler Cycle Latency Jumps With More Than One Channel 9c



    I am using FIR Compiler to create a filter.

    I have 8 channels of data to push thru it.

    I could use 1 channel and 8 paths or I could do something like 4 channels and two paths (which in some ways fits my data flow better)

    The issue is the “Cycle Latency”

    With 1 channel and 8 paths I have a “Cycle Latency” of 10 see below:

    With 4 channels and 2 paths I have a cycle latency of 66675 see below:

    Is this a bug, why does the “Cycle Latency” increase so much?

    DB:3.65:Fir Compiler Cycle Latency Jumps With More Than One Channel 9c


    I am using FIR Compiler to create a filter.

    I have 8 channels of data to push thru it.

    I could use 1 channel and 8 paths or I could do something like 4 channels and two paths (which in some ways fits my data flow better)

    The issue is the “Cycle Latency”

    With 1 channel and 8 paths I have a “Cycle Latency” of 10 see below:

    With 4 channels and 2 paths I have a cycle latency of 66675 see below:

    Is this a bug, why does the “Cycle Latency” increase so much?

  • RELEVANCY SCORE 3.65

    DB:3.65:Supporting Decimation Changes On-The-Fly 79


    Hi All,

    It seems the System Generator FIR Compiler blocks do not provide for a reloadable decimation (or interpolation) factor, is that correct? My application requires that I be able to change the decimation on the fly (and the decimation is not necessarily a power of two). I see these as options:

    1) Implement N FIR filter blocks, each with its own sample rate change;

    2) Use the FIR in single rate mode, followed by N DownSample blocks (each with a unique downsample factor) in parallel;

    3) Use the FIR in single rate mode, followed by an MCode block that can downsampleby a programmable factor;

    4) Use a CIC filter (which does support programmable sample rate changes) in combination with a FIR.

    Has anyone had to deal with this problem? Is one of the above “solutions” better than the others? Is there some alternative anyone can suggest?

    Thanks,

    L M C

    DB:3.65:Supporting Decimation Changes On-The-Fly 79

    Hi All,

    It seems the System Generator FIR Compiler blocks do not provide for a reloadable decimation (or interpolation) factor, is that correct? My application requires that I be able to change the decimation on the fly (and the decimation is not necessarily a power of two). I see these as options:

    1) Implement N FIR filter blocks, each with its own sample rate change;

    2) Use the FIR in single rate mode, followed by N DownSample blocks (each with a unique downsample factor) in parallel;

    3) Use the FIR in single rate mode, followed by an MCode block that can downsampleby a programmable factor;

    4) Use a CIC filter (which does support programmable sample rate changes) in combination with a FIR.

    Has anyone had to deal with this problem? Is one of the above “solutions” better than the others? Is there some alternative anyone can suggest?

    Thanks,

    L M C

  • RELEVANCY SCORE 3.65

    DB:3.65:Loading Filter Coefficient File Into Sysgen Fir Compiler 5.0 dm



    I am trying to load a coefficeint data file into SYSGEN 13.1 FIR Compiler 5.0. when I type

    load('coef_data.coe') into the Coefficient Vector: field, I am getting an error.

    I can do this in the core generator without any problem.

    Can this be done in SYSGEN also?

    Thanks

    Mohan

    DB:3.65:Loading Filter Coefficient File Into Sysgen Fir Compiler 5.0 dm


    use FDATool for creat filter coefficient file, then type "xlfda_numerator('FDATool')" into the Coefficient Vector.

  • RELEVANCY SCORE 3.64

    DB:3.64:Fir Compiler Implementation 7k



    Hi,

    I am very new with IP integration, right now I have custom IP of ADC which is connected with DMA but i want to implement FIR filter on the data from ADC. I have generated the core from core generator and created the custom peripheral in xps project, but i cant see the user logic file of this in HDL folder, i have selected AXI stream.

    Secondly after importing the generated ngc file to the new preipheral, there is no bus interfaces.

    I am following below tutorial.

    http://www.fpgadeveloper.com/2008/10/integrating-blackbox-into-peripheral.html

    I am implementing this on Zynq(zed).

    Thanks,

    DB:3.64:Fir Compiler Implementation 7k


    and there is no comments about

    Component declaration
    Componentinstantiation in the top level file of the new peripheral template.

  • RELEVANCY SCORE 3.63

    DB:3.63:Fir Compiler 5.0 Problem j9



    Hi,

    I've just imported a project from ISE 14.6 to Vivado 2013.3.

    This project uses a FIR compiler 5.0, and I use the generated netlist (ngc) as input to Vivado.

    Vivado has synthetized and placed routed the design successfully, but looking at the area report, it looks like the FIR compiler has been optimized away. The design uses several other IPs, and I don't have this king of issu with them, meaning my compile flow is correclty working.

    Can I use my generated IP FIR compiler 5.0 with Vivado, or do I have to upgrade to another version of the FIR Compiler ?

    Thanks,

    Florian.

    DB:3.63:Fir Compiler 5.0 Problem j9


    F,

    What do the (verbose) reports say? If it is actually optimized away, then it is not connected to anything (unused). That is completely different than being incompatible between ISE and Vivado.




    Austin LeseaPrincipal EngineerXilinx San Jose

  • RELEVANCY SCORE 3.63

    DB:3.63:10.1 Core Generator - Fir Compiler V4.0 Problem: I Cant Parameterize Anything 3j



    Hello

    If I open the FIR editer all field are grey shaded, that is, I am not able to parameterize anything with the exception for the path entry of theCOE File.

    Any help appreciated.










    Attachments:




  • RELEVANCY SCORE 3.63

    DB:3.63:Limits On Dsp48: Fft 5.0 Compiler sx



    Hi,

    I am building a system using system generator.

    I am using vertex -4 .

    I tried to implement an FIR filter with 267 taps using FIR 5.0

    But, to my strange, it says,

    " core requires more DSP48 elements ....... "

    How to overcome this problem?

    what if we need to design a filter with more than 250(order) filter taps?

    Kindly help me..

    DB:3.63:Limits On Dsp48: Fft 5.0 Compiler sx


    I would recommend upgrading to 13.3. If there is a strong reason you want to stay with 12.4 and your target device has plenty of DSP48, you can force the FIR compiler to use non-sysmetric coefficient structure, which allows you to select multi-column DSP48 for the filter.

    santhapurharsha wrote:

    Thank you Jim...

    Does it mean, we cant implement a filter with 250 coefficients, using FIR Compiler v5.0 .. using previous versions of ISE ..

    Should i change to 13.3 to overcome this problem??

    Is there any other way to overcome this, without changing my curent version???

    Thanks

    Sriharsha S




    Cheers,Jim

  • RELEVANCY SCORE 3.63

    DB:3.63:Doubt Regarding Fir Compiler jp



    We are a small team from IIT Madras working on building LTE products.

    I am using the FIR compiler for one of the blocks but as per its datasheet I understand that the coefficients need to be

    given as a .coe file. I have tried a single channel filter with it and its working fine.

    Now instead of this .coe file, can I store coefficients in the FPGA's memory and use them. My requirement is to build a filter whose taps keep changing wrt time as per some algorithm ( adaptive algorithm say which changes filter taps say for every x secs).

    Are there any other commercial IP cores available which provide support for adaptable filter coefficients ?

    We are willing to purchase one such if available.

    We use Virtex 5 device for our testbed.

    Thanks,

    kishore prahlad

    DB:3.63:Doubt Regarding Fir Compiler jp


    http://www.xilinx.com/support/documentation/ip_doc​umentation/fir_compiler/v6_3/ds795_fir_compiler.pd​f

    See pages 24, 62-64 for details on using the interface.

    Can you post a screenshot of the behavior you are seeing?




    www.xilinx.com

  • RELEVANCY SCORE 3.62

    DB:3.62:Filter Delta Response kx



    Hello:

    I am trying to generate a Half-Band Filter using the FIR Compiler 6.3.

    In page 50 of this datasheet, there is a set of coefficientes of half-band filter:

    radix=10;

    coefdata=220,0,-375,0,1283,2047,1283,0,-375,0,220;

    I put theses values in the FIR Compiler and other configurations are:

    Filter type: single rate

    channel sequence: basic; number of channels=1; number of paths=1; sample period = 1;

    coefficient structure = half band; signed; truncate LSBs.

    When i have the filter, i try to test it, the input data is a delta = [1, 0, 0 , 0 ...... 0]; So in the output i expect to see the coefficients of filter because h convolution delta = h. The problem is that i can not see theses coefficients, i see other number without any relation with these coefficients.

    What am i doing wrong? Are there any mistakes in my configuration?

    Thank you.

    DB:3.62:Filter Delta Response kx

    yes this is good catch . you must have to keep the mif file in the same folder



    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.61

    DB:3.61:Sysgen Fir Compiler Block In Fixed Fractional Rate Mode 3x


    I'd like to use Sysgen's Fir Compiler Block in the fixed fractional rate mode.
    Currently Sysgen (9.1) supportsonly integer upsample or downsample modes.
    Is there any plan to support fixed fractional rate mode in the upcomming releases of Sysgen?

    Is it possible to generate Fir with the fractional rate in CoreGen and then simulate it in Sysgen as a HDL blackbox?
    Whatshould I do to include generated core into the Sysgen model?

    DB:3.61:Sysgen Fir Compiler Block In Fixed Fractional Rate Mode 3x

    To submit a formal request to add support for this feature you should open a webcase with Xilinx technical support here:http://www.xilinx.com/support/clearexpress/websupp​ort.htmThere's no technical reason that you could not use an HDL black box to bring in a FIR Compiler from Core Generator which uses a fixed fractional rate change as long as all the rates involved in the model can be derived from integer multiples of the system period.

  • RELEVANCY SCORE 3.59

    DB:3.59:Suggestion To Fir Compiler Maintainers At Xilinx... 8k



    Infer symmetry in floating-point coefficients after quantization, not before. :smileymad:

    DB:3.59:Suggestion To Fir Compiler Maintainers At Xilinx... 8k


    This is an interesting request.

    Have you seen a problem where you couldn't get symmetry before rounding, but you would have after rounding. If so, then please upload that COE file.




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 3.56

    DB:3.56:Problem Regarding To Fir Compiler V2.0 kc


    Hello,
    I am trying to simulate for FIR complier v2.0. I am using System Generator 9.1 and it's example which is given in ..........

    ..sysgen_tree/examples/getting_started_training/lab7/. I am using this lab7 example........ But when I simulate with FIR bloack it gives me error........which is given below........

    --------------------------------------------------------------------------Summary of Errors:Error 0001: Internal Error Block: 'lab7/FIR Compiler v2_0 '--------------------------------------------------------------------------

    Error 0001:

    Reported by: 'lab7/FIR Compiler v2_0 '

    Details:An internal error occurred in the Xilinx Blockset Library.

    Please report this error to Xilinx (http://support.xilinx.com),in as much detail as possible. You may also find immediate helpin the Answers Database and other online resources at http://support.xilinx.com.

    Error occurred during "Rate and Type Error Checking".

    --------------------------------------------------------------------------

    How can I solve this error.........Please help me......

    Thank you,

    Krunal

    DB:3.56:Problem Regarding To Fir Compiler V2.0 kc

    This sounds like there is a problem with your tools setup. Please create a WebCase with Xilinx technical support to debug this specific issue.

  • RELEVANCY SCORE 3.53

    DB:3.53:Fir Compiler Filter Analysis 93



    What is the formula to set Passband Stop band normalized values in FILTER ANALYSIS window of FIR Compiler? What are the optimal values?

    DB:3.53:Fir Compiler Filter Analysis 93


    Not sure what exactly are you asking about. The normalized values are calculated as fpass/(fs/2) or fstop/(fs/2). In other words, fs/2 is normailized to 1 where fs is the sampling frequency.

    ravics wrote:

    What is the formula to set Passband Stop band normalized values in FILTER ANALYSIS window of FIR Compiler? What are the optimal values?




    Cheers,Jim

  • RELEVANCY SCORE 3.52

    DB:3.52:Chan_In And Chan_Out Signals Disappearing In Fir Compiler 4.0 pa



    In FIR compiler 4.0 in System generator 10.1.03, when I set the filter type to decimation with multiple number of channels, outputs chan_in and chan_out disappear when the decimation rate value is greater than 64. Why does that happen? I need those signals.

    Ivan

    DB:3.52:Chan_In And Chan_Out Signals Disappearing In Fir Compiler 4.0 pa


    I don't have SysGen 10.1.03 available to test on but the FIR Compiler 5.0 in 12.2 appears to be working fine. I tested with Filter Type=Decimation, Decimation Rate Value=70, and # of Channels=10.

    Looks like maybe something specific to v4.0...

  • RELEVANCY SCORE 3.49

    DB:3.49:How To Design A Fir Filter Using Sysgen On Xtremerdsp Kit j8



    hi all!i using a FIR Compiler 4.0 sysgen block for design, but to appear error.

    how to design a FIR filter on XtremerDSP kit?

    help for me!










    Attachments:







    do_an_sua.mdl ‏127 KB

    DB:3.49:How To Design A Fir Filter Using Sysgen On Xtremerdsp Kit j8


    i'm start sysgen from programs/matlab/Simulink.

    my design running on the windows 7 with ISE 10.1, Matlab 2007b.

    I do tried it, but no running netlist file

  • RELEVANCY SCORE 3.47

    DB:3.47:Fir Compiler 6.0 Fractional Output Error m3



    Hello,

    I am using FIR compiler 6.0 in the following way:

    http://www.xilinx.com/support/answers/29138.htm

    As you can see the input to the compiler is a UFIX_8_8.

    The mask parameters are [0.0082 0.0152 0.1166 0.0152 0.0082].

    The FIR block is set to decimation with a factor of 5.

    Now, whenever the actual value of the FIR block should be larger than 0.125 (i.e. 2^-3 ) the FIR output is much too large.

    It seems that whenever the value needs to set any of the first three fractional bits(i.e. 2^-1, 2^-2, 2^-3) to 1 it sets ALL three bits to 1.

    Is this a bug of the FIR compiler 6.0? Does it have anything to do with the bugfix of FIR compiler6.2 ?

    BUGFIXES

    CR 581746 Fractional decimation, single channel BRAM data memory output error

    http://www.xilinx.com/support/answers/29138.htm

    If it is not a bug, what am I doing wrong and how can I solve the problem if it is a bug?I can not use 6.2, since SysGen 13.1 crashes for me, as described in

    http://forums.xilinx.com/t5/DSP-Tools/MATLAB-and-or-System-Generator-crash-on-FIR-Filter-5-0-Compiler/td-p/138936

    DB:3.47:Fir Compiler 6.0 Fractional Output Error m3


    This could be the issue, but I'm not certain based on your description.

    I recommend you update to 13.2 or later, and see if you are still seeing problems with the latest tools and IP.

    I know you had some other issue, but the newer tools should do better.

    Also remember that the sample times colors are not supported by SysGen Blocks.

    AR 23220




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 3.44

    DB:3.44:Fir With Mac Generated By Ip Core Gen Filter Compiler V3.2: Width I/O Problem s9


    I want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter.

    My problem is about I/O in the block of filter generated from IP core generator.

    I would the same bit lenght of the input, in output, for connections I/O. In input i have DATA_IN [9 0] and instead DATA_OUT [30 0]. I would [9 0] for output! FILTER is a FIR 21 TAPS with MAC, is there a solution for truncate bit?

    Can you help me?

    Thanks so much.









    Attachments:







    FILTER_SEL_COEF3.vhd ‏1366 KB

    DB:3.44:Fir With Mac Generated By Ip Core Gen Filter Compiler V3.2: Width I/O Problem s9


    I'm working for a thesis, is there a solution for my problem, please? Must Ioperate on the code, manually? What? Isn't an automatic option for filter output truncation (output rounding mode) for my spartan II xc2s200 ?

    Is there a block diagram which describes the MAC structure of filter and specify the code? for example, what is the structure which contains code block VCC, GND, FDCE, XORCY, MULT_AND, LUT4, etc.... block diagram connections?? (The code is generated from filter compiler code, in the datasheet there is generic mac structure!) The code is in attachment.

  • RELEVANCY SCORE 3.43

    DB:3.43:Root Raised Cosine Filter With The Help Of Fir Compiler z9



    hi all,

    I'm doing this for a school project where I need to implement a root raised cosine filter (RRC filter) in Kintex 7 after the Mapper IP block.

    My structure is like this:

    bit sequence - Mapper - RRC filter - fifo - 16 bits DAC - Quadrature Modulator

    ************

    I'm currently trying the FIR Compiler. I have several questions:

    1) the coefficient vector: e.g. 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4​,0,6

    when designing filter in matlab is floating point double, which format is this coefficient vector in this FIR Compiler? and how to convert from matlab format to this format?

    2) is the filter implemented by FIR Compiler serial or parallel filter?

    2) In my project I want to calculate the filter coefficient when doing sythesis, so that I can change the filter just be reset the parameters in verilog or VHDL code. Is there any example or algorithm to calculate the RRC filter coefficients?

    Thanks for any help and advice,

  • RELEVANCY SCORE 3.43

    DB:3.43:Fir Compiler 6.3 Synthesis Report 3k



    Hi All,

    I am trying to build a FIR filter with 15 taps. I have successfully generate IP and instantiate the IP in an verilog module. The synthesis is successful without warning. However, I have seen through the synthesis report, there is something wrong with Device Utilization Summary. Only the Number of bonded IOBs and Number of BUFG/BUFGCTRLs show up. Does anyone know what's going on here?

    Thanks,

    Yi

    DB:3.43:Fir Compiler 6.3 Synthesis Report 3k


    Hi,

    In general we expect Multipliers or DSP48 blocks aslo to be occupied .

    In coregen based on your core configuration resorce estimation summary will vary .

    You may compare it against the synthesis report.

    If they are not matching at all, cross check if you are driving proper inputs to the core and the outputs are not trimmed of by any chance.

    Regards,

    Vanitha.




    ---------------------------------------------------------------------------------------------Please do google search before posting, you may find relavant information.Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

  • RELEVANCY SCORE 3.40

    DB:3.40:Fir Compiler 6.3, Error 0001, Xilinx Example Lab 7 dj



    Hello,

    Simulation of band pass with FIR Compiler 6.3 (Xilinx Example lab 7) produces Error 0001.

    Can anyone help?

    Code generation completes with System Generator 14.7.

    Regards tma










    Attachments:







    FirComp6.3_error0001.zip ‏477 KB

    DB:3.40:Fir Compiler 6.3, Error 0001, Xilinx Example Lab 7 dj

    Moving to correct board



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.37

    DB:3.37:Settings In Matlab And Fir Compiler k3



    Hi DSP Engineers,

    As I am purely FPGA design engineer, I am finding difficulty to understand some the things in DSP.

    1) I am using XADC for converting analog input (sine wave 0V to 1V with 31KHz).

    2) Corresponding to external voltages, I am getting HEX"000" to "FFF" 12-bit binary output of XADC.

    3) Now with this XADC output, I would be able to easily reconstruct a sine wave.(at least I can understand that how is the input coming)

    4) This XADC output is fed to FIR filter input, The .coe file is generated from MATLAB with following settings in MATLAB.. Filter Type =

    Low Pass , Equiripple type,

    Frequency Specification =

    Fs = 961KHz , Fpass = 33 KHz, Fstop = 33.5 KHz

    Magnitude Specification = in dB

    Apass = 1 , Astop = 80

    After converting to fixed-point, the coefficients are generated.

    5) This .coe file taken as an input in FIR complier, Settings done in FIR compiler..

    In Filter Analysis Tab =

    Passband range 0 to 0.06867846 (eqivalent of 33KHz in pi radians)

    Stopband range 0.069719043 (eqivalent of 33.5 KHz in pi radians) to 1

    Then most of the settings are kept default except data input = 12 bit unsigned

    6) Now in simulation, the FIR output is coming in 21 bits and is not in understandable format as its input.

    Questions:

    1) Does I am doing correct settings in MATLAB??

    2) Does I am doing correct settings in FIR Compiler??

    3) As XADC output corresponds to external voltage levels, How I can determine the external voltage level by analyzing the FIR filter output?

    I am sure many of you might have worked with similar designs, so please help me to understand the filter output and reconstruct the input.

    Thanks

    Prashant

    DB:3.37:Settings In Matlab And Fir Compiler k3


    Can you post some of your results so we can see the same behavior that you are observing? Also, can you post your .xco file for the filter?

    Watch out for input/output/coefficient data types and make sure to use a good amount of dynamic range for your signals (i.e. 'use all the bits' by normalizing).




    www.xilinx.com

  • RELEVANCY SCORE 3.37

    DB:3.37:Multiple Filters jc



    Hi,

    I'm new to the ISE design suite and FIR compiler. I am currently using the ISE 12.1 and FIR compiler 5.0. I figured out how to add an FIR compiler as a source to my existing project. My end goal is to apply one filter to the incoming data and afterwards apply a hilbert transform. Is it possible to for me to specify what order the filters are applied?

    As well, I am curious for future development, whether or not I can change the filter settings without having to recompile the entire project? Or will I have to use flash memory on the board to access different preset configurations with different filters?

    Thanks in advance for the help!

    DB:3.37:Multiple Filters jc


    I tried to implement this FILT_SEL. My coe file has two sets of coefficents one right after the other. If I wanted to switch between the two sets, I wouldn't need to use the reloading interface, correct? I would simply set FILT_SEL to the set I want. How are the sets differentiated by the filter select? Are they numbered 0 to N? And if I wanted to set the filter to the second set, I would have to pass in FILT_SEL = 1? Also, is there any delay to the use of a new filter? I want to be able to change the filters as the data continues to come in. I also tried to use the COEF_FILT_SEL port, but had trouble with that as well. If anyone can help me, I would really appreciate it.

    Thanks,

    dlui

  • RELEVANCY SCORE 3.37

    DB:3.37:Using The Polyphase Filter Bank In The Fir Compiler f9



    Does anyone have experience with the FIR Compiler LogiCore. I am attempting to design a Polyphase FFT. I recently found out that the FIR Compiler allows the user to implement a Polyphase Filter Bank, which is directly compatible with the Fast Fourier Transform LogiCore. Previously, I designed my own Polyphase Filter Bank in System Generator out of multipliers, adders, etc., and my design works with the FFT core to produce correct results. The problem with my design is it is not very fast and updating it takes time.

    My problem: Setting up the Polyphase Filter Bank using the FIR Compiler LogiCore appears to be simple, but it produces the wrong outputs. I have set up the Filter for 8 channels with 4 coefficients each. The output appears to output data for 4 samples, then zeroes for 4 samples, then data for 4 samples, then zeroes for 4 samples, and so on.

    Anybody have any suggestions. Thanks!

    DB:3.37:Using The Polyphase Filter Bank In The Fir Compiler f9

    When FFT is connected to Ployphase filter bank transmitter, FIR provides 2^n channels, this something corresponds to FFT points, so FFT only needs to be 1 channel.

  • RELEVANCY SCORE 3.36

    DB:3.36:Fir Compiler 5.0 Gain sa



    Hello!

    I have a problem with the FIR-compiler that results in attenuated signals at the output. My intention is to create different FIR-filters all with Matlab and exporting the coefficients via coewrite() and putting them into the Xilinx FIR compiler. I have a 16-bit signed input and wan't a 16-bit output. (I configure the FIR-compiler output bits to 16 and select some rounding). I also have 16-bit coefficients with a fraction length of 15.

    Now, the problem is that even if I create a Flat response filter in Matlab (0dB) gain and put the coefficients into the compiler I get an attenuated signal at the output. This is weird, is there something I'm missing?

    The response curve in the FIR-compiler looks exactly the same as in matlab except that it shows a positive gain of about 90dB on the Y-axis throughout the frequency range. I think that the compiler somehow interprets the coefficients as whole integers? Even though they are fractions with a fraction length of 15 bits.

    Regards,

    Jonas

    DB:3.36:Fir Compiler 5.0 Gain sa


    Try exporting your filter in decimal:

    coewrite(hd, 10, 'mycoefile.coe')

  • RELEVANCY SCORE 3.35

    DB:3.35:Msi K8t Neo2 Fir With Twinx 3200xlpl Cas2 Problem fc


    I've got a problem with the Corsair Twinx pc3200Xlpl 1024mb.

  • RELEVANCY SCORE 3.34

    DB:3.34:Fir Compiler 7.1 Problem On Vivado 2013.2 f9


    Hi,

    I've just imported a project from PlanAhead 14.4 to Vivado 2013.2 (wich shuld be the first release that supports Zynq7000 hw).

    In Vivado I've recreate some IP that couldn't be updated.

    The FIR compiler 7.1 has given me some problems (I've used fir compiler 5.0 to generate the IP the first time):

    All the net names are changed and the bit input number shuld be now multiple of 8. Reading the dasheet I've correctly mapped all old ports to new ports and followed all the steps suggested:

    ND is mapped to s_axis_data_tvalid
    RFD is mapped to s_axis_data_tready
    RDY is mapped to m_axis_data_tvalid
    ....
    .....

    http://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_1/pg149-fir-compiler.pdf
    (page 120)

    but debugging the nets I've found that:s_axis_data_tready (which is a filter output that goes high when the IP is ready to accept new data) doesn't move, and the synthetizer puts this signal to ground.

    Another thing that I've noticed is that the first time I've tried to debug, in the debug config window, Vivado did not recognized automatically a clock for the output data of the filter, so I've imposed the same clock net of the other ports...but this thing seems strange...

    Can someone help me?

    Thanx a lot.
    Matteo

    DB:3.34:Fir Compiler 7.1 Problem On Vivado 2013.2 f9


    I've checked everything once again but it doesn't work.

    Here il the instantiation code of the filter:

    I_FIR_highpass_PCR_0 : FIR_highpass_PCR PORT MAP ( aresetn = not FIR_sclr, aclk = CLKM, s_axis_data_tready = FIR_rfd_0, s_axis_data_tvalid = FIR_nd_0, s_axis_data_tdata = FIR_din(30) "0" FIR_din(29 downto 0), m_axis_data_tvalid = FIR_rdy_0, m_axis_data_tdata = FIR_dout_a );

    FIR_dout_0 = FIR_dout_a(39) FIR_dout_a(37 downto 0);

    FIR_d_in is a 31 bit std logic vector (bit 30 is the sign) and FIR_dout_0 is a 39 bit std logic vector (bit 39 is the sign). So I've put an extra zero to the input (because now filter designer 7.1 wants only multiple of 8 bit signals) and I've ignored the bit 38 of the output .

    before, in PlanAhead, the instantiation was:

    clk = CLKM, sclr = FIR_sclr, nd = FIR_nd_0, rfd = FIR_rfd_0, rdy = FIR_rdy_0, din = FIR_din, dout = FIR_dout_0

    and the filter was working correcly.

    I've attached the xci file of the filter and a screenshot where you can see that the port s_axis_data_tready is seen as a constant in post synthesis net list.

    Thanx.

    Matteo










    Attachments:




  • RELEVANCY SCORE 3.33

    DB:3.33:Audio Weighting A,C Etc. s1



    Hello!

    Just wondering if anyone has implemented audio Weighting filters such as A- and C-weighting with the Xilinx FIR-compiler? My question is that is it possible to implement (approximate) these using FIR coefficients as every tool I find in matlab uses IIR-type filters for all A and C audio weighting. This is natural because according to Wikipedia the weighting transfer functions have poles and not only zeroes as with a FIR-filter (Although the weighting functions are not defined by a transfer function).

    One of my approaches that I was thinking of is to try to approximate the weighting curve with a FIR bandpass-filter of some sort.

    I would appriciate if anyone could help me out.

    Thanks,

    Jonas

    DB:3.33:Audio Weighting A,C Etc. s1


    Which setting (TAPS) are you using?

    How did you achieve your solution?

    From the theory you need to integrate over the frequencies with in this case the weight values

  • RELEVANCY SCORE 3.33

    DB:3.33:Problem With Fir Compiler cm



    Hi

    I am trying to design a lowpass FIR filter in system generator. But i am having problem with FIR complier. what does "ISE Simulator Simulation could not be started. It is possible that the system memory available for this process has been exhausted.Error occurred during "Simulation Initialization"." mean?

    How can i resolve this problem?

    Regards

    Yadav Shrestha

    DB:3.33:Problem With Fir Compiler cm


    It is hard to say based on this information. What version of sysgen? What version of matlab? Do you get this error when generating a netlist? Make sure you're launching sysgen from the windows start menu rather than matlab/simulink.

    See here for some other suggestions:

    http://www.xilinx.com/support/answers/44617.htm




    www.xilinx.com

  • RELEVANCY SCORE 3.32

    DB:3.32:Sink Block Wrong Display p1



    I am implementing a digital receiver for a radar system using System Generator 11.

    The receiver has several stages of downsampling.

    The problem occurs with the FIR Complier 5.0, regardless of the co-effs and etc i set the filter to Decimation, factor 5.

    The sampling before the FIR is at 125MHz therefore logically it is reduced to 25MHz after the filter which is confirmed by the sample time function in place.

    BUT....i have a sink (BFFT) attached to display the frequency response at the output, this does NOT show the correct bandwidth (0 to Fs/2) which should now be12.5MHz.

    INSTEAD it displays the original 125MHz (Fs/2 =62.5MHz).

    Does anyone know weather this is a bug with the FIR compiler or am i doing something wrong, i have tried a million things and asked everyone at work no one is sure.

    Thanks guys







    Solved!
    Go to Solution.

    DB:3.32:Sink Block Wrong Display p1


    I have fixed this problem. But i still belive the FIR filter has some fault with it.

    By placing a Delay block or Register after the FIR filter, it forces the right frequency display on the BFFT window

  • RELEVANCY SCORE 3.30

    DB:3.30:How Can I Get A Da Fir Filter In Virtex 5 ????? mf



    Because virtex 5 IP core don't provide DA fir filter in FIR compiler V3.2, so how can i get a DA fir filter?

    I find it's toohard to write codewithout IP core,could anybody give me some methord?

    THX a lot

    DB:3.30:How Can I Get A Da Fir Filter In Virtex 5 ????? mf


    You can use FIR compiler V3.2 also for designing any kind of filter

    Follow this procedure for using Xilinxfilter design core

    In matlab usefdatool for designing any kind offilter coefficient oruseavailable filter commands

    1. Command window fdatool

    design ur filter exportcoefficientinto workspace or into some file

    2. Write coe for XILINX FIR compiler core

    http://www.mathworks.com/access/helpdesk/help/toolbox/filterdesign/index.html?/access/helpdesk/help/toolbox/filterdesign/ref/coewrite.htmlhttp://www.google.com/search?hl=enq=convert+to+coe+filebtnG=Google+Searchaq=foq=

    3. Generate FIR core from Xilinx coregengive coe file path name and select appropriatecore option

    I it will solve your purpose

    Regards

    Balkrishan




    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.30

    DB:3.30:Latency Of Fir Compiler V6.3 ad



    Hello,

    I'm using the FIR Compiler v6.3 for one channel and 8 non-symmetrical coefficients; the coregen UI reports Latency 6, in XSIM it works at latency 6, but in hardware and in post-map simulation it works at latency 7.

    Is this a bug?

    DB:3.30:Latency Of Fir Compiler V6.3 ad


    Oh I found it, but I fail to simulate it. I get this error:

    ISim
    # run all
    Simulator is doing circuit initialization process.
    Finished circuit initialization process.
    at 550 ns(2), Instance /tb_fir/dut/U0/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
    at 650 ns(2): Error: pB
    ERROR: In process fir_compiler_v6_3.vhd:i_fir
    FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
    INFO: Simulator is stopped.

    It's a simple project with only one FIR without input fifo (8 coefs, cycle latency 6 reported), and trying to simulate the testbench.

    Any idea what happened?

  • RELEVANCY SCORE 3.30

    DB:3.30:Problem Regarding To Fir Compiler V2.0 9a


  • RELEVANCY SCORE 3.30

    DB:3.30:A Error With Fir Compiler V5.0 f1



    sir:

    I am implementing a fir filter in the virtex-4 sx35, and i use the ipcore of fir complier v5.0. I make the sample frequency is 40MHz and the clock frequency is 200Mhz, and the 3db bandwidth of the filter is 1Mhz. I construct the filter with DA architecture, and the filter type is Single Rate(PDA). The coefficient width is 16bits and the data width is 14bits , both of which are signed type. The coefficient length is 64. So,the output width is 36(16+14+log(64)). The error i confront is that , in the chipscope i can only view the dout[35:18], and the lower dout[17:0] was not recongnized by chipscope(when i use the "auto create-bus" function in the chipscope, i cannot find the lower 18bits). besides, the control signal "nd","rfd","rdy" also can not be viewed in the chipscope, even though i have take them to the .cdc file before.

    what's the possible reason for this question??

    the design summary of fir compiler is in the attachments.

    Thx










    Attachments:




    DB:3.30:A Error With Fir Compiler V5.0 f1


    sir:

    In the implementation log, I find the error as fllow. fir_instance1/instance1 is the instantiation of fir complier v5.0. what's the error mean?










    Attachments:




  • RELEVANCY SCORE 3.30

    DB:3.30:Fir Compiler 5.0 Problem sx



    Hi,

    I have used in my system generator mdl file FIR Compiler 6.3 and everything worked fine. My development board doesn't support 6.3, I had to migrate to 5.0. And when I try to simulate/generate design, I get this error:

    Error reported by S-function 'sysgen' in 'test/DSP/H_FIL/FIR Compiler 5.0 ':Error: Unknown container type

    How can fix this?

    Best regards,Darko T.

    Matlab: 2011b

    ISE: 13.4

    OS: Centos 5.6 32-bit

    Java: 1.6.0_22







    Solved!
    Go to Solution.

    DB:3.30:Fir Compiler 5.0 Problem sx


    I solved this problem. The problem was in the "scope" usage. I connected FIR Compiler 5.0 direct to the scope. When I insert "Gateway Out" between FIR and scope, everything works fine.

  • RELEVANCY SCORE 3.29

    DB:3.29:Sysgen 11.4, Fir Compiler 5.0 3z



    Hello everyone,

    I designed a system in System Generator and then tried to implement it on a ML507 Virtex5 FPGA.

    The problem is that System Generator creates two files for the FIR Filter component, one in VHDL and one in Verilog. I would like to use the VHDL file, but as soon as I try to create the Bit Stream, I get an error :

    ERROR:NgdBuild:604 - logical block 'my_cic_x0/fir_compiler_5_0_i/fr_cmplr_v5_0_74f73c​d5d06c22f4_instance/blk0000 0003' with type 'fr_cmplr_v5_0_74f73cd5d06c22f4_fir_compiler_v5_0_​xst_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fr_cmplr_v5_0_74f73cd5d06c22f4_fir_compiler_v5_0_​xst_1' is not supported in target 'virtex5'.ERROR:NgdBuild:604 - logical block 'my_cic_x0/fir_compiler_5_0_q/fr_cmplr_v5_0_74f73c​d5d06c22f4_instance/blk0000 0003' with type 'fr_cmplr_v5_0_74f73cd5d06c22f4_fir_compiler_v5_0_​xst_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fr_cmplr_v5_0_74f73cd5d06c22f4_fir_compiler_v5_0_​xst_1' is not supported in target 'virtex5'.

    The problem is that this "blk00000003" comes from the Verilog module. I still have the VHDL file, but I have no idea how to force Sysgen to use it.

    Any help would be appreciated.

    Regards,

    Valentin

    DB:3.29:Sysgen 11.4, Fir Compiler 5.0 3z


    Hi,

    yes i selected VHDL.

    I tried to change the platform and I think the problem is somehow connected with the Speedgrade of my device. The Virtex5 I am using is -1. SysGen implements the design if I select -2, but -1 causes problems.

    I will try out if I can find something else.

    Thanks for the advice.

    Regards,

    Valentin

  • RELEVANCY SCORE 3.29

    DB:3.29:System Generator 10.1.02 Fir Complier 3.2 9x



    HI!

    I'm using FIR complier 3.2 for interpolation (1:3). I'm getting the output signal (1:6) with 6 times interpolation. So I modified with Upsampling block (3x) + FIR compiler (1:1) for single rate, but still FIR compiler generate 2x interpolation output signal. I don't why. I guess that this is a bug?

    Anybody has similar experience?

    DB:3.29:System Generator 10.1.02 Fir Complier 3.2 9x

    use a delay block after fir compiler block. I am sure it will get u the required output.
    but still i do not know the reason may be others can help with that.

  • RELEVANCY SCORE 3.28

    DB:3.28:Fixed Fractional Interpolation Fir - Please Help Understand Fir Spec 19



    Hello!

    I have a signal sampled at 80 MHz and need to feed it to DAC running at 200 MHz. So I planned to interpolate with 5/2 rate. I am using FIR compiler v.5.0. I set interpolation to 5, decimation to 2. Then I selected frequncy specification. I set input sampling to 80 MHz. Coregen allows to set clock in 240..300 MHz range. I've chosen 240 MHz. When I simulate this FIR, samples are output every 4.16ns, i.e @240 MHz.

    Probably I misunderstood the core purpose. Please suggest, what I am missing? How do I get samples coming @200 MHz?

    Thanks.

    DB:3.28:Fixed Fractional Interpolation Fir - Please Help Understand Fir Spec 19


    Hello!

    I have a signal sampled at 80 MHz and need to feed it to DAC running at 200 MHz. So I planned to interpolate with 5/2 rate. I am using FIR compiler v.5.0. I set interpolation to 5, decimation to 2. Then I selected frequncy specification. I set input sampling to 80 MHz. Coregen allows to set clock in 240..300 MHz range. I've chosen 240 MHz. When I simulate this FIR, samples are output every 4.16ns, i.e @240 MHz.

    Probably I misunderstood the core purpose. Please suggest, what I am missing? How do I get samples coming @200 MHz?

    Thanks.

  • RELEVANCY SCORE 3.28

    DB:3.28:Need Help For Fir Filter jm



    Hi;

    I am a beginner to filter design and I want to implementFIR filter with 300 tap and complex coefficient value. I want to use this FIR filter for implement MATCHED filter in virtex-4 fpga. I designed this FIR filter in MATLAB and when I want to generate COE file for xilinx, process stopped and displayed error to create COE file with complex value for xilinx.

    Please help me to solve this problem and implement FIR and MATCHED filter.

    Regards

    DB:3.28:Need Help For Fir Filter jm


    can u please tell how cross correlation of two signals can be implemented by both DAFIR and also BY FIR complier.

    waiting for your reply

  • RELEVANCY SCORE 3.27

    DB:3.27:Hilbert Transform Using Fir Compiler And Fda Tool cx



    Hi,

    I am trying to design an Hilbert Transform to convert 16-bit data that we used to drive a regular DAC, to 16-bit I and Q data to drive a DAC with I and Q inputs to improve our signal performance and baseband filtering.

    (I am using a Virtex 4 at the moment but will be moving to a Virtex 6 for the new design)

    I used core generator with FIR Compiler V5.0 and, using the excellent datasheet with coregen, I copied the Hilbert Transform notes providing the coef data (-819,0,-1365,0,-4096,0,4096,0,1365,0,819), into the coefficient vector of FIR Compiler. This seemed to work OK.

    But I am now using FDA Tool in Matlab to try to generate a larger order Hilbert Filter.

    My problem is I don't know how to convert the coefficents generated by the FDA Tool (for example:

    -0.222066272080177 -2.08652071664799e-16 -0.207067108122115 1.30206236849937e-16 -0.634683409629885 0 0.634683409629885 -1.30206236849937e-16)

    into suitable coefficents for Core Gen FIR Compiler.

    I know I need to force the very small values to Zero, but what should I scale the rest of the numbers by to generate 16-bit coeff data?

    And, is FDA Tool the right thing to use (it allows export of the coeff data) or should I be using another filter design tool in Matlab?

    And, on a more general topic - any suggestions about how many terms I should be using?

    Many thanks, Jim







    Solved!
    Go to Solution.

    DB:3.27:Hilbert Transform Using Fir Compiler And Fda Tool cx


    Hello es,

    many thanks for the prompt reply,

    I can see the coeffs Ok:

    -0.00226818593342183 -1.33773708791948e-17 -0.00417491568177813 1.30261555193310e-17 -0.00683468973978054 -4.19582596789382e-17 etc.

    But how do I convert these to what Xilinx FIR Compiler requires?

    I know I have to force the small values to zero but how do I scale the rest of the values (I assume the coefdata needs to be in integers)?

    Thanks, Jim

  • RELEVANCY SCORE 3.24

    DB:3.24:Spartan 6 Fir Core Stops Producing Output After Certain Time x3



    Hello -

    I'm seeing an issue with a Spartan 6 design where I have a FIR compiler core instantiated. Using Chipscope, I'm able to see the output signals performing as expected, but after some time (10-20 seconds) the output signal becomes a random constant value and the "ready for data" signal stays low.

    The same code (same bit file) on a different Spartan 6board (same FPGA, same I/O used, but different alternate peripherals installed), produces correct results every time.

    My first thought goes to power issues (brown out, etc.), but after scoping the supplies, they are very clean and don't seem to dip at all after configuration.

    Has anyone seen anything similar where a FIR filter stops responding?

    Thanks!!

    Adam

    DB:3.24:Spartan 6 Fir Core Stops Producing Output After Certain Time x3


    It still seems like a timing-related issue to me. Are you sure that all of the inputs to the

    FIR core are synchronous to the clock? Do any of them come from off-chip without

    first going through a flip-flop inside the FPGA? If so, do you have OFFSET IN BEFORE

    constraints on these inputs? Remember that PERIOD constraints only check internal

    flop to flop paths.

    -- Gabor




    -- Gabor

  • RELEVANCY SCORE 3.23

    DB:3.23:Calculated Coefficients In Fir Compiler? x9



    For instance, I generate a non-symmetric FIR filter with 161 taps and a multichannel realisation with two channels.

    Trying to compute the number of utilised resources, the number of DSP48A slices yields:

    100MHz/12.5MHz = 8 cycles/input sample, 2 channels = 8/2=4 cycles/input sample

    161 taps/4 = 41 DSP slices

    However, the GUI shows a DSP48 usage of 42 DSP slices taking into account165 calculated coefficients.

    What exactly are the number of calculated coefficients?

    DB:3.23:Calculated Coefficients In Fir Compiler? x9


    my .coe file.

    Thank you!










    Attachments:







    bsd_filter.coe ‏4 KB

  • RELEVANCY SCORE 3.22

    DB:3.22:Fir Compiler With Variable Sample Rate fa



    I am implementing Digital Up Conversion on a Virtex 6

    lx75t so I'm looking to save space.

    I have 4 signals at 1,2,4 and 8 Msps - I am transmitting at 16Msps

    The 1 Msps case looks like this

    data in |-1Msps-|raised cosine pulse shaper|-1Msps-|halfband interpolator|-2Msps-|halfband interpolator|-4Msps-|halfband interpolator|-8Msps-|halfband interpolator|-16Msps-|data out

    I switch the halfband filters in when they are needed - and have 4 pulse shapers to switch in for the different rates.

    My question is this: is there a way to generate a FIR with the fir compiler which can accept switchable sampling rates, so as to only have the 8Msps filter, and the lower rates use the sampe MAC stages - thus saving DSP slices.

    DB:3.22:Fir Compiler With Variable Sample Rate fa


    Hi,

    basically yes (if you do it properly by using the CE inputs of the FFs).

    If you are working with System generator, the tool should apply the necessary sampling clocks automatically according to the signals sampling rate. However, I'm not sure what happens if you switch different signals at runtime on a DSP Macro which has a global CE and several pipeline stages.

    Have a nice synthesis

    Eilert

  • RELEVANCY SCORE 3.22

    DB:3.22:Fir Compiler 6.0 da



    hello,

    I am using a FIR compiler 6.0.In the Filter I am using a Interpolation rate of 12 and it was working good.But when i enabled the reset port it is not working either i give a "high" or a "Low" and if i disable the reset port it is working. What can be the problem?

    DB:3.22:Fir Compiler 6.0 da


    What specifically do you mean by 'it is not working.' What is it doing? Can you post some screenshots of the behavior and/or the design?




    www.xilinx.com

  • RELEVANCY SCORE 3.21

    DB:3.21:Problem Generating .Coe (Coefficients) File For A Polyphase Fir Decimator In Matlab 3c



    Hi everyoneI have been trying to generate a .coe file in MATLAB for the Polyphase Decimator Filter Structure for an FIR Compiler design as follows:

    Hlpf = mfilt.firdecim(...);hq = dfilt.dffir(hlpf.Numerator);

    set(hq, 'Arithmetic', 'fixed');coewrite(hq, 10, 'coefile');

    Though I could get a .coe file after this, I am unsure if what I did was correct. The mfilt.firdecim is a Direct Form FIR Polyphase Decimator structure while dfilt.dffir is Direct Form FIR structure. So, how do I generate coefficients for the Polyphase decimator structure for the FIR compiler?

    Any help would be greatly appreciated.

    Regards,Kumar Vijay Mishra.

    DB:3.21:Problem Generating .Coe (Coefficients) File For A Polyphase Fir Decimator In Matlab 3c


    Hello vizzie

    You can do the following :

    1)Design your filter in Matlab using FDA tool

    2)Click on " Set quantization parameters" on the left side of GUI

    3)Change "filter arithmetic" to Fixed point

    4)Click on the Coefficients tab to check the number of bits ( Numerator word length = 16 etc.).

    5)Change "filter arithmetic" back to Full precision

    6)Export the filter coefficients "Num" into Matlab workspace by clicking File-Export

    7)Go to Matlab command prompt and type the following:

    coef_set= round(Num * (2^(bits-1))); Note : [ bits = 16]

    dlmwrite('mycoefile.coe',coef_set);

    8)Now you will have a .coe file which contains the coefficients as a,b.............. a

    9) Now you need to modify it so that it is suitable for Xilinx CORE.

    A) Add the following lines at the beginning:

    ;Radix = 10; Coefficient_Width = 16; CoefData =

    B) Change all the ' , ' to ' ; '

    C) Add a ' ; ' in the end

    Now your file looks like :

    ;
    Radix = 10;
    Coefficient_Width = 16;
    CoefData = a; b; ........... a;

    D)Save the file

    Now it should be okay for the Xilinx core.

    Good luck

    Mona

  • RELEVANCY SCORE 3.21

    DB:3.21:Fir Compiler Simulation Error 73



    Hi All,

    I create a Vivado project which only contains FIR Compiler IP Core. During simulation, an error occurs.

    ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.tb_fir_basic in library work located at xsim.dir/work.

    How to fix it?

    Thanks

    Best Regards

    DB:3.21:Fir Compiler Simulation Error 73


    Hi,From Vivado 2014.2 work library is no more there. It is changed to xil_defaultlib. So change the library of tb_fir_basic from work to xil_defaultlib. You can change the library by right click selecting the file as seen in snapshot below




    Regards,Ashish----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.20

    DB:3.20:Labview Fir Compiler Coregen Decimate By 2 Loses Samples mp



    Trying to get a basic FIR decimation (by 2) filter implementation to work using the Xilinx FIR Compiler (V5) IP. The problem I'm having is the number of output samples is half of what I'm expecting to get. If I feed in 500 samples I'm only getting 125 samples (instead of 250). I tried changing the filter to a single rate type and get 250 samples instead of 500.

    DB:3.20:Labview Fir Compiler Coregen Decimate By 2 Loses Samples mp


    I am still having trouble getting this to work on my end. I think I just have some setting that is incorrect and I am able to get this to work using the LabVIEW IP. However, I would like to have the flexability of using the Xilinx IP going forward. Can anyone help me understand what settings I need to have to get a decimate by 2 to work?

  • RELEVANCY SCORE 3.20

    DB:3.20:Problem In Fir Compiler V4.0 Used In System Generator fc



    hi

    I am implementing QPSK modulation/demodulation in system generator and using hardware spartan 3E starter kit. In the demodulator I am using FIR COMPILER v4.0 as a LOW PASS FILTER using the FDA Tool. It is giving me very accurate results. The problem is the compiler is taking too much of resources available. I am having implementation errors in the ISE simulation of the model regarding the usage of a lot of resources.

    I implemented a simple n-TAP MAC FIR FILTER block instead to cater for the resources but it gives a much poorer result although the resource utilization have been within limits and totally implementable.

    So i m stuck in between these two and cannot proceed further.

    Please help

    regards










    Attachments:







    trans_razi4.mdl ‏177 KB

    DB:3.20:Problem In Fir Compiler V4.0 Used In System Generator fc


    hi

    I am implementing QPSK modulation/demodulation in system generator and using hardware spartan 3E starter kit. In the demodulator I am using FIR COMPILER v4.0 as a LOW PASS FILTER using the FDA Tool. It is giving me very accurate results. The problem is the compiler is taking too much of resources available. I am having implementation errors in the ISE simulation of the model regarding the usage of a lot of resources.

    I implemented a simple n-TAP MAC FIR FILTER block instead to cater for the resources but it gives a much poorer result although the resource utilization have been within limits and totally implementable.

    So i m stuck in between these two and cannot proceed further.

    Please help

    regards










    Attachments:







    trans_razi4.mdl ‏177 KB

  • RELEVANCY SCORE 3.20

    DB:3.20:Fir Filter Control kk



    Hello

    I am new to LabVIEW and have problem with FIR fillter control.

    I have usual FIR filter which has Lower cut off frequency control. But

    it does not have taps control. Is it possible to make taps controlto itor to select other block with same properties as this FILTER block?

    Thank you for your answers.

    DB:3.20:Fir Filter Control kk


    Hi DODI,

    I think your question was answered in this topic:

    http://forums.ni.com/t5/LabVIEW/FITTING-IN-XY-GRAP​H/m-p/1619242

    If you need more help, please write the details here and I'll try to find a solution for you!

    Regards,

    Virdzs

  • RELEVANCY SCORE 3.20

    DB:3.20:Reloading Coefficients For Interpolator That Uses Distributed Arithmetic ck



    Hello everyone,

    I am trying to implement an interpolator by 4 using the distributed arithmetic (DA) approach with FIR Compiler v3.2. I want to be able to reload the coefficients, so I enable the "Roloadable coefficients" option.

    In the FIR Compiler manual, although there is a section that explains in which order the coefficients should be reloaded when using the multiply-accumulate (MAC) approach, there is nothing about it when using the DA approach. I even checked the manual of later FIR Compiler versions (up to v5.0), but still there is no such section.

    It would be greatly appreciated if anyone could provide few hints about the reloading order of the coefficients when using the DA approach.

    Kind regards,

    dtheodor







    Solved!
    Go to Solution.

    DB:3.20:Reloading Coefficients For Interpolator That Uses Distributed Arithmetic ck


    employing the DA approach it is not possible to reload coefficients online.

    Regards,

    John

  • RELEVANCY SCORE 3.20

    DB:3.20:Fir Compiler - Efficiency Issue ? xs



    Hello there,I was not sure about posting my question here or to DSP board, but it is rather related to FIR Core itself than algorithms stuff. I'm pushing FIR compiler to its limits a bit as I need 1024 tap 4 times interpolating filter, 32 bit resolution coefs as well as input signal. I think no further details are needed.Here's my concern.

    Obsolete MAC FIR filter 5.1 core generates filter occupying about 15% of logic, 4 BRAMs and 4 MULTs in Spartan 3S200/3S250E. Generating core itself took about 30 seconds.Now FIR Compiler 4.0 does the IDENTICAL job with 48% of logic, 5 BRAMs, 4 MULTs and requiring incredible 17 minutes to generate the core. I though that new versions of anything should be faster, better and more efficient while I experience quite opposite with FIR Compiler. I'm using ISE 10.1.3.Anyone has similar experience with other cores or can comment on this ?Thanks.ctck

    DB:3.20:Fir Compiler - Efficiency Issue ? xs


    Hello there,I was not sure about posting my question here or to DSP board, but it is rather related to FIR Core itself than algorithms stuff. I'm pushing FIR compiler to its limits a bit as I need 1024 tap 4 times interpolating filter, 32 bit resolution coefs as well as input signal. I think no further details are needed.Here's my concern.

    Obsolete MAC FIR filter 5.1 core generates filter occupying about 15% of logic, 4 BRAMs and 4 MULTs in Spartan 3S200/3S250E. Generating core itself took about 30 seconds.Now FIR Compiler 4.0 does the IDENTICAL job with 48% of logic, 5 BRAMs, 4 MULTs and requiring incredible 17 minutes to generate the core. I though that new versions of anything should be faster, better and more efficient while I experience quite opposite with FIR Compiler. I'm using ISE 10.1.3.Anyone has similar experience with other cores or can comment on this ?Thanks.ctck

  • RELEVANCY SCORE 3.19

    DB:3.19:Fir Compiler V3_2 In Sysgen j7


    Hello,

    I'm working with a Virtex2P and I have downloaded an evaluation version of System Generator (Xilinx DSP Tools 9.2.01i).
    Furthermore, I've got MATLAB 7.4/Simulink v6.6. Within the Simulink library Browser/Xilinx Blockset/DSP I cannot see the FIR Compiler v3_2. Is that normal? All the FIR Compilers listed there do not support Virtex2P.

    How to solve this problem?

    Thanks!

    DB:3.19:Fir Compiler V3_2 In Sysgen j7

    The latest version of the FIR Compiler for System Generator for DSP 9.2.01 is version v3.1. We will have the latest version in the next release of the tools. If you would like to use v3.2, then you will have to blackbox it into System Generator for now.

  • RELEVANCY SCORE 3.18

    DB:3.18:Output Gain For Fir Compiler 5.0 9p



    Hi,

    I have generated a 32kHz - 8kHz, 8-channel decimator using FIR compiler 5.0. I have obtained a 76 tap FIR coefficients using a online FIR LPF calculator.

    After implementing and testing in PCBA, I the decimation works, except the output amplitude of the decimator is 1/4 of the input samples. Thinking it is the effect of 4:1 decimation, I re-calculated the LPF FIR coefficients with 4x gain and re-compile.

    The output of the decimator is still 1/4 the inputs.

    How can I set FIR compiler 5.0 to have same output as input amplitude?

    Currently I manually shift the bits to introduce a 4x gain at the outputs which is not optimal.

    Regards,

    Wei Thiam

    DB:3.18:Output Gain For Fir Compiler 5.0 9p


    Hi,

    I have generated a 32kHz - 8kHz, 8-channel decimator using FIR compiler 5.0. I have obtained a 76 tap FIR coefficients using a online FIR LPF calculator.

    After implementing and testing in PCBA, I the decimation works, except the output amplitude of the decimator is 1/4 of the input samples. Thinking it is the effect of 4:1 decimation, I re-calculated the LPF FIR coefficients with 4x gain and re-compile.

    The output of the decimator is still 1/4 the inputs.

    How can I set FIR compiler 5.0 to have same output as input amplitude?

    Currently I manually shift the bits to introduce a 4x gain at the outputs which is not optimal.

    Regards,

    Wei Thiam

  • RELEVANCY SCORE 3.18

    DB:3.18:Fir Compiler V6.1 38



    Hi,

    I wanted to make some clarifications regarding the new FIR Compiler v6.1. I was using FIR Compiler 5.0 previously, but wasn't able to get the reloadable coefficients working, so I'm giving 6.1 a try. What I'm trying to do is to set up an FIR filter to act as a bandpass filter. I have all the filter coefficients I need, but through external software, where the user can choose to change the filter, I'd like to signal to the FPGA to consequently load the new set of coefficients.

    In FIR Compiler 6.1, there is a new field where you can put a "reloadable coefficient file". From what I understand, I can put multiple filters here and then use the filter select in the CONFIG channel to load them to the filter. It generates .mif files which I'm guessing allow the filter to load the new coefficients immediately? Is it correct that I would set the CONFIG_TDATA signal to specify which filter I'd like to select. For example if I have two sets of coefficents in a .coe file, it would output rld_0.mif and a rld_1.mif. If I wanted to use the first set of coefficients, I would set CONFIG_TDATA to be "x0000" and otherwise, "x0001"? I would be satisfied with this if there weren't the reload channel signals to worry about. The documentation doesn't seem to have much regarding this file, so I wanted to make sure my assumption is correct. The documentation, however, refers to a configuration packet which is supposed to signal a reload, however it never specifies what a configuration packet is and its format, unless they are referring to log2roundip(NUM_FILTS). It would be useful if there was a good timing diagram.

    Are there any example designs that I could work from?

    Thanks in advance for the help.

    Regards,

    dlui

    DB:3.18:Fir Compiler V6.1 38


    Both the FIR Compiler v5.0 and v6.x versions support multiple coefficent sets.

    This is in addition to the reloadable coefficent interface.

    The way this works is that user creates a single COE file that cascades the differnt sets together.

    Set 1: 1,2,3,4,5

    Set 2 10,20,30,40, 50

    COE 1,2,3,4,5,10,20,30,40,50

    Then the the user needs to select the number of sets in the CORE Generotor GUI. This will enable to select port and you can then switch between coefficent sets.

    This is the easiest way to do multiple coefs if they are static, but it does cost a bit more in memory storrage. If you do the reloadable interface you can store the coefs off chip and load them when needed.




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 3.17

    DB:3.17:Coefficient Load In Fir Compiler 5.0 Using System Generator 89



    Hi, I have a question about the way coefficients are reloaded into the FIR compiler core under System Generator. The LogiCOREFIR Compiler datasheet (V5.0 P43-45) mentions that the coefficient reload order is not always from coefficientzero to(tap length-1)in sequence, it can be something like 4,5,6,1,2,3 for instance. I was wondering if this were the case with the System Generator FIR compiler block.In the datasheet it mentions that when the FIR compiler is used through COREgen a text file is produced which lists the correct reload order, however I can find no such text file generated when using the FIR compiler block in Sysgen. Does the sysgen block automatically assign the coefficients to the correct taps ordoes the user have to do this manually. If this is the casethen where does the compiler specify the required reload order?

    I was also wondering if this is architecture dependent. The reference design I'm making use of uses the symmetricSystolic Multiply Accumulate architecture, and I've also been able to modify it touse the symmetricDistributed Arithmetic architecture with only minor changes to the coefficient reload order (only reversing the order of reload rather than a complete reorder). However, when I attempt to use the non-symmetricTranspose MAC architecture the results are incorrect (although the timing and input data appears correct).

    Thanks for taking the time to read this,

    RL

    DB:3.17:Coefficient Load In Fir Compiler 5.0 Using System Generator 89


    This is correct that the coef order is not alway sequential.

    There is a function that should be described in the FIR Compiler Help in System Generator that will help with the reload order. xlGetReloadOrderIf you find that it is not working, then you can generate the same core in CORE Generator and use the output file to reorder coefs.




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 3.16

    DB:3.16:Problem With Fir Compiler In Ise Webpack 14.3 z8



    I have used ISE Webpack for about 7 years building FIR filters with Distributed Arithmetic architecture. About a months ago , I noticed that ISE Webpack (14.3) on my PC (Windows 7) returns ERRORs when building the same FIR filter (with FIR Copiler 5.0) that I used to built before with this ISE version. I checked three other PCs in my office and home, they return the same ERROR. Nothing has changed in my design before and after getting the ERROR, it seems like there is a ERROR in the package that was activated after a particular date.

    The FIR Compiler does not return any ERROR if I use other architectures such as Systolic MA. The same design works very well with older versions (like 12.4). A copy of ERROR message is given below. Thanks for any comment/help. -Abi

    XST: HDL CompilationXST: Design Hierarchy AnalysisXST: HDL AnalysisXST: HDL SynthesisERROR:coreutil - Exception caught when running synthesis! ERROR:coreutil - Failure to generate output productsERROR:coreutil - An error occurred while running Java. Please examine the console or CoreGen log file for a specific IP related error. For more information please search the Xilinx Answers Database for this error: http://www.xilinx.com/support ERROR:coreutil - XST has returned an error: coreutil:1012 - CommandERROR:sim - Error found during generation.ERROR:sim - Failed to generate 'trig_filter'. XST has returned an error: coreutil:1012 - CommandWrote CGP file for project 'trig_filter'.

    DB:3.16:Problem With Fir Compiler In Ise Webpack 14.3 z8


    This is not the bug .It seems you are using old core configuration in latest version of core

    Distributed_Arithmetic Filter Architecture not supported in latest version

    FIR Compiler v5.0 these Filter Architecture supported

    Systolic_Multiply_Accumulate, Transpose_Multiply_Accumulate, Distributed_Arithmetic

    FIR Compiler v6.3 these Filter Architecture supported

    Filter_Architecture Systolic_Multiply_Accumulate, Transpose_Multiply_Accumulate




    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.16

    DB:3.16:System Generator Output Does Not Update At All. Fir Compiler. Decimator. kj



    Hi all,

    We are currently facing a very strange behavior in our design we are not able to explain.

    Our system generator design has three outputs. Now, when we directly connect input to outputs (decimating 102400) it works well. If we add a filter that decimates by 10 and then after the filter we decimate by 10240 everything works as expected.

    If we eliminate the decimation stage and connect the filter output to another filter that decimates by 10 and then, after the second filter, we decimate again by 1024 output does not change.

    We tried different things [Please note that all cases worked as expected in Simulink and in ISE (We performed Isim postplace simulations too and apparently it works)]:

    1. Checking it out just with the second filter: output works.

    2. With two filters and making the second filter decimation =1. Output does not work (This case is two filters N_1 =10 N_2=1)

    3.This design worked well in the past (so we know for sure the rest of our design is working great and filters coefficients are properly calculated) we just changed the computer that we are using for this development.

    4. We have three outputs and we shuffled them to be sure our issue is inside system generator part (and it is, as problem is always in the output fed by two filters in cascade).

    5. We were using FIR Compiler 6.3 so we tried by changing them by two FIR compilers 5.0 to get rid of the AXI part. It doesn´t work.

    Some help would be greatly appreciated.

    Best regards

    Francisco Gallardo

    DB:3.16:System Generator Output Does Not Update At All. Fir Compiler. Decimator. kj


    We think it could have to do with decimation in some strange manner.

    It works well when we avoid decimation inside FIR compilers and decimate N=102400 just after second FIR filter.

    Any ideas? We are now trying with the "ND" optional input in FIR compile

  • RELEVANCY SCORE 3.15

    DB:3.15:Fir Compiler V6.3 sd



    Hi,

    I have designed a low-pass filter using simulink and transfered the coefficients into the FIR compiler v6.3, this then displays the correct frequency responce on the diagram to the left, generate the module using all standard setting, adjusting bit sizes as I require. However when I run a simulation with a signal with dc off-set the filter is letting the signal through at the same level as the DC offsset, when it should be being suppressed by 80dB with respect to the DC off-set.

    Does anyone have any suggestions of why this would be the case?

    Thanks

    DB:3.15:Fir Compiler V6.3 sd


    Can you post your coefficients? How are you setting up the quantization and bit width/binary point settings in the core?

    If you send in an impulse, do you get your expected coeffs back out of the core?

    What are the characteristics of the signal youare using to test with?




    www.xilinx.com

  • RELEVANCY SCORE 3.15

    DB:3.15:Complex Cross Correlation Using Fir sk



    HI all,

    (I know I can use a FIR fiter for correlation. I have searched the forum first before posting here and read some threads, but for example in this onehttp://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/Cross-correlation-to-detect-special-bitstream/m-p/148484where the problem is similar, the TS never explains how he got it working).

    I have a system that transmits an I and a Q signal. I modelled it in Matlab to test and now also in System Generator because I need to implement it on FPGA. So it enters the receiver after being sent through a wire, so it gets noisy.

    What is the format? In every frame of 80 samples there is a specific sequence of 8 samples (normally complex number, but here thus I and Q). My receiver needs to determine the location of this sequence of 8 samples in the frame of 80 samples. So my idea was to buffer/store these 80 samples. Then do a cross correlation on the entire frame with the reference sequence (that is known in the receiver) and thus determine where in the frame the sequence is located. With that I load a counter that unloads the sequence out of the addressable shift register.(ps: the coeffs are dynamically loaded)

    I don't think doing this with complex numbers on FPGA will work, so I'm doing this separately with I and Q and hope they give the same location :) (any new ideas on that are always welcome ;) )

    In matlab I use this function:xcorr_signal=filter(conj(reference(end:-1:1)),1,input);

    This filter should be a FIR filter so I decided to use the FIR compiler in System Generator. Because I didn't get it to work I isolated the block and I'm trying to get it working. The FIR outputs a peak somewhere but not where it should be (peak in Matlab is at the end of the sequence I'm looking for).

    This is the isolated problem:

    The input sequence is:[2,6,8,7,1,4,5,3,2,1,4,5,8,9,1,0] stored in ROM

    The sequence I want to detect and is read in as coeffs (so already reversed) is[1,2,3] (so I want to detect sequence 321 in the input). The initial value of the coeffs as entered in the FIR compiler block is: zeros(3,1)

    The timings are correct according to the Wavescope (data and coeffs at right moments nd en coef_we):

    Now in Matlab my maximum would be on place 10 (the end of the sequence 321). However this is the output I get when I to workspace the rdy and dout signal of the FIR:

    The maximum clearly lies on sample 3 based on the ready signal, which is not at all correct. I tried adding zeros so that coeffs length matches input length but that did not help.

    I sincerely hope that someone knows why this is wrong (probably it's trivial though :p )....I have two days to get this part ready so I'm a bit stressed :p

    thanx a lot in advance!

    Tom

    DB:3.15:Complex Cross Correlation Using Fir sk


    ok, I fixed it together with my assistants I think. I have been using the wrong sequence to test this. all my values are positive so the filter will only add up and the peak will be at the location where the highest result is based on the input power....Matlab also gives the wrong value when using these inputs and coeffs.

    If I add random noise to my frame with zero mean so that it generates some negative values it does give the right location. Now gonna test it in sysgen but should work fine

    Tom

  • RELEVANCY SCORE 3.15

    DB:3.15:Fir Compiler Polyphase Filter Bank Not In Ver 6.3 cd



    FIR Compiler ver 6.3 datasheet doesn't list Polyphase Filter Bank as being an option. But it is an option in ver 5, and 6.2. Will it be supported in future versions?

    thanks.

    DB:3.15:Fir Compiler Polyphase Filter Bank Not In Ver 6.3 cd


    FIR Compiler ver 6.3 datasheet doesn't list Polyphase Filter Bank as being an option. But it is an option in ver 5, and 6.2. Will it be supported in future versions?

    thanks.

  • RELEVANCY SCORE 3.15

    DB:3.15:Fir Compiler 5.0 Problem j8



    Im trying to feed some noice into the gateway, ftilter it and then use the DSP - Spectrum Alalyzer to se if the filter is working. Witch is its, but when im trying to run the modell on whit Co Hardware, im getting error posted below. It says that there is something wrong whit the bool-constant, but i cant figure out whats wrong whit it?

    [url=http://bildr.no/view/L0N6c09j][img]http://bildr.no​/thumb/L0N6c09j.jpeg[/img][/url]










    Attachments:







    testFPGA_sysgen_error.log ‏2 KB

    DB:3.15:Fir Compiler 5.0 Problem j8

    The most common cause for a standard exception error in System Generator is an error message that originates in another tool, but is not properly issued to System Generator to pass along as the correct error message. There may be an error message embedded after the standard exception message, which gives additional information about a specific core or tool which failed during generation. Some known causes of this error message are as follows: (Xilinx Answer 23614) - System Generator 11.2 and 11.3, TEMP/TMP environment variables(Xilinx Answer 33993) - System Generator 11.2, 11.3 and 11.4 there is an XST known issue which can cause this error messagecoregen.log will contains the following message:ERROR:Xst:2996 - XST patch Expired. - System Generator has to generate an IP core in CORE Generator and the correct IP is not installed or found. - CORE Generator runs out of memory during generation of an IP core. - XST generates an error during generation of an IP core. - The output netlist directory is too deep and cannot be created by Windows. (Note that 256 is the maximum number of characters in a directory path and that System Generator often creates several subfolders used during generation.) - Cannot use System Generator with IBM Clear Case. See (Xilinx Answer 24267). - Cannot generate a multiple subsystem generator design which contains an HDL black box with bi-directional ports. See (Xilinx Answer 31071). - Cannot communicate with ISE because an unsupported version is pointed to by the Xilinx environment variable. See (Xilinx Answer 17966) for information on tool compatibility. - After updating software versions, previously generated cores cannot be replaced. Clear the System Generator core cache (see the user guide for details). NOTE: A log file in the output netlist directory and subdirectories might provide further information on the error. Java Another possible problem could be a conflict with a Java process that is already running on your machine, or with the Java Run-time version installed on your machine. If you are using a version of Java other than that installed by MATLAB, this could cause problems. It has also been found that if Java is running before you launch MATLAB, it might interfere with the interprocess communication. Terminating any existing Java processes with the Windows Task Manager might also resolve this problem.



    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.14

    DB:3.14:Fir Compiler V3.0 And Mac Fir Filter 5.1 Core Generators 8s



    Hello everyone,

    I want to generate a decimator by 4 using the FIR Compiler v3.0. As I have posted in my previous thread ( http://forums.xilinx.com/xlnx/board/message?board.​id=DSPmessage.id=308query.id=313542#M308 ), I run into some simulation problems on either behavioral or PAR. However, under behavioral simulation, the results are eventually correct, but under PAR simulation, Modelsim compains with messages like the one that follows, so I have to stop it:

    ** Warning: Functional warning at simulation time ( 2994.903 ns) :
    X_ARAMB36_INTERNAL (
    :tb2_tb_vhd:uut:buffers_and_decimators_13_decimato​rs_i_blk00000003_blk00000147:x_ramb16_inst:)
    port B is in WRITE_FIRST mode. The write will be successful, however
    DOB shows only the enabled newly written byte(s). The other byte values
    on DOB are unknown until the next CLKB cycle and all bits of WEB is set
    to all 1s or 0s.

    Furthermore, when I try to use the MAC filter v5.1 core to generate a decimator by 4, after accepting the first input, the core's output rfd (ready for data) is not asserted and further processing is stopped.

    I would like to ask if anyone has run into similar problems under the exact core versions and if eventually managed to successfully create a decimator.

    Any help would be great.

    Kind regards,

    dtheodor

    DB:3.14:Fir Compiler V3.0 And Mac Fir Filter 5.1 Core Generators 8s


    Hello Ticktack,

    Again thank you for your reply.

    Unfortunately, as you know, when using the FIR compiler or the MAC / DA FIR filter core generators, you do not have access on the write mode of the memories that are used by the core. And, of course, you were right about the functional warning that may appear to these cores (except the Block memory generator).

    So, after several lost days of trying different versions of the FIR compiler, I decided to put all coefficients and input data buffer to distributed memory and (presto!) the functional warning is gone. But my problem, as you can understand, is that now my design occupies much more FPGA area.

    My design consists of 16 FIR filters, each one having 19 sets of 128 coefficients. Instead of using the FIR Compiler's ability to generate an FIR filter with many coefficient sets (all stored in Block memories and easily selected by a control signal), now I'll have to generate all FIR filters with only 1 set mapped onto distributed memory and reload manually the new coefficients from block memories.Up to now, this is the best solution that I've found to bypass the problem.

    Indeed, it is realy a pity to lose so many days on issues like this one...

    Sorry for my long reply and again thank you very much for your comments, which helped a lot.

    Kind regards,

    dtheodor

  • RELEVANCY SCORE 3.14

    DB:3.14:Problem In Using Fir Complier 7d



    I created a fir filter with 10 coefficents througn the FIR complier, and although I used the SYSTOLIC structure, the filter ouputed results after 14 cycles, and the valid results are about 19 cycles later.Why?

    I think the filter should output the valid result just after 14 clock cycles.

    Is there any problem in my creating the filter?

    Thank you !

  • RELEVANCY SCORE 3.14

    DB:3.14:Reloadable Coefficients Fir Filter ks



    Hi everyone,

    i have question about the behaviour of a FIR filter with reloadable coefficients. After generating a FIR filter with the FIR compiler v6.3 i tried to simulate the reload process in my design according to Fig. 10 on page 26 of ds795_fir_compiler.pdf document. After several tries I always saw that after asserting s_axis_config_tvalid (a filter with one channel and one coefficient set) the event event_s_reload_tlast_unexpected is asserted. So i switched to the demo testbench generated by the fir compiler itself. As given in the Figure below the same behaviour can be observed.

    So my questions are: Is this desired behaviour of the core? Did i misunderstand something when generating the core or maybe in the control protocol (but this is simulated with the "official" testbench)?

    On page 25 of the mentioned document it says that the signals of the event interface are to be considered as errors or can (maybe) ignored. So are the reloaded coefficients in the rld_coeff tregister of the core nevertheless loaded to the core when asserting s_axis_config_tvalid?

    DB:3.14:Reloadable Coefficients Fir Filter ks


    hello i am a student.

    now i am design a filter wtih 3 coefficient sets,i want to use reload funtion in FIR Compiler 6.3 .the system can work in 3 sample feequency so the filter have 3 coefficeint sets. when chose the sample frequey, i want to reload the coefficeints.

    the coefficeitns are in *.coe file, when reloading,how the coefficient data downto the core?

    and how to caculae the reload slots?

    i am looking forword your reply!

    my mail is wuyanbei24@gmial.com.

    thank you!

  • RELEVANCY SCORE 3.14

    DB:3.14:Theads Threads Threads..... ca


    Hi everyone.I am trying to build an airport with two runways using Threads I am trying to use my semaphore class so two airplane at most can land.My problem is that when I call the down method (controlTower.value.down())the system halts.
    and I dont know how to fix it.if I remove the method one airplane lands at a time.
    Thanx in advance sorry about the large parts of code the first method is the one that calls the down() method and the second class is my semaphore class.
    code
    synchronized public void run() {
    while (true)
    {

    for(int no=0;nofir.length;no++)
    {
    if (fir[no]==null) {}
    else
    {
    if (!fir[no].isAlive())
    {
    fir[no].start();
    }
    if((fir[no].x==0)(fir[no].y==0))
    {

    if(fir[no].allowedRunway1==true )
    {
    controlTower.runway1.available=true;
    }
    if(fir[no].allowedRunway2==true )
    {
    controlTower.runway2.available=true;
    }

    fir[no]=null;
    //code to release runways
    count++;
    }
    }
    }

    drawPlanes(point);
    try
    {
    controlTower.value.down();}catch(InterruptedException e){System.out.println(e);}

    if(controlTower.runway1.available==true)
    {
    for(int i=0;ifir.length;i++)
    {
    if(fir!=null)
    {
    controlTower.runway1.available=false;
    try
    {
    // controlTower.value.down();
    }catch(InterruptedException e){System.out.println("qwertt");}

    fir[i].allowedRunway1=true;break;

    }
    }
    }
    else if(controlTower.runway2.available==true)
    {
    for(int i=0;ifir.length;i++)
    {
    if(fir[i]!=null)
    {
    // controlTower.runway2.available=false;
    try
    {
    controlTower.value.down();
    }catch(InterruptedException e){System.out.println("q");}

    fir[i].allowedRunway2=true;break;
    }
    }
    }
    }
    }
    //another class semaphore
    class Semaphore
    {

    private int value;

    public Semaphore (int initial)
    {
    value = initial;
    }

    synchronized public void up()
    {
    ++value;
    notifyAll();//should be notify() but does not work in some browsers
    }

    synchronized public void down() throws InterruptedException
    {
    while (value==0) wait();
    --value;
    }
    }

    /code

    DB:3.14:Theads Threads Threads..... ca

    In you code, below (snippet):
    synchronized public void up() {
    ++value;
    notifyAll(); //should be notify() but does not work in some browsers
    }... It's you comment that caught my attention.

  • RELEVANCY SCORE 3.12

    DB:3.12:Fir Filtering Design With Optional Parameters 3c



    Was trying hands-on in creating my own VI with reference to the existing one available for LabView 8.5 - FIR Filtering Design with Optional Parameters.

    Everything which I had created is the same as what was provided, however there pop an error which I'm not sure what it is. Can anyone help me take a look, and how can I rectify these problem? The error only appears when you run the program.










    Attachments:







    FIR Filtering Design with Optional Parameters.vi ‏51 KB

  • RELEVANCY SCORE 3.12

    DB:3.12:Fir Compiler 5 Decimation Problem d9



    Hello,

    I'm trying to migrate my design, from ISE 9.1 to ISE 13.4 and a lot of things have change.

    I have a Digital Down Converter, and I implement it whit DAFIR, now in the new System Generator, I have to choose FIR COMPILER 5, with the Distributed Aritmethic ta checked. If I try to generate a first decimator by a factor of 2 with the Systolic, or acumulative mult I have no problems, but if I try to generate a decimator with Distributed arithmetic I have no decimation at the output of the filter. I can´t use Systolic, because I have not enought DSP 48 in my spartan 3ADSP, I attach an image of an example of what is happening. Althougt I do a decimation, at the output of the filter I have the same freq.

    

    Any help will be very gratefull.







    Solved!
    Go to Solution.

    DB:3.12:Fir Compiler 5 Decimation Problem d9


    I attach the design, if anyone have couriosity.

    The fs is 121.76 Mhz.

    Thanks










    Attachments:







    design.zip ‏30 KB

  • RELEVANCY SCORE 3.11

    DB:3.11:Fir Compiler mx



    AFAIK, FIR is nothing more than a set of (convolution) coefficients. Now, how is it possible that you provide both passband and stopband as input arguments for the filter generation along with the coefficients? Aren't they related, implying redundancy or, more likely, incompatibility conflicts? Why I always have a low-pass filter, no matter which coefficients I choose? Why don't coefficients affect anything but ripple? Why do I get a low-pass filter, despite my pass band is in (0.5-1) and stop-band in the range (0-0.5)?







    Solved!
    Go to Solution.

    DB:3.11:Fir Compiler mx


    I have accepted but I do not agree that it is clear from the datasheet.

  • RELEVANCY SCORE 3.10

    DB:3.10:Fir Compiler V5.0 Problem m7



    I am trying to design QPSK modulator demodulator. Modulator is working fine but in demodulator filter design is creating problems.

    Below Image shows the signal before low pass filter and after low pass filter which is an error.

    I am also attaching the entire model.

    I am using Matlab R2011a and Xilinx version 13..please help me..










    Attachments:







    qpsk_dev13.mdl ‏167 KB

    DB:3.10:Fir Compiler V5.0 Problem m7


    the problem is due to assigning the binary point for the filter. abjust the binary point you may get the solution.




    Shark

  • RELEVANCY SCORE 3.10

    DB:3.10:Fir Compiler Beginner Question 8k



    I am multiplying a 2kHz sinewave with another 100khz sinewave to obtain a dsb-sc signal. These sinewaves were designed using DDS cores. I am also using a 50mHz clock. I would like to demodulate this dsb-sc signal. I am doing this by multiplying the dsb-sc signal with the carrier (100khz signal). Now i have to pass this signal through a low pass filter. I have generated a coefficient file (.coe) from matlab and am using the FIR compiler to actually generate the low pass filter. I have put 50mhz as the input clock frequency but the problem is that i am not exactly sure what to put in as the sampling frequency. Could anyone provide some help regarding this.

    Thanks a million

    DB:3.10:Fir Compiler Beginner Question 8k


    I am multiplying a 2kHz sinewave with another 100khz sinewave to obtain a dsb-sc signal. These sinewaves were designed using DDS cores. I am also using a 50mHz clock. I would like to demodulate this dsb-sc signal. I am doing this by multiplying the dsb-sc signal with the carrier (100khz signal). Now i have to pass this signal through a low pass filter. I have generated a coefficient file (.coe) from matlab and am using the FIR compiler to actually generate the low pass filter. I have put 50mhz as the input clock frequency but the problem is that i am not exactly sure what to put in as the sampling frequency. Could anyone provide some help regarding this.

    Thanks a million

  • RELEVANCY SCORE 3.10

    DB:3.10:Trouble With Simulation Of Filter From Fir Compiler 6.3 xz



    I have a simple fir filter that I would like to simulate. It has been instantiated as follows:

    firFilter u_firFilter ( .aresetn(rst_n), // input aresetn .aclk(clk), // input aclk .s_axis_data_tvalid(1'b1), // input s_axis_data_tvalid .s_axis_data_tready(), // output s_axis_data_tready .s_axis_data_tdata(impulse), // input [15 : 0] s_axis_data_tdata .m_axis_data_tvalid(), // output m_axis_data_tvalid .m_axis_data_tdata(impResponse) // output [23 : 0] m_axis_data_tdata);

    I was expecting to see the coefficents come out when running an impulse test (assuming I scale

    my impusle correctly). Instead I do not see anything on the output. When I try a step response

    (just driving the input with a fixed value) I see unkowns on the output.

    Any thoughts on what the problem might be?

    I tied tvalid on the input hi so that it would process everything on the input after reset.







    Solved!
    Go to Solution.

    DB:3.10:Trouble With Simulation Of Filter From Fir Compiler 6.3 xz

    Should've looked at the tb generated by coregen first. While I still don't understand the need for tready, I need to wait for it to be asserted before presenting a new sample (and asserting tvalid) on the input. It seems unecessary for a FIR filter, but at least I understand how to drive it now.

  • RELEVANCY SCORE 3.09

    DB:3.09:Interpolator Using Fir Compiler Never Outputs A Result 9j



    Hi,

    I'm attempting to simulate an interpolation by 2 implemented with the fir compiler 5.0 for the virtex 4. When I send data to the IP core the ready for data line drops after two samples and then never goes high again. Similarly, the RDY line saying that an output sample can be read never goes high. I'm using the default filter that the core assumes for the coefficients as well as new data (ND) and clock enable (CE). My test bench file is attached, as well as the data sheet for the IP Core and a screen shot of the signals.

    Can anybody tell me why the core gets stuck and produces nothing?

    Thanks for your help.

    jw







    Solved!
    Go to Solution.

    DB:3.09:Interpolator Using Fir Compiler Never Outputs A Result 9j


    Hi,

    It was the clock frequency. I was assuming the input sample rate field in the IP GUI was dealing only with the display to the left and did not impact the core itself. Bad assumption. When I changed the sample rate field, I started getting data as quick as I was hoping.

    Thank you for your help.

    jw

  • RELEVANCY SCORE 3.09

    DB:3.09:Designing Fir Filter kf



    Hello,

    I am designing a FIR filter using the FIR compiler v 5.0 and FDATool. I have some issues running the simulink:

    I get error saying i need to add a buffer. However i add the buffer but nothing has changed. the other issue is when i connect the output of FIR filter stight to the scope i get nothing.

    Can someone help please??

    Thanks










    Attachments:




    DB:3.09:Designing Fir Filter kf


    Hello,

    I am designing a FIR filter using the FIR compiler v 5.0 and FDATool. I have some issues running the simulink:

    I get error saying i need to add a buffer. However i add the buffer but nothing has changed. the other issue is when i connect the output of FIR filter stight to the scope i get nothing.

    Can someone help please??

    Thanks










    Attachments:




  • RELEVANCY SCORE 3.09

    DB:3.09:System Generator 13.3, Matlab R2012a : Error: Ise Simulator Simulation Could Not Be Started 99



    hi,

    I am new to System Generator. I recently installed Xilinx EDK, ISE and System Generator version 13.3 . I tried doing all the System Generator Labs 1 to 7 to get familiar with its usage. In the final lab, lab7, whie simulating the FIR filter design I got the following error:

    "

    ISE Simulator Simulation could not be started. It is possible that the system memory available for this process has been exhausted.Error occurred during "Simulation Initialization".

    "

    I do not get this error if there is only simulink FIR model (FDA Tool). I could see the resultant output on the simulink spectrum scope.

    The simulink model configuration:

    "Random Number Generator" --- "FDA Tool" --- Spectrum Scope

    I get the error as soon as I include Xilinx FIR compiler 5.0 block and relevant xilinx components.

    Xilinx model configuration:

    Same "random number generator" -- "gateway in" -- "Fir Compiler 5.0 block "--- "Convert/cast" ---"gateway out"---Spectrum Scope 1

    The error stays with all Xilinx FIR Compiler versions (Fir Compiler 6).

    Any help will be much appreciated.







    Solved!
    Go to Solution.

    DB:3.09:System Generator 13.3, Matlab R2012a : Error: Ise Simulator Simulation Could Not Be Started 99


    Depends on which version of the tools you're looking at. See here for an enumerated list:

    http://www.xilinx.com/support/answers/17966.htm




    www.xilinx.com

  • RELEVANCY SCORE 3.09

    DB:3.09:Artix 7 Vivado Fir Compiler 7.1 Parallel Channel Problem 33



    Hi All,

    I am having some trouble with using a FIR filter with parallel channels.

    Using a FIR compiler (7.1), I made a band-pass filter which receives two input buses.

    In AXI4 stream format, s_axis_data_tdata = {4'd0, INPUT2[11:0], 4'd0, INPUT1[11:0]};

    The FIR filter input width is 12 bits, and its output width is 17 bits such that the width of m_axis_data_tdata is 48 bits (24 bit + 24 bit).

    I declared that m_axis_data_tdata = {temp_2[7:0], OUTPUT_2[15:0], temp_1[7:0], OUTPUT_1[15:0]} because I only want to use 16 LSBs from each output channel.

    temp_1, and temp_2 are left unconnected.

    However, when I see the output of the FIR filter, LSBs of OUTPUT_2 is affected by the MSBs of OUTPUT_1, and OUTPUT_1 seems to have similar problem as well...

    I tested plugging the cleansine wave to INPUT_1 and just noise to INPUT_2, and I can see that the OUTPUT_2 shows a small sine wave (seems like only 6 LSBs are affected by 6 MSBs of INPUT_1).

    Is there anything that I need to be cautious when the BPF are used in parallel channels? I thought this would be pretty straight-forward, but it causes a lot of trouble..

    Thanks in advance,

    Joohyun

    DB:3.09:Artix 7 Vivado Fir Compiler 7.1 Parallel Channel Problem 33


    It turns out that there is no issue with a FIR filter, but rather the problem that I am struggling comes from other sources.

    Sorry for the confusion, and thank you for your reply.

    Thanks,

    Joohyun

  • RELEVANCY SCORE 3.08

    DB:3.08:Fir Filter Strange Behaviour On Clock Change 8f



    Hello,

    I'm running a FIR filter on a Spartan 3A usign a DCM to raise my input clock to a value that fits both incoming sampling frequency and minimum clock requirement. The problem with the filter is that the input clock can change between 22.5792MHz and 24.576MHz, passing through temporary values around the mentioned ones, but slightly different (it's an external PLL freerunning). When this happens, the output signal's amplitude changes, as if my data were misaligned. I know they aren't, so it seems like it's a problem of clock glithes or similar which affect the FIR. I've also gated the ND signal with a flag driven by the external PLL, with no success. Using the SCLR pin doesn't help. Also, I've seen that the LOCKED pin of the DCM never goes low after locking the first time, even if I change the incoming clock or I stop it! I use a counter to reset the DCM after configuration download in order to have it working properly.

    I'm using ISE 11.1 and FIR compiler 4.0.

    Marco

    DB:3.08:Fir Filter Strange Behaviour On Clock Change 8f


    Hello,

    I'm running a FIR filter on a Spartan 3A usign a DCM to raise my input clock to a value that fits both incoming sampling frequency and minimum clock requirement. The problem with the filter is that the input clock can change between 22.5792MHz and 24.576MHz, passing through temporary values around the mentioned ones, but slightly different (it's an external PLL freerunning). When this happens, the output signal's amplitude changes, as if my data were misaligned. I know they aren't, so it seems like it's a problem of clock glithes or similar which affect the FIR. I've also gated the ND signal with a flag driven by the external PLL, with no success. Using the SCLR pin doesn't help. Also, I've seen that the LOCKED pin of the DCM never goes low after locking the first time, even if I change the incoming clock or I stop it! I use a counter to reset the DCM after configuration download in order to have it working properly.

    I'm using ISE 11.1 and FIR compiler 4.0.

    Marco

  • RELEVANCY SCORE 3.08

    DB:3.08:Fir Compiler 6.3 Problem During Synthesis 3c



    Hi,

    I m trying to do Interpolation using FIR Compiler 6.3. My model is working is fine in Simulink. I have added Xilinx Model project file into my Xilinx ISE. Simulation using ISIM is also working fine.

    When i want to synthesize the code then i m getting errors as below.

    WARNING:Xst:1513 - No elements found for TNM 'ce_3_8fede06e_group' on object 'ce_3_sg_x0'.ERROR:Xst:1617 - Processing TIMESPEC TS_ce_3_8fede06e_group_to_ce_3_8fede06e_group: user TIMEGRP 'ce_3_8fede06e_group' must be previously defined in FROM/TO constraint.ERROR:Xst:1489 - Constraint annotation failed.

    Can anyone please help me in this regard. Thanks in advance.

    Regards,

    Kiran

    DB:3.08:Fir Compiler 6.3 Problem During Synthesis 3c


    Hallo,

    back to problem again. Does anyone have any idea regarding my problem?

    Thanks in advance.

    Regards,

    Kiran

  • RELEVANCY SCORE 3.08

    DB:3.08:Fir Compiler 5.0 / Hilbert jp



    Hi,

    I want to Hilbert Transform for demodulation. I m using FIR Compiler 5.0 from System Generator for DSP 13.2 with Matlab 2010b.

    My questions are

    Hilbert from FIR Compiler 5.0 gives the analytic signal as "hilbert.m" function in Matlab?

    I have compared the results by applying same input signal...but the results are not same. any ideas please??

    I have tried also using Hilbert Transform from FDA tool (Hilbert Filter) in the Signal Processing Toolbox in Matlab for the same input signal. I got different results compared to both of the above.

    So finally i m confused which result is correct..?

    What is the difference between Hilbert Filter and Hilbert Transform??

    Thanks a lot in advance for your replies.

    Best Regards,

    Kiran

    DB:3.08:Fir Compiler 5.0 / Hilbert jp


    Hi Thomas,

    Its working now. I checked the result. thanks for your reply.

    Cheers,

    Kiran

  • RELEVANCY SCORE 3.07

    DB:3.07:Doubt In Fir Compiler 9x



    Hi,

    I am using FIR compiler V5.0 in my application.

    I am using the coefficient reload interface to update the coefficients of my adaptive filter every 1msec.

    What I observe is, sometimes the filter core updates the filter with a new set of coefficientseven when the trigger to adaptive filter does not come.

    I have attached the logic for updating the coefficients in the file, I have given sufficient comments wherever possible. Please give some pointers on how to solve this problem.

    Thanks in advance.










    Attachments:







    adaptive_check.v ‏4 KB

    DB:3.07:Doubt In Fir Compiler 9x

    Hi,

    I have one more doubt.

    Is there a minimum time which the core needs, before upating the filter for the second time (i,e time interval between

    updating two sets of coefficients) ?

    There is nothing like that mentioned in the datasheet, but I just wanted to clarify

    Thanks

  • RELEVANCY SCORE 3.07

    DB:3.07:Fir Compiler 5.0 And 2012.2 ap



    Any idea why FIR Compiler 5.0 is removed from ISE and Vivado 2012 ?

    I don't see option to use distributed arithmetic filters in FIR 6.3.

    DB:3.07:Fir Compiler 5.0 And 2012.2 ap


    The reason is FIR compiler v5.0 doesn't have support for 7 series devices andVivado only supporte 7-series i.e. Kintex-7,​ Virtex-7,​ Artix-7. So you can't design with Vivado and 7-series using FIR compiler v5.0. You need to migrate your designs with FIR compiler v5.0 to FIR compiler v6.3 to make it work with 7 series and Vivado tool.




    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.05

    DB:3.05:Fir Compiler Output 1x



    Hi all,

    I've tried to implement a low pass filter using fir compiler 6.3 but the ouput i've got is something different. can anyone suggest what went wrong. i am attaching the simulink model here. i've used ISE14.2 with Matlab 2012a.

    Thanks in Advance,

    Naidu.










    Attachments:







    fir_filter.mdl ‏102 KB

    DB:3.05:Fir Compiler Output 1x


    Hi all,

    I've tried to implement a low pass filter using fir compiler 6.3 but the ouput i've got is something different. can anyone suggest what went wrong. i am attaching the simulink model here. i've used ISE14.2 with Matlab 2012a.

    Thanks in Advance,

    Naidu.










    Attachments:







    fir_filter.mdl ‏102 KB

  • RELEVANCY SCORE 3.05

    DB:3.05:Fir Filter Parallel Channel Problem cp



    Hi All,

    I am having some trouble with using a FIR filter with parallel channels.

    Using FIR compiler (7.1), I made a band-pass filter which receives two input buses.

    In AXI4 stream, s_axis_data_tdata = {4'd0, INPUT2[11:0], 4'd0, INPUT1[11:0]};

    The FIR filter input width is 12 bits, and its output width is 17 bits such that the width of m_axis_data_tdata is 48 bits (24 bit + 24 bit).

    I declared that m_axis_data_tdata = {temp_2[7:0], OUTPUT_2[15:0], temp_1[7:0], OUTPUT_1[15:0]} because I only want to use 16 LSBs from each channel.

    temp_1, and temp_2 are left unconnected.

    However, when I see the output of the FIR filter, LSBs of OUTPUT_2 is affected by the MSBs of OUTPUT_1, and OUTPUT_1 seems to have similar problem as well...

    I tested plugging the cleansine wave to INPUT_1 and just noise to INPUT_2, and I can see that the OUTPUT_2 shows a small sine wave (seems like only 6LSBs are affected by 6 MSBs of INPUT_1).

    Is there anything that I need to be cautious when the BPF are used in parallel channels?

    Thanks in advance,

    Joohyun

    DB:3.05:Fir Filter Parallel Channel Problem cp

    Please refer to this post:http://forums.xilinx.com/t5/7-Series-FPGAs/Artix-7​-Vivado-FIR-Compiler-7-1-Parallel-Channel-Problem/​m-p/538189



    www.xilinx.com