• RELEVANCY SCORE 3.71

    DB:3.71:Debug Download Failed To Sp601 Board c9





    I´m working with EDK 12.1 and a Spartan SP601 board. I worked for a while with small c-Projects with SDK and debugging via the on-board USB-JTAG. With another (bigger) project I can not download the elf-file to the board.

    I get the following message (if I try it the first time after downloading the bitstream (this works always):

    (mb-gdb console)

    .gdbinit: No such file or directory.Ignoring packet error, continuing...Ignoring packet error, continuing...

    (after that in a message box)

    Unexpected error while launching program: Error downloading program to target: Target is not responding (timed out)

    Trying it more times I get the message:

    (mb-gdb console)

    .gdbinit: No such file or directory.
    Ignoring packet error, continuing...
    Ignoring packet error, continuing...

    (after that in a message box)

    Unexpected error while launching program: target selection failed

    I already tried a .gdbinit file with the following entries:

    set download-write-size 4096set remote memory-write-packet-size 4096set remote memory-write-packet-size fixedset remote memory-read-packet-size 4096set remote memory-read-packet-size fixed

    Got the same result...

    Any ideas?

    Regards,

    Thomas







    Solved!
    Go to Solution.

    DB:3.71:Debug Download Failed To Sp601 Board c9


    You can use the hostname instead of the IP address.

  • RELEVANCY SCORE 3.18

    DB:3.18:Sp601 Evaluation Board Problem With Downloading .Mcs File Into Spi Flash 88





    hello, everyone.

    i just started to study sp601 evaluation board, encounting several problem. one of which is downloading .mcs file into spi flash.

    i can use impact to download .bit file in jtag mode, and the led subsequently blinked, proving the .bit file was actually downloaded. but i failed to download .mcs file as soon as i issue the command.

    there is instruction in doc, saying use sw2 m0m1 to switch between spi rom and bpi rom, and j15 , 16*4 spi rom w25q64bv and J12 ,which is generally used. and it guarantee that the usb-jtag connectorcan be used not only in jtag mode,but also in spi-flash rom mode, (though not clear descriped, with word "indirectly" or likewise) .in addition, i swith sw2 to SPI FLASH, J15 to ON, and the mentioned above can be mostly found in SP601 Hardware User Guide.

    how did you all make it? since there were few to ask, anything i miss or mistake?or there are some doc i should check at first?

    thanks in advance.

    DB:3.18:Sp601 Evaluation Board Problem With Downloading .Mcs File Into Spi Flash 88


    hello, everyone.

    i just started to study sp601 evaluation board, encounting several problem. one of which is downloading .mcs file into spi flash.

    i can use impact to download .bit file in jtag mode, and the led subsequently blinked, proving the .bit file was actually downloaded. but i failed to download .mcs file as soon as i issue the command.

    there is instruction in doc, saying use sw2 m0m1 to switch between spi rom and bpi rom, and j15 , 16*4 spi rom w25q64bv and J12 ,which is generally used. and it guarantee that the usb-jtag connectorcan be used not only in jtag mode,but also in spi-flash rom mode, (though not clear descriped, with word "indirectly" or likewise) .in addition, i swith sw2 to SPI FLASH, J15 to ON, and the mentioned above can be mostly found in SP601 Hardware User Guide.

    how did you all make it? since there were few to ask, anything i miss or mistake?or there are some doc i should check at first?

    thanks in advance.

  • RELEVANCY SCORE 3.15

    DB:3.15:Sp601 Base System Reference Design Project Speed pz





    I'm currently using (and modifying) the provided SP601 base reference design project and running into timing issues. I modified the GUI to constantly request data from the SP601 board at a rate of 1ms (xilinxDevice.SendUserDefinedPacket(control,controlWord)), however the average time between messages received from the SP601 is 15-20ms and sometimes as large as 300ms. Is there a way to increase this speed or what is that actually limiting factor?

    Is there any additional information on this project besides UG523 that walks through the project?

  • RELEVANCY SCORE 3.12

    DB:3.12:Connecting Uart With Sp601 mx



    Hi,

    using sp601 evaluation board. i have written in my design a UART code and i see that there is a usb-rs232 bridge on the board but except for RX,TX it needs RTS and CTS.

    can i use this uart bridge and simply not connect those signals ? (my uart is a simply one with one RX and TX)

    thanks!

    Zvika.

    DB:3.12:Connecting Uart With Sp601 mx

    You can refer this ARs http://www.xilinx.com/support/answers/33319.htmboard documentation may help youwww.xilinx.com/support/documentation/boards_and_kits/xtp049.pdf



    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 3.06

    DB:3.06:Start Work Of Using Ice To Debug Empty I.Mx6solo Board pk



    Hi guys:

    today, i started to work on i.MX6solo board, it's empty. I used ARM DS-5 debugger to connect it, but failed(please see attachment).

    I find that I just have only i.MX6Q configure file of i.MX6 in locate:C:\Program Files\DS-5\sw\debugger\configdb\Boards\Freescale\i.MX6 Quad (Generic)\Freescale_iMX6_Quad.rvc.

    i think there should be some files like "i.MX6 Solo", but there isn't(my configure file is in attachment too).

    Is my questions generated by it?

    if there aren't any problems, what can i do to download my image file to the iRAM or SDRam? i just want to run a little test program like "Hello World!",

    the bootloader will be developed latter.

    need your help

    Thanks

    DB:3.06:Start Work Of Using Ice To Debug Empty I.Mx6solo Board pk


    Sorry, i describe the problem with some mistake, i will current it next time, sorry.

  • RELEVANCY SCORE 2.94

    DB:2.94:Conveting Old Reference Design Examples j8



    I just got a new Spartan 6 starter kit (SP601) and was wondering if anyone has taken the Spartan 3E referrence design examples and convertered them to the new board. Since the new board no longer has the LCD, has anyone thought of sending the data to the computer (maybe via ethernet connection)?

    DB:2.94:Conveting Old Reference Design Examples j8


    I just got a new Spartan 6 starter kit (SP601) and was wondering if anyone has taken the Spartan 3E referrence design examples and convertered them to the new board. Since the new board no longer has the LCD, has anyone thought of sending the data to the computer (maybe via ethernet connection)?

  • RELEVANCY SCORE 2.90

    DB:2.90:Simulation For Mig Core In Sp601 jj



    I m using sp 601 evaluation board. I generated a MCB block using MIG tool.

    When i specified the Elpedia DDR2 in the MIG tool , the tool complained that simulation model are not provided for elpedia even though it generated the core.

    My questions are

    1. Can i use the generated core for spartan 6 fpga on the sp601?

    2. How do i simulate the core?

    3. I tried to implement the design (just the core) but ISE 12.1 is complaining regarding timing.How do i get red of this error?

    I would really appreciate if someone can help.

    DB:2.90:Simulation For Mig Core In Sp601 jj


    You should probably take a look athttp://www.xilinx.com/products/boards/sp601/refere​nce_designs.htm which has some information on a MIG reference design for this particular board.

    You can download Elpida DDR2 simulation models from Elpida directly:http://www.elpida.com/en/products/ddr2.html

    Post the specific information on the timing error and perhaps someone can help.

  • RELEVANCY SCORE 2.86

    DB:2.86:Debug Assertion Failed kx


    Can this error be fixed with a download?

    DB:2.86:Debug Assertion Failed kx

    hello
    have you tried checking in ToolsInternet OptionsAdvanced and unchecking the
    "enable debugging" and "display script errors" boxes?

    Please click the Check Mark As Answered Check Mark On This Page If this post helps to resolve your issue, as it helps others who need quick access to Answers THANK YOU AND GOOD LUCK

  • RELEVANCY SCORE 2.85

    DB:2.85:Microblaze Debugging km



    Hello,

    I'm using ISE 14.2 and SP605 board and there is some troubles with Microbaze debug. When I download simple application in FPGA using "Program" tool - all is OK. But when I start debugging, error "Target reqest failed: Target is not suspended" appears randomly. In one cases there is, in other - not.

    Does anyone have a hint?

    Thanks so much.

    Leofr.

    DB:2.85:Microblaze Debugging km


    Thank you, I have solved the problem. Now I launch debugging by another way, and it allows to debug with no errors.

  • RELEVANCY SCORE 2.82

    DB:2.82:Memory Interface Generator (Mig ) On Spartan 6 Sp601 Evaluation Platform 3a



    Hello,

    I have a Spartan 6 SP601 evaluation board . To use the memoory (DDR2 Ram ) on my board , I created a MIG core using the CoreGen . I came across some issues with the Pin allocations . I need to design a counter that can store upto 100 numbers in the DDR 2 RAM and print them back . Could you help me with the memory interface to efficiently use the memory after the creation of the MIG ?

    Regards

    David

    DB:2.82:Memory Interface Generator (Mig ) On Spartan 6 Sp601 Evaluation Platform 3a


    What was the pin allocation issue? Make sure you base the design on the supplied UCF. There's only going to be one way you can configure the pins, as the hardware is fixed.

    Efficient use of the MIG will depend entirely on what your requirements are. For information on how to actually drive the MIG, first read and understand the documentation thoroughly (UG416 and UG388, I think). Look at the traffic generator reference design to see how to drive the MIG, or if that's too complicated, have a look at the example code in thisXilinx MIG tutorial.

    I can't really see any reason why you wouldn't just use BRAM for only 100 numbers,unless this is purely an academic exercise.

  • RELEVANCY SCORE 2.82

    DB:2.82:Linux Cable Drivers, Sp601. Problem 9d



    I have the SP601 start board.

    I am trying to install the cable drivers for Linux.

    In UG344.pdf. p. 11, Table 1-1 there is a list of possible USB cables tha tI am suppose to choose from.

    DLC10, DLC9 and a few other codes.

    It is not clear which one I should choose since in the SP601 user guide, the only name that appears for the usb cable is:

    Type A end to host, Type Mini-B end to SP601 board.

    Please advise which of the Xilinx USB Cables listed in UG344.pdf. p. 11, Table 1-1 should I select in order to complete the Linux cable driver installation ?

    thanks

    Dag

    DB:2.82:Linux Cable Drivers, Sp601. Problem 9d


    To answer your question:

    I found another posting " installing platform cable USB II (ubuntu)" in the forum

    Installation and Licensing

    I was able to succeed by following the solution there.
    Thanks
    Dag

  • RELEVANCY SCORE 2.81

    DB:2.81:Voltage Buffers Requried? z7



    Hi all,

    We are developing custom add-on card for sp601 board. Where the reference IO voltages of sp601 board is 2.5V and DAC in add-on card is 3.3V device.

    Vmin for Logic 1 in DAC is 2.2 V. I hope 2.5V for logic 1 from FPGA will also be considered as logic 1 in DAC!!

    or Should we have to use 2.5V to 3.3V buffer to interface to DAC?




    FPGA freak

    DB:2.81:Voltage Buffers Requried? z7


    Please refer to the Spartan 6 Datasheet DS162, Table 9.

    Even though VCCO to the (non-DDR) IO banks of the FPGA is 2.5V, the IO pins are tolerant of Vin up to 4.1V (as long as the PCI clamp diodes are not enabled).

    The FPGA can handle 3.3V logic inputs, and the 2.5V logic outputs should have sufficient Voh to drive 3.3V logic inputs on your DAC board.

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.80

    DB:2.80:Spartan 6 Sp601 Application Source Code 7c



    Is it possible to get the host application source code for the SP601 Base Reference Design. (originally rdf0003.zip)

    This is the program that demonstrates the DSP and Logic functionality of the board by processing

    images with various filters.

    I am interested in studying the host application and how it passes data and command information to and from the

    SP601/SPARTAN6 system. The HDL files are there and are well documented and complete.

    Thank you.

    J. C.







    Solved!
    Go to Solution.

    DB:2.80:Spartan 6 Sp601 Application Source Code 7c


    I set up a packet sniffer between the PC and the SP601 to capture frame transfers of the image data before and after the processing occurs. The ethernet frames are non-standard transfers. There seems some pre-filtering or data formating going on on the PC before the image data is streamed to the FPGA for processing.

    I completely understand the VERILOG code provided in the reference design. What I was hoping to get a copy of is the source code for the application running on the PC that performs this pre-processing and data transfer functionalilty.

    Having this code will complete my understanding of how data is handled by the FPGA across the ethernet PHY.

    Will Xilinx be able and willing to provide this PC application code?

    Thank you,

    JIm

  • RELEVANCY SCORE 2.77

    DB:2.77:Which Boards Can Measure Current (Sp601 Or Sp605) 73



    I understand that the SP605 can measure the current and voltage of the board or just the FPGA. Is this correct?

    Am I right to think the SP601 cannot measure the current of either? However, the PDF Getting Started with the Xilinx Spartan-6 FPGA SP601 Evaluation Kit (UG523) states as a feature: "Current measurement on 3.3V, 2.5V, 1.8V, and 1.2V supplies." Can somebody please clarify this for me.

    I am fairly unknowledgeable in this area, so please excuse me if the answer is obvious.

    DB:2.77:Which Boards Can Measure Current (Sp601 Or Sp605) 73


    Does the TI USB work with an already generated bitfile, or do I need to insert IP into my design?

    What about if I want to use System Monitor? Would I need to integrate it into my design?

  • RELEVANCY SCORE 2.77

    DB:2.77:Mig Testing Ug818 z3



    I have three DDR3s in my design. I want to develop a DDR test for production. I plan to emulate the UG818 tutorial.

    I have a SP601 Dev board. I want to do Hardware Co-sim for my design similar to this tutorial. I need to develop a

    Board Support Package for my board to get the Hardware Co-sim check box to show up in ISE.

    How do I create a .bsp file for my design?

    Thank you,

    DB:2.77:Mig Testing Ug818 z3


    Bob,

    I am just using the SP601 design to work thru the HW-cosim tutorial. I am appling this to my own hardware. I am aware that the SP601 is DDR2 but the MIG generation and testing procedure is what I am trying to emulate with my custom hardware.

    I have narrowed my focus to testing just 1 DDR3 ram on my design. I will expand this once I get a single MCB/DDR3 connection verified. This is my first experience with the Xilinx MIG and MCBs. Following the tutorial I generated my MEM1_mig.v, Use the example mig_dut.v as a guide for my MEM1_mig_dut.v. I created my MEM1_mig_hw_tb.v from the example mig_hw_tb.v. I have added my modified constraints file separating external I/O from Test bench driven I/O. I have run the ISIM with HW-cosim. I am working through some contraint errors.

    The design compiled Isim pops up with signals showing. Nothing is running when simulation is started. I am working though these issues now.

    Thank you for your continued support and guidance.

    Andrew

  • RELEVANCY SCORE 2.76

    DB:2.76:Fmc Of Sp601 k3



    hello,everyone.

    we know that Spartan-6 FPGA SP601 boardhas oneFMC-LPC connector ,and we can extend our applications to video、audio、and so on ,but where to find the FMC daughter cards ?

    I have read the document 《I/O Design Flexibility with the FPGA Mezzanine Card (FMC)》 ,but only to find FMC-Video Mezzanine Board, where to find FMC-Audio Mezzanine Boardor other application cards.

    thanks sincerely!







    Solved!
    Go to Solution.

    DB:2.76:Fmc Of Sp601 k3

    You couldalways design and build a FMC with the components that you need.



    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.74

    DB:2.74:Sp601 - Spartan-6 Ibis Model - Ddr2 Si Simulation a7



    Hi, I'd like to do some simulation of SP601 and I would like to gettheSpartan-6 Ibis file for SP601 board to learn how totest DDR2 signal Integrity channels. I tried to generate it from a MCB core inISE but I think I do not have a correct/complete pin planning. I'm pcb designer and not really into the ISE thing...

    Thanks for help.







    Solved!
    Go to Solution.

    DB:2.74:Sp601 - Spartan-6 Ibis Model - Ddr2 Si Simulation a7

    You can download the models herehttp://www.xilinx.com/support/download/index.html/​content/xilinx/en/downloadNav/device-models/ibis-m​odels/spartan-series-fpgas.html



    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.71

    DB:2.71:Sp601 Base System Reference Design Continuous Tx 13



    I’m currently using the BSR provide for the SP601 board and would like to change the logic to always send a user status message; even without receiving a user acknowledgement message from the GUI.

    It would seem that I would be able to set one of the variables high (faking out a message received from the GUI)so that once one message has been transmitted (user status), the next message can be sent.

    Any help would be appreciated.

    DB:2.71:Sp601 Base System Reference Design Continuous Tx 13


    In addition, I have found that if I constantly request data from the SP601 every 10ms I receive about 30 message at about 15msthen the SP601 starts to slow up and only responds onceevery 50ms.

    Is there a way to expain why it is reacting this way?

  • RELEVANCY SCORE 2.71

    DB:2.71:Sp601 Ref Design Problem 8m



    I have a similar problem as referenced in this older thread.

    http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Cant-Boot-new-Spartan-6-SP601-Board/m-p/47815

    and

    http://forums.xilinx.com/xlnx/board/crawl_message?board.id=XLNXBRDmessage.id=3929

    I CAN get it to run the hyperterminal interface and run and pass all the BIST tests, but then loading the reference design with the proper settings leads to a link status of "Not Connected to the FPGA,, even though on both the board and the ethernet port on the computer the green light is blinking so there is activity.

    I've tried out the tip from http://www.xilinx.com/support/answers/33229.htm but it didn't help out. SW2 is ON/OFF ethernet cord IS directly connected to computer. but it won't link up.

    Any extra solutions or tips would really help.

    DB:2.71:Sp601 Ref Design Problem 8m


    I have a similar problem as referenced in this older thread.

    http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Cant-Boot-new-Spartan-6-SP601-Board/m-p/47815

    and

    http://forums.xilinx.com/xlnx/board/crawl_message?board.id=XLNXBRDmessage.id=3929

    I CAN get it to run the hyperterminal interface and run and pass all the BIST tests, but then loading the reference design with the proper settings leads to a link status of "Not Connected to the FPGA,, even though on both the board and the ethernet port on the computer the green light is blinking so there is activity.

    I've tried out the tip from http://www.xilinx.com/support/answers/33229.htm but it didn't help out. SW2 is ON/OFF ethernet cord IS directly connected to computer. but it won't link up.

    Any extra solutions or tips would really help.

  • RELEVANCY SCORE 2.70

    DB:2.70:Clock Dedicated Route Fix - Sp601 9z



    Hi,

    I am using a SPARTAN SP601 development board and have designed a mezzanine board to connect to the FMC connector which is already completed.

    An error I think I made was to use one of the regular user defined pins to bring in the “clock” instead of CLK0_M2C_P or similar pin. When I design the FPGA, I therefore have to use CLOCK_DEDICATED_ROUTE = FALSE in my UCF to allow the design to route. I think this is because the software recognizes that the user defined pin with my “clock” is connected to the clock of a logic block (flip flop for example). My actual application “clocks” will be at ~350MHz and 10MHz and as it stands, on the actual board they are already wired to user pins.

    I was wondering if anyone knows a good method to connect the user defined pin to the true clock pin so that I do not have that error / warning.

    I think it would be a better design to have this connected – am I right on this?

    Thanks very much, I appreciate your help and any advice as I haven’t routed one of these in a long time.

    DB:2.70:Clock Dedicated Route Fix - Sp601 9z


    You can't connect an IBUF to an IBUFG because both of these are input pads.

    If the clock signal is not coming into to a global clock (GC) pin on the Spartan-6 design you will get this error/warning message. The only way to fix it is to change your FMC module.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.69

    DB:2.69:Sp601 Sample Vhdl Project With The Ethernet Link dm



    Dear all,

    I'm a newby to xilinx FPGAs. I had experience with Altera FPGAs, but not Xilinx.

    I work in a public research institution and I was asked to make an embedded system with the SP601 development board and the idea is to use extensively the GBE link.

    To my surprise I find the Xilinx documentation a bit, or quite a bit, limited. I don't find any sample project with the sources in VHDL and the C-code of a sample application like a simple webserver. Furthermore, there is no tutorial showing step by step how to do it with the Xilinx dev board SP601, which I think is a bit discouraging...

    Could anyone provide me with some help to go through? I've read many of the manuals but it's not easy to get something done without a proper example with the sources...

    I think that Xilinx should ease the people to get these kind of things for free (as Altera does...) because the time we have to invest figuring out by our selves becomes quite expensive and finally frustrating. I'm sure there are bunches or simple projects that could be used and readapted for our purposes...

    Thanks in advance for your help.

    DB:2.69:Sp601 Sample Vhdl Project With The Ethernet Link dm


    Has anyone else had the issue where, after downloading the bitfile, the fms, and the elf, the program starts, i get the menu, the RX LED on the board blinks with laptop traffic, but NOTHING is TX-ed from the SP601 to the laptop??

    I tried reloading, buut was wondering if there was a jumper setting that would matter for ethernet?

    Thanks,

    TMB

  • RELEVANCY SCORE 2.69

    DB:2.69:Sp601: Temac: Data Transmission. f8



    I was able to generate bit file for the example program that ships with "LogiCORE IP Tri-Mode Ethernet MAC v5.1". I didnt did any changes to this example, with out any modifications I generated bit file. I made one to one connection between PC and SP601 board. I burned the file to SP601 board and configured the boards DIP switch (SW8) to "max_speed[0]" and enabled the "Enable_pat_gen". The status of 3rd LED -"Pat check Pass" is ON. "update_speed" push button is also pressed. Link Ststus "tx" LED is blinking.

    Made settings as per Figure 17-5 in page 205 of "ug777_tri_mode_eth_mac.pdf".

    I ran "Wireshark" tool. In wireshark, I am not able to intepret the data. Please, any one let me know of what I did so far is write or wrong and also need help on how to validate the data from board using Wireshark.

    In Wireshark log, I am not able to find the MAC address of SP601 board, which means no data is being received though SP601 "tx" LED is blinking?

    What about IP address, where in code level I can mention the IP address?

    Any help is much appreciated.

    Thanks,

    Regards,

    Manohar Reddy

    DB:2.69:Sp601: Temac: Data Transmission. f8


    Hi

    The pattern generator data will be send with “5A-01-02-03-04-05” as Source Address and“DA-01-02-03-04-05” as destination address.

    You can see the frames captured in wirshark with these addresses as below snapshot.

    The Ethernet packet at the Mac layer doesnot IP addresses embedded in it as the IP address will be used in the network layer and to use it you need to have a stack developed over the MAC layer.




    Regards,Satish--------------------------------------------------​--------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful.--------------------------------------------------​-------------------------------------------

  • RELEVANCY SCORE 2.69

    DB:2.69:Spartan 6 Multiboot - Config Header ff



    For the"programming" part I followed the xt038 instructions to create 2 bit streams (Golden_image, Multiboot_image) as samples for SP601 board. Then use this sample batch file along with boot_header_onl_SPI_x1.hex (for the address of each bit stream). The SP601 reference design "run_all_bulid_script.bat" is:

    --------------------------------------------------​​-------------------------------------------------​-​------------------------------------

    cd golden_image

    rem run xilinx tools through synthesis, ngdbuild, map, place route, and bitgen for "golden_image"call run_xilinx_tools.bat

    cd ..

    cd multiboot_image

    rem run xilinx tools through synthesis, ngdbuild, map, place route, and bitgen for "multiboot_image"call run_xilinx_tools.bat

    cd ..

    cd PROM_files

    del *.mcs

    rem convert boot header file from editable HEX file to MCS filerem (i.e. edit boot header HEX to change jump addresses for golden and multiboot images)promgen -w -p mcs -r boot_header_only_SPI_x1.hex -o boot_header_only_spi_x1.mcs

    rem create combined MCS with golden and multiboot images but missing boot header MCSpromgen -w -p mcs -spi -s 16384 -u 010000 ../golden_image/goldenboot_lwir_spi_x1.bit -u 400000 ../multiboot_image/multiboot_lwir_spi_x1.bit -o incomplete_dual_image_lwir.mcs

    rem combine boot header with golden and multiboot image into one MCS file for iMPACTtype boot_header_only_spi_x1.mcs incomplete_dual_image_lwir.mcs header_golden_multiboot.mcsrem delete intermediate MCS files to avoid confusiondel incomplete_dual_image_lwir.*cd ..

    --------------------------------------------------​​-------------------------------------------------​-​------------------------------------

    Tthe "header_golden_multiboot.mcs" file contains the golden_image, multiboot_image, header files. The xt038 said, using Impact to download to PROM via JTAG/SPI, then it should work.

    No: the programming failed :-(

    I noticed that, normally when generating a mcs file for SPI PROM via Impact (GUI),IMPACT also generates other two files along with the design_xx.mcs: - design_xx.cfi and design_xx.prm.

    The reference design (xt038) process did not create"header_golden_multiboot.cfi" and "header_golden_multiboot.prm" files.

    There are "boot_header_only_spi_x1.cfi" and "boot_header_golden_spi_x1.prm" , which covered the header part.

    also "incomplete_dual_image_lwir.prm" and "incomple_dual_image_lwir.cfi" generated for two image files, but they are deleted by the script . Is there any way to combine those sets? they are not in the same format:

    - boot_header_golden_spi_x1.prm and boot_header_golden_spi_x1.cfi: bus wdith is 8, device is 1K

    - incomplete_dual_image_lwir.prm and incomplete_dual_image.cfi: bus width is 1 device is 8192K

    I could not create/combine the golden_image and multiboot_image in Impact (GUI), the instruction is not intuititve enough for me, specially the header file.

    Anyone know what need to add in the "run_all_build_script.bat" script to make *.cfi and *.prm files? or using the IMPACT (GUI) to specify the PROM address of each image to make it behaves as advertised in SP601 Reference Design document?

    DB:2.69:Spartan 6 Multiboot - Config Header ff


    the final .mcs file will not have the .prm and .cfi since this .mcs file is not generated by promgen, but by windows dos command in the .bat file

    rem combine boot header with golden and multiboot image into one MCS file for iMPACTtype boot_header_only_SPI_x1.mcs incomplete_dual_image_SP601.mcs header_golden_multiboot.mcs

    you can ignore the warning message of the .cfi file requirement during flash programming.

    --Krishna

  • RELEVANCY SCORE 2.68

    DB:2.68:Unable To Start Debug Session: Error- Processor Configured As Dpm/Lsm Opposite Of The Project Settings. d8



    Hi ,

    I am working with the MPC5675K evaluation board and the development environment is Codewarrior 10.5.

    I have successfully been able t download the code onto the target earlier. The codes were in LSM and DPM configurations and have not faced any issue. However since yesterday there seems to be a problem with doing the same.

    I am trying to flash a simple Bareboard C project that is given as a startup code within codewarrior in DPM mode and i get the following error message.

    Error launching Test_MPC5675K_DPM_FLASH_PnE USB-ML-PPCNEXUS

    EPPC GDI protocol error: Failed to configure target. Processor configured as DPM/LSM opposite of the project settings.

    There are no debug logs, since this is failing at the very first step.

    I am also attaching the expert diagnostics file generated by Codewarrior.

    Thanks in advance for the help.

    Girish Rao Bulusu

    DB:2.68:Unable To Start Debug Session: Error- Processor Configured As Dpm/Lsm Opposite Of The Project Settings. d8


    Hi,

    I had a word with an engineer from Freescale regarding this issue, and it turns out that the Shadow Flash block which contains censorship word got corrupted. The only way to fix the problem according to them was to replace the board altogether.

    So then my department did go ahead and order a new board.

    Sorry for being the bearer of bad news. Hope you find a work around and do let us know.

    Regards,

    Girish Rao Bulusu

  • RELEVANCY SCORE 2.68

    DB:2.68:Sp601 Ethernet Help xx



    I know the SP601 has an ethernet port which is used for communication as shown by the base reference design, however, is there any tutorial on how to do this ethernet communication yourself?

    Is the source code for the base reference design gui available?

    Also, is there a simple example design which shows the use of the ethernet port?

    I want to be able to use the ethernet communication for other applications.

    Also:

    Does the source code for the Base reference design actually work? To install it onto a board, are you supposed to load both the DSP48A design along with the logic design? Or is the source code just for show, and you must use the "ready for download" folder in the sp601 brd design.

    Thanks,

    DB:2.68:Sp601 Ethernet Help xx


    Did you ever get anything working for communicating between the FPGA and GUI? I'm looking for more information onhow theBRD sends data to the GUI.

  • RELEVANCY SCORE 2.68

    DB:2.68:Programming Fpga On Sp601 Board 7a



    I m a Newbie.What are the possible ways of programming fpga on sp601 board?

    I do not have FMC connector attached.

    Would appreciate if some one can help.

  • RELEVANCY SCORE 2.68

    DB:2.68:Spi With Sp601 Board ja



    SP601 Board

    Hi all,

    I would like to program the fpga via spi and an external MCU .

    MCU - master

    FPGA -slace

    Mode PINs M0 and M1 - ON

    DIN - J12 - TDO

    CLLK - J12 TCK

    Program - J12 PIN 1

    When I'm starting the serial bitstream either CSO/MOSI toggle or DOUT reflects the input stream.

    Has anybody managed to program the fpga in slave mode ?

    thx







    Solved!
    Go to Solution.

    DB:2.68:Spi With Sp601 Board ja


    Many thanks for your reply Gabor.

  • RELEVANCY SCORE 2.67

    DB:2.67:Mpower Board Failed With A2 Debug...Help!! ca




    Had this board up and running for a week. A little sketchy, rebooted a couple times by itself. Other than that, working fine. Then last night, I went to sleep while letting it finish a huge game download. When I checked it in the morning, the screen was black with A2 in the bottom right corner, ALL the blue CPU LEDs were lit up and the damn DrMOS alarm led next to the CPU leds was on. Tried rebooting, comes on and off a few times then sticks on the A2 black screen. Im using a 3770k, a kit of Crucial Ballistix Tactical 16GB 1600, (the MSI board defaults it to 1333?!) and a Thermaltake TR2 750w Bronze.

    DB:2.67:Mpower Board Failed With A2 Debug...Help!! ca


    Dont worry i just had the same problem recently and fixed it, and here is how.

    This happened when i updated my bios drivers when oc genie was on and i tried to reset cmos. But the solution was easy.

    I switched to the second bios using the switch on the lower right side of the motherboard, and booted to windows. From there i made a bootable usb to flash bios using the msi bios update tool. Then i rebooted to the usb and right before i hit flash, i switched the switch back to the first bios. Then i flashed it and reset cmos after it was done. It didnt boot for few times, so i removed my hdmi from back of my graphics card and put it back again and it booted normally. Hope it helps.

  • RELEVANCY SCORE 2.65

    DB:2.65:High Level Source Code For Base Reference Design Interface Project 7f



    Hello,

    I have installed the Base Reference Design Interface demo for the SP601 board. The installation seems to install the executables and the SP601 board source file (vhd and/or verilog)but not the high level projectsource.

    I have not been able to locate the high level source code (VB or VC++) project that drives the FPGA code on the board.

    Has anybody downloaded it or could youpoint me out to it?

    Regards,

    DB:2.65:High Level Source Code For Base Reference Design Interface Project 7f

    Hi Heldeeb and Kumudnepal,Is there any investigation about these source codes? I'm looking for similar codes and I guess more people looking for same codes? Can Xilinx experts help us please?Best regards. Thank you.

  • RELEVANCY SCORE 2.65

    DB:2.65:Upgrade Sp601 To Lx45? zz



    Can the SP601 board be upgraded to the LX45?

    The FAQ is ambiguous:

    6. Can I upgrade to a larger or faster device? A: Yes, you can but to do so voids the Xilinx warranty and support for the board will not be provided. In general, the CS324 footprint allows upgrading the on-board FPGA to the LX25, but is not designed to support the LX45T.

    DB:2.65:Upgrade Sp601 To Lx45? zz


    Can you replace the LX16 with a LX45? Yes.

    However, the LX45-CS324 has 218 IO vs the LX16-CS324 with 232 IO. The functionality of the modified board will be dependent on which 14 IOs are no longer connected on the board.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.65

    DB:2.65:Problem When Try To Debug Program On Kl16 Over Freedom Board Kl25 fx



    I have install CodeWarrior 10.5 with the newest version USBDM driver and ARM Flash Programmer.

    I have created programm to pull high one pin on PORTA. Before download code I connect SWD pin from KL25 (FRDM-KL25_SCH) to my board where is KL16,

    http://usbdm.sourceforge.net/USBDM_V4.10/Freedom/html/freedom_setup.html

    download that code to chip with FlashProgrammer from CW, measure voltage on pin and it works fine.

    Also, when I download program with newest version USBDM ARM_FlashProgrammer,

    Debugging FRDM-KL05Z with USBDM | MCU on Eclipse

    it works fine.

    Problem is when I try to debug code, it return message: "Failed to resume target process. Downloading binary to target.....".

    I have try this with CW 10.4 and older USBDM driver but without success.

    What I'm doing wrong?

    Looking to hearing from You.

    Thank You in advance!

    DB:2.65:Problem When Try To Debug Program On Kl16 Over Freedom Board Kl25 fx


    Hi Mirza,

    USBDM doesn't support KL16 - mainly because I didn't know it existed.

    When you use the stand-alone programmer which device are you selecting?

    It may be possible to use the standalone programmer with the 'wrong' chip but Codewarrior use requires the actual chip to be supported.

    You can try adding an alias to the C:\Program Files (x86)\pgo\USBDM 4.10.6.100\DeviceData\arm_devices.xml file.

    Add the following line after line 1780 (make obvious changes for the actual device you are using):

    device name="KL16Z32M4" alias="MKL15Z32M4" hidden="true"/

  • RELEVANCY SCORE 2.65

    DB:2.65:Sp601 Max Voltage On J13 Gpio Pin 3x



    I have a SP601 starter kit board and was wondering if I can place a 15v signal without frying the board. Thank you for your help.

    DB:2.65:Sp601 Max Voltage On J13 Gpio Pin 3x

    You stated the first step is to measure the 0-1 levels. Ranging on the
    signal, I have 13-15 and 14-15; therefore a 1volt to 2 volt
    differential.

    Is your "15V signal" a differential pair? What do the numbers "13-15" and "14-15" represent?

    Please be as concise and unambiguous as possible in your response.

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.65

    DB:2.65:Edk With Eval License 87



    Hello everybody!I will be using the SP601 for an academic project, and would like to try invoking a MicroBlaze in my design.Since the SP601 only includes the WebPack and the timeline of the project is limited, I came up with the idea of using an Evaluation License of the EDK to do some experiments with the MicroBlaze based designs. Picoblaze is no option, since I also want to try out a protocol stack which is designed exclusively for MicroBlaze.So my question, is it possible to use MicroBlaze with an Evaluation License of EDK on the SP601 board?Looking forward to your replies,Z.

    DB:2.65:Edk With Eval License 87

    I would be grateful for any suggestions related to this matter, because unfortunately

    I don't find a clarifying thread in the forum or statement in the Licensing FAQ.

  • RELEVANCY SCORE 2.64

    DB:2.64:Spartan 6 Multiboot - Problem With Generate Combined Mcs File For Downloading To Prom Via Impact d9



    For the"programming" part I followed the xt038 instructionsto create 2 bit streams (Golden_image, Multiboot_image) as sample command for SP601 board. Then use this sample batch file along with boot_header_onl_SPI_x1.hex (for the address of each bit stream). The SP601 reference design "run_all_bulid_script.bat" is:

    --------------------------------------------------​--------------------------------------------------​------------------------------------

    cd golden_image

    rem run xilinx tools through synthesis, ngdbuild, map, place route, and bitgen for "golden_image"call run_xilinx_tools.bat

    cd ..

    cd multiboot_image

    rem run xilinx tools through synthesis, ngdbuild, map, place route, and bitgen for "multiboot_image"call run_xilinx_tools.bat

    cd ..

    cd PROM_files

    del *.mcs

    rem convert boot header file from editable HEX file to MCS filerem (i.e. edit boot header HEX to change jump addresses for golden and multiboot images)promgen -w -p mcs -r boot_header_only_SPI_x1.hex -o boot_header_only_spi_x1.mcs

    rem create combined MCS with golden and multiboot images but missing boot header MCSpromgen -w -p mcs -spi -s 16384 -u 010000 ../golden_image/goldenboot_lwir_spi_x1.bit -u 400000 ../multiboot_image/multiboot_lwir_spi_x1.bit -o incomplete_dual_image_lwir.mcs

    rem combine boot header with golden and multiboot image into one MCS file for iMPACTtype boot_header_only_spi_x1.mcs incomplete_dual_image_lwir.mcs header_golden_multiboot.mcsrem delete intermediate MCS files to avoid confusionrem del incomplete_dual_image_lwir.*cd ..

    --------------------------------------------------​--------------------------------------------------​------------------------------------

    Ibelieved the "header_golden_multiboot.mcs" file contains the golden_image, multiboot_image, header files. The xt038 said, using Impact to download to PROM via JTAG/SPI, then it should work.

    No: the programming failed :-(

    At first I thought, theremight be an issuewith my hardware or ISE 14.7 (I don't use SP601 board). Struggling for a few days,then using IMPACT (GUI) tocreate a normal mcs of a normal design (no multiboot, writing to ICAP etc), with the same board, the Impactprogramming worked well.

    I noticed that, whengenerating a mcs file for SPI PROM via Impact (GUI),IMPACT also generatesother two files along with the design_xx.mcs: - design_xx.cfi and design_xx.prm. There is a warning when I first programmed the mcs from the script, but I ignored: I believed the reference design process ... lol

    The reference design (xt038) process did not create "header_golden_multiboot.cfi" and "header_golden_multiboot.prm" files.

    There are "boot_header_only_spi_x1.cfi" and "boot_header_golden_spi_x1.prm", which covered the header part.

    also incomplete_dual_image_lwir.prm and incomple_dual_image_lwir.cfi generated for two image files. Should I manually edit and put them together in to a form like "header_golden_multiboot.cfi" and "header_golden_multiboot.prm" ????

    I could not create/combine the golden_image and multiboot_image in Impact (GUI), the instruction is not intuititve enough for me.

    Anyone know what need to add in the "run_all_build_script.bat" script to make *.cfi and *.prm files? or using the IMPACT (GUI) to specify the PROM address of each image to make it behaves as advertised in SP601 Reference Design document?

    Thank you for reading, and help if you can.

    Please, point to solution if any, not to a dozen of links to documents.

    DB:2.64:Spartan 6 Multiboot - Problem With Generate Combined Mcs File For Downloading To Prom Via Impact d9


    I believe the -s switch/option is for Flash's size, so it should be 8192 for W25Q64XX (64 megabits). The Evaluation board was on market for a long time, why no one got in to this problem ? or rarely used this board for mulitboot purpose? I was thinking to buy this board for reference, but the "discrepancies" in documents, AN made me have second thought...

    Perhaps, this kind of "issue" does not belong here (Design Tools section)? there is not much response here. May be I should repost on the Board and Kits section then.

    BTW, I tried to mannualy edit/create the *.cfi and *.prm files, but "boot_header_only.mcs" was specified as 8-bit bus while all multiboot, goldden images bit files are 1 bit. I'm confused, don't want to waste time to combine them.

    Sample file from SP601 Development Kits:

    "boot_header_only_SPI_x1.cfi"

    --------------------------------------------------​----------------------------------------------

    # PROMGEN: Xilinx Prom Generator O.40d# Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

    SOFTWARE_VERSION O.40dDATE 02/23/2011 - 07:47SOURCE boot_header_only_SPI_x1.mcsDEVICE 1K -- what is it?DATA_WIDTH 8FILL_DATA 0xFFSTART_ADDRESS 0x00000000 END_ADDRESS 0x0000003A DIRECTION_UP "boot_header_only_SPI_x1.hex"

    --------------------------------------------------​-------------------------------------------------

    "dual_image_lwir.cfi" generated by sample script:

    --------------------------------------------------​--------------------------------------------------

    # PROMGEN: Xilinx Prom Generator P.20131013# Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

    SOFTWARE_VERSION P.20131013DATE 08/25/2014 - 16:21SOURCE incomplete_dual_image_lwir.mcsDEVICE 16384K -- should be 8,192 for W25Q64BV on SP601 ???DATA_WIDTH 1FILL_DATA 0xFFSTART_ADDRESS 0x00010000 END_ADDRESS 0x0017AE03 DIRECTION_UP "../golden_image/goldenboot_lwir_spi_x1.bit" 6slx45fgg484START_ADDRESS 0x00400000 END_ADDRESS 0x0056B02B DIRECTION_UP "../multiboot_image/multiboot_lwir_spi_x1.bit" 6slx45fgg484

    --------------------------------------------------​--------------------------------------------------​-----------

    Using IMPACT (GUI) to create the combinedmcs file, when specified the first bit file for rev 0, the tool automactically assigned to address 0x0, this address was unedittable ? why? In term of multiboot/fallback design, rev 0 for the golden Image, rev 1 for multiboot image or vice versa ?it was not clear at all

    Xilinx's experts, I have read through "many" documents and tried to generate *.mcs file in both command lines and GUI versions, please help.

  • RELEVANCY SCORE 2.62

    DB:2.62:Zynq Zc702 Eval Kit Jtag Issue With Fmc Debug Card Plugged In sc



    Hello, I'm using a a Zynq ZC702 Eval Kit which I'm able to download bitstreams to the FPGA using Impact (14.1) and my Platform Cable USB II programmer. I purchased a pair of the FMC debug cards (XM105) so I can poke into my FPGA design with a logic analyzer.

    When I have the FMC card installed I'm able to see the FPGA and ARM core in impact but I receive a "Program Failed" message when I try to download a bitstream. The following is the log of the message

    INFO:iMPACT - Current time: 7/26/12 3:40 PMPROGRESS_START - Starting Operation.INFO:iMPACT:583 - '2': The idcode read from the device does not match the idcode in the bsdl File.INFO:iMPACT:1578 - '2': Device IDCODE : 00001111111111111111111111111100INFO:iMPACT:1579 - '2': Expected IDCODE: 00000011011100100111000010010011PROGRESS_END - End Operation.Elapsed time = 0 sec.

    I know the FMC becomes part of the JTAG chain but since I'm able to see the FPGA I figured I should still be programming it. I was reading the FMC debug card documentation and it was saying that the LED DS5 is "good power" indicator which for some reason is not lit on my board ... but the following LEDs are lit on my board (DS6 and DS7). I tried both FMC boards and I also tried another ZC702 board which was untouched this behavior has persisted.

    Basically, can I have the FMC debug card plugged into the board and still use my JTAG to target the FPGA? Thanks.

    DB:2.62:Zynq Zc702 Eval Kit Jtag Issue With Fmc Debug Card Plugged In sc


    You need to place a jumper across the TDI/TDO pins (67) of the JTAG header J5 in order to loop the signal back to theZC702.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.61

    DB:2.61:How To Debug A New Board Designed By Myself? m3



    I designed a new board based on "sabrelite", but I can not run any programs by usb. can Someone help me? the Debug information is as follows:

    F:\tftpbootsb_loader.exe -f sdk_unit_test_ALL.bin

    Executed plugin successfully.

    Succeed to download sdk_unit_test_ALL.bin to the device.

    Failed to run plugin sdk_unit_test_ALL.bin to the device.

    F:\tftpbootsb_loader.exe -f sdk_unit_test_ALL.bin

    Failed to initialize memory!

    Failed to run plugin sdk_unit_test_ALL.bin to the device.

    DB:2.61:How To Debug A New Board Designed By Myself? m3


    several questions.

    - the logs are the result of running this same command twice?

    - are you sure sb_loader.exe is suitable to run on your board? is the format of 'sdk_unit_test_ALL.bin' correct?

    - what do you mean by debug a new board? already boot up or just attempt to boot up?

    Have you modified the normal things like ddr script, etc?

  • RELEVANCY SCORE 2.61

    DB:2.61:Source File Afifo_Synth.V Lost From 13.X To 14.4 cf



    try to regenerate all cores, or generate program file:========================ERROR:sim - Failed to set default project options.ERROR:sim - Unable to create project from file '/home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/afifo.xco '.ERROR: could not migrate Core Generator project from file: /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/afifo.xco.=========================clear project files, redo, got this popup:========================The required file /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/afifo_synth.v for the IP core afifo.xco was not found in the IP core source directory. In order for synthesis to run successfully, you will need to either copy the file(s) to the IP core source directory or regenerate the core. Would you like to create these files by regenerating the IP Core? Click "Yes" to regenerate this IP core to create the necessary file(s). Click "No" to skip regeneration of this IP core only.The Regenerate All Cores process in Project Navigator can also be used to automate the regeneration of all cores in the project.Click "Abort" to exit the process and return to Project Navigator.=========================try to manage or regenerate afifo.xco core, got this in coregen:========================There is no project open.You may browse the IP Catalog but you will not be able to generate any cores until you open or create a project.========================in console, it says:========================Welcome to Xilinx CORE Generator.Help system initialized.The IP Catalog has been reloaded.ERROR:sim - Failed to find a part for: acr2ERROR:sim - Failed to find a part for: xa9500xlERROR:sim - Failed to find a part for: xbrERROR:sim - Failed to find a part for: xc9500ERROR:sim - Failed to find a part for: xc9500xlERROR:sim - Failed to find a part for: xpla3Loaded all available family support information.Opening project file /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/coregen.cgp.ERROR:sim - Failed to set default project options.ERROR:sim - Unable to create project from file '/home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/coregen.cgp'.ERROR:encore - Unable to migrate /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/coregen.cgp to /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/coregen.cgcCould not open project file /home/project/src/d/sp601/sp601_brd/SP601_BRD_Src/Logic/ipcore_dir/coregen.cgp.========================

    the subject, i think, is the possible cause.

    tia

    johnthan

    DB:2.61:Source File Afifo_Synth.V Lost From 13.X To 14.4 cf


    btw, i installed system edition, not dsp/embeded ones.

    maybe it is too old, i downloaded it in 2012.5 or so

  • RELEVANCY SCORE 2.60

    DB:2.60:Failed To Download Elf File On A Custom Board mp



    We are building a custom board. Here's what I ran in xmd:

    XMD% connect arm hw

    ...

    XMD% source ps7_init.tcl

    XMD% ps7_init

    XMD% fpga -debugdevice devicenr 2 -f system.bit

    XMD% dow u-boot.elf

    Downloading Program -- u-boot.elf section, .text: 0x04000000-0x0401b577 section, .rodata: 0x0401b578-0x04020f60 section, .hash: 0x04020f64-0x04020fa3 section, .data: 0x04020fa4-0x04021aeb section, .got.plt: 0x04021aec-0x04021af7 section, .u_boot_cmd: 0x04021af8-0x04021eff section, .rel.dyn: 0x04021f00-0x04025def section, .dynsym: 0x04025df0-0x04025e9f section, .bss: 0x04021f00-0x04034b5bERROR: Failed to download ELF file

    Any suggestion how to debug further? What could be the cause?

    Thanks.

    Haibing

    DB:2.60:Failed To Download Elf File On A Custom Board mp


    hello

    sir i am using microblaze project on vertex 5 , while i am using run as - launch on hardware it shows error unexpected eror while launchung program : error failed to download ELF file. i-side memory access check failed section , 0X00000050-0x0009140 not accesseble from processor i-side interface..

    anyone have any idea about this issue plzz help

  • RELEVANCY SCORE 2.59

    DB:2.59:Accessing Io On External Circuitry Conected To The Fmc Lpc Connector ad



    Hey

    I have an SP601 Board . I bought a FMC XM105 Debug Card to get access to the FMC LPC connector pins and connected my external circuitry to the pins on the debug card. Now i want to access the IO on this external circuitry using the MicroBlaze.

    I know how to access the standard io's used in the sp601 board such as the Dip Switches , Led's and Pushbutton switches using the GPIO IP (by calling the low level functions in xgpio_l.h and reading from the appropriate address mentioned in xparameters.h) on the MicroBlaze. But how do i access the IO's on my external circuitry using the MicroBlaze.

    And suggestions will be greatly helpful :)

    Thanks a lot in advance







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.59

    DB:2.59:Sp601 Uart Communication Problem 3k


    Hi,

    I Send a data in the hyperterminal through a usb_com port and connect it to sp601 board (usb input that goes to usb2uart bridge). I got at the bridge (cp2103) output the 8_bit packet but with a problem: the 1 logic was ~2.5V and when it goes down to 0 logic it was ~2V.

    I thinkthat it had something to do with my fpga design (driving to the rx_in or something) so I deleted the associated line in the UCF file but I didn't get any change.

    Another info is that when I insert the design of xilinxfrom the flash (include a testing of the hardware) and do a UART test the '0 logic' is OK.

    Does anybody have any idea?

    BR

    Zvika

    DB:2.59:Sp601 Uart Communication Problem 3k


    In the past, I have found the documentation for the boards somewhat confusing with respect to "what is RX and what is TX". In most of the documentation, it is spec'ed from the point of the USB-UART converter chip (which makes it backwards for those of us that are FPGA centric).

    For data sent by the USB-UART chip to the FPGA, the data is carried on pin K14 - this should be the FPGA input. For data sent by the FPGA to the USB-UART chip, the data is carried on pin L12 - this should be the FPGA output pin.

    Avrum

  • RELEVANCY SCORE 2.59

    DB:2.59:Programming zf



    Hi, I am trying to debug my program and download it onto my board for Freescale Cup Car. However when I attempt this i get an error message (shown in the screenshot). My board is attached to the battery and connected to the computer correctly as my computer is recognising the board. Anyone know how i fix this ? Thanks

    DB:2.59:Programming zf


    Aidan,

    Go here: http://mbed.org/handbook/mbed-FRDM-KL25Z-Getting-Started

    and here: Firmware FRDM KL25Z - Handbook | mbed

    If you are using mbed you need to modify the firmware first to permit 'programming' with mbed binaries (basically adding openSDA support).

    Daniel

  • RELEVANCY SCORE 2.59

    DB:2.59:Inout Mcb_Rzq And Mcb_Zio Are Unused For Sp601 1d



    Hi,

    i'm trying to synthesis my design for spartan-6 with evaluation board - SP601.

    the synthesis runs but for mcb_rzq and mcb_zio it write a warnning that they are unused.

    i followed thous signals from the top-level to the ncb_calibration istance (RTL from the MIG generation).

    can someone have any clue?

    thanks

    Zvika.

    DB:2.59:Inout Mcb_Rzq And Mcb_Zio Are Unused For Sp601 1d


    Both signals must be connected to package pins.

    Both of these signals appear in the reference design .UCF file. The excerpts are here:

    NET "FPGA_ONCHIP_TERM1" LOC = "L6"; ## ZIO no connect (R86 is DNP)NET "FPGA_ONCHIP_TERM2" LOC = "C2"; ## RZQ 100 ohm to GND

    The .UCF file is found, with the rest of the SP601 documentation, here.

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.59

    DB:2.59:Sp601 Ddr2 Bypass Capacitors jk



    On the SP601 Development Board, they are using 2 2.2uF and 5 0.1uF caps to bypass the 1.8 supply voltage for the DDR2 SDRAM. How were these bypass values calculated?

    DB:2.59:Sp601 Ddr2 Bypass Capacitors jk


    For more details on the caps, take a look at the PCB designers guide for Spartan-6:

    http://www.xilinx.com/support/documentation/user_g​uides/ug393.pdf

    On Page 14 it talks about which caps to use on what rails. These are the officialrecommendationthat came from testing and characterization. Use these instead of what you may find on different board layouts.




    /k

  • RELEVANCY SCORE 2.58

    DB:2.58:Orientation Of Fmc Connector On Sp601 Board? 38



    Is it possible to confirm the orientation of the FMC connector on this board? Thepicture here is very strange. The board we actually have (I don't have access to it right now) has the writing on the LINEAR chips upside down with respect to the word SPARTAN. Also, on the board we actually have the FMC connector is on the left (if we orient it with the word SPARTAN up). Now, in the hardware user guide pg 43 here, the H column of the FMC connector is on the left in the picture.

    I'm designing a board that will plug into this FMC connector and now I am extremely confused about the orientation of the connector. Is the H column closest to the edge of the board? Or the C column? Here is a picture of our board.

    DB:2.58:Orientation Of Fmc Connector On Sp601 Board? 38

    You should design you FMC mezzanine card to e compliant to the VITA 57.1 specification and it will work, including mechanically, with the SP601 and other FMC carrier cards.



    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.58

    DB:2.58:Flashing Ds1, Ds2, Ds3, Ds4, Ds5, Ds6, Ds7, Ds10, Ds17 - Spartan 6 Fpga Sp601 Evaluation Kit 7s


    I'm having some issues with a Spartan 6 FPGA SP601 Evaluation kit board. When I initially powered up the board it seemed to work fine. I have since powered up the board and DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS10, DS17 flash constantly. I assume some sort of reset has happened but i'm not sure what? Any ideas of how to revert the board back to initial setup?

    Any ideas or help would be appreciated!

    Regards,

    DB:2.58:Flashing Ds1, Ds2, Ds3, Ds4, Ds5, Ds6, Ds7, Ds10, Ds17 - Spartan 6 Fpga Sp601 Evaluation Kit 7s

    Refer to http://www.xilinx.com/support/answers/44022.html to debug board related issue.



    -----------------------------------------------------------------------------------------------Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.Give Kudos to a post which you think is helpful.

  • RELEVANCY SCORE 2.58

    DB:2.58:Getting Started With Ise On A Sp601 Board ck



    I just bought a SP601 development board with the intent of learning the ise system and make simple

    fpga designs. What I look for is a tutorial with a instructional example for my card.

    Nothing that came with the labcard was useful or contained the source code.

    By searching on the web I found a document: "ISE In-Depth Tutorial" where a stopwatch is developed from scratch.

    This looked good but it seems like the files are not for my board.

    It says:This design targets a Spartan™-3A device; however, all of the principles and flows taughtare applicable to any Xilinx® device family, unless otherwise noted.

    I suppose this means that I cannot use the source files as they come for my card.

    So my question is: Is there any tutorial at all which targets the card that I have bought. If so please

    share the link!

    Thanks

    Dan Synek

    DB:2.58:Getting Started With Ise On A Sp601 Board ck


    If you only learn to use ISE, or ISE Webpack, (without using iMPACT) you can follow this Spartan-3 example without problem. You can do "Synthesize", "Implement Design" and "Generate Programming File". SP601 has Spartan-6 (lx16), if you want to build image for SP601, you have to select the following:

    ♦ Device: XC6SLX16

    ♦ Package: FT(G)256

    ♦ Speed: -2Unfortunately, the example is for Spartan-3. You'd better to create your own design for Spartan-6 to generate programming file.

    I have just been through this procedure without proper demo for SP601.

    Goodluck for you!

  • RELEVANCY SCORE 2.57

    DB:2.57:Cant Boot New Spartan 6 Sp601 Board 91



    Got the Spartan SP601 board, box unwrapped, 11.1 installed, 11.2 patched, sample app installed, but no joy...

    The application starts and cant connect to the board. no output to hyperterminal. Ethernet resets, and Rx flashes with traffic from the laptop. No instructions on how to load the .mcs file, and no bit to download, and no sample app to build included with the kit.

    I'm beyond depressed on this one.

    Come on XIlinx guys, throw me a bone here!!!!

    Tracey







    Solved!
    Go to Solution.

    DB:2.57:Cant Boot New Spartan 6 Sp601 Board 91

    Hmmm, are you connected directly from the computer to the board? No switch in the middle? The other quick thing to try is to run wiresharkonthat interface and see if there are packets flowing . If not, check if you have the right bitfile and switch settings.Then let us know all that worked and we'll try something else.Tb

  • RELEVANCY SCORE 2.56

    DB:2.56:Imx6 Sabresd Customized Board With Sd Card Failed Booting cc



    Hi,

    I am facing board bring up for i.mx6solo customized board. The basic features are
    SD3 for bootingLPDDR2 : Configured with reference to Mx6DQSDL LPDDR2 Script Aid V0.01.xlsUART3 for Debug

    Using:

    SDK: L3.0.35_4.1.0_130816_source

    Linux BSP: board-mx6q_sabresd.c - attached

    u-boot board file: mx6q_sabersd.c - attached

    I have a LTIB installed, u-boot is buled with the script (./build_uboot.sh sd2).

    Can any one suggest me basic steeps need to be taken care to bring up the board ASAP.

    Regards,

    Vishwa

    DB:2.56:Imx6 Sabresd Customized Board With Sd Card Failed Booting cc


    Hi Vladan Jovanovic,

    Thanks for your quick replay.

    I don't have JTAG connected, Let me crossverify LPDDR2 and DRAM (i,e. Table 45-7) pin mux mapping cross verify and i will get back to you.

    Thanks Regards,

    Vishwa

  • RELEVANCY SCORE 2.55

    DB:2.55:Pacman Cant Reach Kdemod.Ath.Cx? 37



    Hi guys I think I need your help. I tried to install kdemod all day but it doesnt work.

    --------
    pacman -Syuv --debug

    Root : /
    DBPath : var/lib/pacman/
    CacheDir : var/cache/pacman/pkg/
    Targets : None

    debug: registering database local
    debug: opening database local
    debug: opening database from path /var/lib/pacman/local/
    :: Synchronizing package databases...
    debug: logaction called: synchronizing package lists
    debug: failed to get lastupdate time for kdemod (no big deal)
    debug: file path: /repo/current/i686/kdemod.db.tar.gz
    debug: using kdemod.db.tar.gz for download progresslooking up
    kdemod.ath.cx
    connecting to kdemod.ath.cx:80

    DB:2.55:Pacman Cant Reach Kdemod.Ath.Cx? 37


    thank you, Lone_Wolf!This folder is there.

    Now it is working with kdemod.podzone.net

    I would not have expected KDE to be that fast. Awesome!

  • RELEVANCY SCORE 2.55

    DB:2.55:Sp601 Example Projects. cd



    I recently acquired an SP601 development board and am still trying to figure out the nitty gritties of the bard and the painful task of loading, running, upgrading, again loading of the ISE design suite. Finally all done, now I've graduated on to the basics of the board as well as the programming. I found that there aren't enough example programs for the SP601 board in the ISE. I need to program the board to generate a MLBS signal at a freq of at least 200Mhz. and then perform certain modulations and later analyse the return signal.

    I'd be grateful if I could find some basic example programs in the line of my task in hand. I found a good PDF here... http://www.xilinx.com/support/documentation/application_notes/xapp1026.pdf

    There are applications for the TCP/IP networking stack. I'd appreciate if someone points me towards similar resource programs so that I could kick start my work.

    Regards,

    Jack

    DB:2.55:Sp601 Example Projects. cd

    If you didn't have a look yet, SP601Evaluation Kit documentation online repository:

    http://www.xilinx.com/support/documentation/sp601.htm

    Regards,

    afarn

  • RELEVANCY SCORE 2.55

    DB:2.55:Fmc Xm105 Connected To Sp601 Voltage Level 81



    I'm currently using the FMC XM105 debug card connected to a SP601 starter kit board and looking to use differential inputs located on J1:FMC_LA10_PandFMC_LA10_N. I was unable to locate the proper voltage level inputs. Do these I/Os support LVCMOS25?

    VIL min = -0.3 Volts

    VIL max = 0.7 Volts

    VIH min = 1.7 Volts

    VIH min = 4.1 Volts







    Solved!
    Go to Solution.

    DB:2.55:Fmc Xm105 Connected To Sp601 Voltage Level 81


    UG518 - SP601 HW UG Page 25

    The SP601 board VADJ voltage for the FMC LPC connector (J1) is fixed at 2.5V (nonadjustable).The 2.5V rail cannot be turned off.

    UG537 - XM105 UG

    All correctly designed FMC modules take the VADJ from the carrier card that it is the host.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.55

    DB:2.55:Base Reference Design Interface Error On Sp601 ss



    Hi there!

    I got a new Spartan SP601 Eval board and an in the process of understanding it step by step. I performed all the initial diagnostic test demo and all the tests were fine and everything working smoothly. Next I installed the Base System Reference design program, connected the ethernet cable etc. to the board, set the board on SPI config mode by swithing M0= "ON" and M1= "OFF" on SW2.

    Ran the program and it was working smoothly until I reached the step of 'Selecting a Network Application'.

    It is written that I need to select a network interface and when I do that, there's an error and the program closes itself. Have attached the screenshot. Is there a problem with my network controller? I am running this on a Win 7 PC.

    Regards,

    Jack







    Solved!
    Go to Solution.

    DB:2.55:Base Reference Design Interface Error On Sp601 ss


    kirantherock,

    The BRD will not run on Windows 7, and you will encounter issues such as you have seen.

    Please see Answer Record #40705: http://www.xilinx.com/support/answers/40705.htmfor more details on this.

  • RELEVANCY SCORE 2.54

    DB:2.54:Could Sp601 Generate A 500mhz Clock Using Dcm Without External Clock kk



    SP601:

    FPGA:Spartan-6 XC6SLX16-CS324

    Clock Generation There are three clock sources available on the SP601.

    1.Oscillator (Differential)
    The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the boardand wired to an FPGA global clock input.• Crystal oscillator: Epson EG2121CA• PPM frequency jitter: 50 ppm

    2.Oscillator Socket (Single-Ended, 2.5V or 3.3V)
    One populated single-ended clock socket (X2) is provided for user applications. The optionof 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board isshipped with a 27MHz 2.5V oscillator installed

    3.SMA Connectors (Differential)
    A high-precision clock signal can be provided to the FPGA using differential clock signalsthrough the onboard 50-ohm SMA connectors J7(P)/J8(N).

    DB:2.54:Could Sp601 Generate A 500mhz Clock Using Dcm Without External Clock kk


    SP601:

    FPGA:Spartan-6 XC6SLX16-CS324

    Clock Generation There are three clock sources available on the SP601.

    1.Oscillator (Differential)
    The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the boardand wired to an FPGA global clock input.• Crystal oscillator: Epson EG2121CA• PPM frequency jitter: 50 ppm

    2.Oscillator Socket (Single-Ended, 2.5V or 3.3V)
    One populated single-ended clock socket (X2) is provided for user applications. The optionof 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board isshipped with a 27MHz 2.5V oscillator installed

    3.SMA Connectors (Differential)
    A high-precision clock signal can be provided to the FPGA using differential clock signalsthrough the onboard 50-ohm SMA connectors J7(P)/J8(N).

  • RELEVANCY SCORE 2.53

    DB:2.53:Sp601 With External Dac c3



    Hi there,

    I have one question about the EvaluationBoard SP601 with the FMC XM105 Debug Card.

    I'd like to control the following Evaluation Module of the 260MSa/s DAC5672 by Texas Industries [link].

    Both cards are connected via SMA (clock-signal) and single-ended ribbon cable (data, 14bit).

    Is there any chance to operate this combination (fpga dac) at frequencies ~ 200MHz? I mean, is it at least on principle possible or is this whole setup a no-go?

    With clock rates about 80-90MHz everything's fine, but at higher frequencies the dac output gets more and more disturbed (the whole signal form changes totally). Perhabs it's the cable, perhabs I need some kind of termination, I don't know what to do.

    I am thankful for all help and information.

    DB:2.53:Sp601 With External Dac c3


    Ifimpendence mismatches exists there is possibility of Signal Integrity (SI) problems at higher frequencies (EX~ 200MHz).

    Please verify that by doing IBIS simulations

    You can find IBIS models for Xilinx Spartan-6 devices at: http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html

    You can find all Sp601 board files in the following SP601 boardlink.




    ________________________________________________Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.Give kudos to this post in case if you think the information is useful and reply oriented.

  • RELEVANCY SCORE 2.53

    DB:2.53:System Generator And Sdk Co-Debug Problem dc



    Hi,

    I'm trying to use System Generator and SDK to Co-Debug anEmbedded DSP Design. I follow the system generator UG tutorial example on p.214.

    I'm using Nexys3 Spartan6 based board.

    The problem is that after generation of the processor sub-system block

    no bit file is generated. Consequently the JTAG Co-SIM block can't be configured.

    If I use some of the predifined boards like SP601 the bit file is generated properly!

    Thanks in advance for your help!!!

    Eltimir

    DB:2.53:System Generator And Sdk Co-Debug Problem dc


    P.S.

    It appears that the SG - SDK co-debug is impossible with

    boards not included in the default list (like Nexys3).

  • RELEVANCY SCORE 2.53

    DB:2.53:A Custom Board Edk Problem s8



    I am designing a custom board of xcs6lx16 as the sp601, a spansion BPI flash (s29), ddr2 (same with board), ethernet( same with board)

    it runs ok in a coustom EDK project (test apps),MB with rs232 ddr2 ethernetlite;

    but when using XBD of sp601, it get wrong:

    1. just MB with rs232,it downloads and runs ok;

    2. MB with rs232, ddr2 , it can't download ,as follows,and the board 's 3.3v ,0.9v,1.8v are pull down to 1.3v, 0.5v,1.0v ,that I havn't met before.what to do with it?

    ----------------------------------------------------------------------Maximum TCK operating frequency for this device chain: 25000000.Validating chain...Boundary-scan chain validated successfully.'1': Programming device...INFO:iMPACT:501 - '1': Added Device xc6slx16 successfully.LCK_cycle = NoWait.LCK cycle: NoWaitdone.'1': Reading status register contents...[0] CRC ERROR : 0[1] IDCODE ERROR : 0[2] DCM LOCK STATUS : 1[3] GTS_CFG_B STATUS : 1[4] GWE STATUS : 1[5] GHIGH STATUS : 1[6] DECRYPTION ERROR : 0[7] DECRYPTOR ENABLE : 0[8] HSWAPEN PIN : 1[9] MODE PIN M[0] : 1[10] MODE PIN M[1] : 1[11] RESERVED : 0[12] INIT_B PIN : 1[13] DONE PIN : 1[14] SUSPEND STATUS : 0[15] FALLBACK STATUS : 0LCK_cycle = NoWait.LCK cycle: NoWait'1': Programmed successfully.VREF was lost during the current operation. It is recommended that theoperation be repeated.Elapsed time = 1 sec.INFO:iMPACT:2219 - Status register values:INFO:iMPACT - 0011 1100 1110 1100 INFO:iMPACT:579 - '1': Completed downloading bit file to device.INFO:iMPACT:188 - '1': Programming completed successfully.INFO:iMPACT - '1': Checking done pin....done.ERROR:Cse - A reference voltage has not been detected on the ribbon cable interface to the target system ( pin 2 ). Check that power is applied to the target system and that the ribbon cable is properly seated at both ends. The status LED on Platform Cable USB will be GREEN if target voltage is in the proper range and applied to the correct pin.Done!

    DB:2.53:A Custom Board Edk Problem s8


    I tested the ddr2 and ethernet, with selftest app in EDK on my custom board;

    1. MB+ ddr2; 2. MB+ethernet; 3. MB+ddr2+ethernet

    for EDK 11.5 , all 1,2,3,runs ok;

    for EDK12.3 ,1 ,2 , run ok, but 3 just mem_test runs ok, peripheral_test stops .

    I don't know what is matter.

  • RELEVANCY SCORE 2.53

    DB:2.53:How To Debug Claibration Problem? fm



    Hello!

    I have custom board with xc6slx100 of -2 speed grade. Physically there are two k4t51163qg-hce6, which are DDR2 chips by Samsung. At present I am trying to get up with just one of them, which connected to MCB3.

    So far I have successfully simulated example_design with Modelsin. There was TEST PASSED in log. So now I proceed to hardware test.

    I managed to generate binary, load it to FPGA and monitor signals using ChipScope. At this stage I see that calib_done never asserts. So I want to find the root cause of calibration failure.

    In our design RZQ and ZIO pins were not routed, so I selected uncalibrated input termination and set it to 50 Ohm. So I guess, that input termination stage is bypassed and I stuck on some next stage. Does it seem reasonable? If so, then should I proceed to DQS CenteringDebug. AR#43557 suggests to go for AR#43643, which further forwards to AR#42172. The latter one is described for SP601 board. What should I do with custom board? How do I start with debugging?

    So far I have performed some preliminary checks. Our design runs at 160 MHz. I have verified, that external oscillator has locked. Using clock forwarding I have verified, that 160 MHz is available at c3_clk0, which is user clock output of MCB's PLL.

    Please advise.

    Thanks in advance.

    DB:2.53:How To Debug Claibration Problem? fm

    We attached a button to make reset signal to memory stuff. By monitoring signals on test points we found, that PLL locks reliably, while calibration does not complete. Pointless clicking on reset button made MCB to calibrate once. Then it was able to pass calibration in one of approx. ten cases. Applying wet finger success rate was increased. So I conclude, that trouble related with board layout. Very little could be done in software.

  • RELEVANCY SCORE 2.51

    DB:2.51:Elfcheck Failed z3



    I have an EDK project on the SP601 dev board. The project involves a MicroBlaze processor, and it works fine when I program the FPGA in SDK with a bootloop, then load up the code. I want the board to function stand-alone, so I want to generate a bitstream that I can program into the BPI flash. I'm using ISE/EDK/SDK 13.4.

    The code won't fit in the BRAM (I've set the BRAM size to 32k, the largest possible on the SP601). So I need to load code into the DDR2 RAM. I use the "Generate Linker Script" tool to make a script that puts the code and data sections into DDR2. But when I try to generate the bitstream I get:

    ERROR:EDK:3165 - elfcheck failed!The following sections did not fit into Processor BRAM memory: Section .jcr (0x88000944 - 0x88000947) Section .eh_frame (0x88000940 - 0x88000943) Section .data (0x88000830 - 0x8800093F) Section .rodata (0x88000814 - 0x88000829) Section .dtors (0x8800080C - 0x88000813) Section .ctors (0x88000804 - 0x8800080B) Section .fini (0x880007E8 - 0x88000803) Section .init (0x880007B4 - 0x880007E7) Section .text (0x88000000 - 0x880007B3)

    Try using the linker script generation tools to generate an ELF that mapscorrectly to your hardware design.

    I've seen a lot of questions on this forum describing similar problems, but no real answers. The FPGA must be up and running before the DDR2 can be loaded, I get that, but is there not some hidden magic that does that?

    Thanks for any help

    Rick







    Solved!
    Go to Solution.

    DB:2.51:Elfcheck Failed z3


    Hi,

    Here's what I do:

    In SDK (13.4) I go to XilinxTools-ProgramFPGA. I select the .bit and .bmm files, and the .elf file of my application. The result is the error message copied above.

    What I was hoping would happen is that a bitstream would be generated from which I could then generate an mcs file to load into BPI Flash, so that the board would boot up with my application at power on. That's what I do with an application that fits into BRAM. But this one doesn't fit into BRAM.

    I realize now, I think, that what Doug says above is correct. I think I need to use the ProgramFlash option to turn the elf into an SREC file, then load the SREC into the flash, then use the Files-New C Application-SREC Bootloader to generate a bootloader application. Then the bootloader.bit file can be turned into an mcs and loaded into the flash at 0x000000, and can point to the application SREC....

    Seems awfully complicated, and it seems like a pretty common need, so I thought it would all just magically happen behind the scenes. But I guess not. Can you confirm that, and maybe offer some guidance?

    Thanks,

    Rick

  • RELEVANCY SCORE 2.51

    DB:2.51:[Solved] Pacman Hangs At Database Sycnrhonization x9



    Hello, all! I recently did a fresh installation of Arch, and all things went fairly smoothly (Im on KDE right now ), but for some reason pacman no longer works. It hangs on the database sychronization.

    Here is the output of pacman -Syu --debug:
    debug: config: attempting to read file /etc/pacman.conf
    debug: config: new section options
    debug: config: HoldPkg: pacman
    debug: config: HoldPkg: glibc
    debug: config: SyncFirst: pacman
    debug: config: Architecture: i686
    debug: config: new section core
    debug: registering sync database core
    debug: config file /etc/pacman.conf, line 64: including /etc/pacman.d/mirrorlist
    debug: config: attempting to read file /etc/pacman.d/mirrorlist
    debug: adding new server URL to database core: ftp://mirror.rit.edu/archlinux/core/os/i686
    debug: adding new server URL to database core: http://mirror.yellowfiber.net/archlinux/core/os/i686
    debug: setlibpaths() called
    debug: option cachedir = /var/cache/pacman/pkg/
    debug: config: finished parsing /etc/pacman.d/mirrorlist
    debug: adding new server URL to database core: http://mirror.yellowfiber.net/archlinux/core/os/i686
    debug: config: new section extra
    debug: registering sync database extra
    debug: config file /etc/pacman.conf, line 68: including /etc/pacman.d/mirrorlist
    debug: config: attempting to read file /etc/pacman.d/mirrorlist
    debug: adding new server URL to database extra: ftp://mirror.rit.edu/archlinux/extra/os/i686
    debug: adding new server URL to database extra: http://mirror.yellowfiber.net/archlinux/extra/os/i686
    debug: config: finished parsing /etc/pacman.d/mirrorlist
    debug: adding new server URL to database extra: http://mirror.yellowfiber.net/archlinux/extra/os/i686
    debug: config: new section community
    debug: registering sync database community
    debug: config file /etc/pacman.conf, line 75: including /etc/pacman.d/mirrorlist
    debug: config: attempting to read file /etc/pacman.d/mirrorlist
    debug: adding new server URL to database community: ftp://mirror.rit.edu/archlinux/community/os/i686
    debug: adding new server URL to database community: http://mirror.yellowfiber.net/archlinux/community/os/i686
    debug: config: finished parsing /etc/pacman.d/mirrorlist
    debug: adding new server URL to database community: http://mirror.yellowfiber.net/archlinux/community/os/i686
    debug: config: finished parsing /etc/pacman.conf
    debug: registering local database
    :: Synchronizing package databases...
    debug: destfile found, using mtime only
    debug: using core.db.tar.gz for download progress
    debug: HTTP_PROXY: (null)
    debug: http_proxy: (null)
    debug: FTP_PROXY: (null)
    debug: ftp_proxy: (null)
    ^Cerror: failed retrieving file core.db.tar.gz from mirror.rit.edu : Interrupted system call

    Interrupt signal received
    debug: returning error 25 from alpm_trans_interrupt : operation not compatible with the transaction type

    debug: unregistering database local
    debug: unregistering database core
    debug: unregistering database extra
    debug: unregistering database community

  • RELEVANCY SCORE 2.51

    DB:2.51:Spi Flash Programming Failed z7



    Hello,

    I am using a SPARTAN-3A(VQ100) FPGA and trying to program SPI Serial NOR flash(N25Q(128Mb)) using indirect SPI programming.

    Progamming is failing and error is shown below

    '1': ID Check passed. '1': ID Check passed. '1': Erasing Device.'1': Using Sector Erase.'1': Programming Flash.'1': Reading device contents...

    Failed at address, 0'1': Verification TerminatedINFO:iMPACT - '1': Flash was not programmed successfully.

    But it is working fine if i connect my memory(N25Q) to J12 Header of SP601 EVALUTION Board(By removing the J15 Header).

    Please give me the solution for this as i want use this IC in another design.

    Regards

    Anil Sutej










    Attachments:







    Prom_test_board_nov8th_01.pdf ‏53 KB

    DB:2.51:Spi Flash Programming Failed z7

    what is the ISE version you are using at your end . We have known issue with earlier version.. To resolve this issue, use iMPACT 13.4 or older versions to program M25P16 SPIs while running Indirect Programming via Spartan-3E/-3A devices.



    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 2.51

    DB:2.51:Clocking Wizard For Sp601 f3



    Hi there!

    I have just acquired a Xilinx SP601 Eval board and have received the ISE software ver. 11.3 with the same. I am going through the In-depth tutorial of the ISE but am stuck at one point. In the 'Creating a DCM Module' section, I need to use the Clocking wizard. In that when I select FPGA Features and Design Clocking, I cannot find the clocking option for the Spartan 6 board in the software.

    Could someone help me as to what values are needed to be changes so that I can use this module on my Spartan 6 board. Can I directly use the FPGA Features and Design Clocking Clocking Wizard. ?? If so, what values do I need to change?

    Regards,

    Jack







    Solved!
    Go to Solution.

    DB:2.51:Clocking Wizard For Sp601 f3


    Are you using an oscilloscope to probe your signal?

    If you want to measure a 100MHz digital signal with a 'scope, the scope and probes should be rated for at least 350MHz bandidth. A 1GHz scope will give you more accurate measurements than a 350MHz scope, but 350MHz should be (barely) adequate.

    A 100MHz scope (and probes) is entirely inadequate for measuring or displaying amplitude, risetime, shape (e.g. ringing or reflections) or duty cycle of a 100MHz digital signal.

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.51

    DB:2.51:Need Some Help For Sp601 Microblaze + Lwip d8



    Hello everyone!

    I am a microblaze and lwip beginner ,and I really really want to learn those quickly, I have read xapp1026 and some articles in forum.But there are still some problems.

    Here is a simple discription for my design:

    I use ISE12.3 and Lwip's version is 1.3.0 , Xilinx adapter is v3.00a, iperf is v1.7.0.My PC's netcard is a 10/100M adapter.

    My design is to establish a UDP stack(don't need TCP) in microblaze with lwip's raw mode on my SP601 board.I need to microblaze to do two things : firstly ,receive a udp unicast or multicast packet to configure another module in FPGA ( the speed is very low ) ;on the other hand, send bigger packets to PC or routers( speed need to be 10Mbps at least , I think it can be realize on SP601 ).

    My problem are listed below:

    1.After I past the udp echo test. I've rewrote the xapp1026's utxperf( the original version is made to ISE10.1 ),but test result of bandwidth I get is 2.02Mbits/sec ,Jitter is about 5.5ms.

    I think maybe the reason is somewhat interrupt happens periodically and blocked every 5.5ms. But I don't know how that happens.Maybe my code is wrong.

    I have enlarged the mem_size,memp_n_udp_pcb in lwip_memory_option table.But as I seen ,it just enlarge the .elf file other than get a better performance.

    2.When I built my udp echo test apps in XPS , the generated .elf file is about 300KB( so big!!! I can't download it in the bram ).And then I try to put this .elf file to SP601's BPI Flash( SPI Flash was damaged ), so I follow the xtp041's example to make a bootloader. But it didn't work.

    Now I just can run my design in SDK's debug mode.First download the bitstream,it will note that FPGA configuration encounter error ,but when I click download the bitstream again ,it works( Maybe SDK runs bootloader automatically ).Then I can debug my design.

    Can someone help me to store the elf app to FLASH , and run bootloader to read it from FLASH to DDR?

    3.I can't use xps_ll_temac_v2 module. My license of xps_ll_temac_v2 is expired in 2011-5-27.I have searched in the google , someone said SP601 cannot use xps_ll_temac. Is that true?

    I really need your help .Any idea is important to me.

    Thanks for you reading my words.

    Best wishes!

    DB:2.51:Need Some Help For Sp601 Microblaze + Lwip d8


    Hello!

    I am working with digilent Nexys3 board( Spartan6 FPGA) and I need to implement simple UDP/IP connection for streaming some data to PC. I created Microblaze controller with Xilinx XPS, and I am trying to use code from xilinx app1026 project. Basically I am trying to take out just UDP/IP part. It's not working and sometimes I get error about undefined functions and sometimes about .elf file exceeding the memory. I am so confused.

    Can I have working code from xilinx app1026 only with microblaze and ethernet IP or I need to have external RAM memory? If you have some examples I would appreciate it very much.

    Thank you.

    Best regards.

  • RELEVANCY SCORE 2.50

    DB:2.50:Debug Assertion Failed 8a


    Can this error be fixed with a download?

    DB:2.50:Debug Assertion Failed 8a

    What are you doing when you get this error message?

    MS-MVP - Elephant Boy Computers - Don't Panic!

  • RELEVANCY SCORE 2.50

    DB:2.50:Platform Usb Cable On Sp601 9j



    I am trying to use the jtag interface on sp601.

    I have platform cablue USB and i have connected the flying leads to the SPI Prog Header on the sp601.

    I am using ISE 12.1.

    When i try to use impact to start downloading it gives me this error.

    Attempting to identify devices in the boundary-scan chain configuration...INFO:iMPACT - Current time: Mon Jun 20 13:34:49 2011// *** BATCH CMD : Identify -inferir PROGRESS_START - Starting Operation.Identifying chain contents...done.ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.PROGRESS_END - End Operation.

    I have checked the connections, the status led on the platform usb cable is green.

    Is platform cable usb compatible with sp601 board fpga or do i need a newer version like platform cable usb II?

    Would appreciate if some one can help.

    DB:2.50:Platform Usb Cable On Sp601 9j

    I could program FPGA via integrated USB JTAG interface (J10).

    This should also allow you to program the flash memory on the board, using IMPACT.

    But, is it possible to connect standard JTAG cable (such as classic parallel JTAG cable) to SP601?

    Just check the fine schematics. If it's there, it should be easy for you to find.

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.48

    DB:2.48:Sp601 Board 9s



    Hi,

    We are purchasing SP601 spartan-6 evaulation kit and designing FMC based add-on card. Whereas, this card will consists of components such as, DAC, Amplifier, IO switches and LEDs.

    Can I able to use the 3.3V supply in FMC connector to provide the power to DAC, AMP and other components in add-on board or should I have to have the seperate power section to provide the supply to these components?




    FPGA freak

    DB:2.48:Sp601 Board 9s


    The FMC interface on SP601 (and SP605 and ML605) uses a VADJ of 2.5V for the IO levels between the carrier card (SP601) and the FMC module.

    The SP601 (and SP605 and ML605) also provides 3.3V and 12.0V to the FMC module per the FMC specification and these can be used to power components as necessary.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.48

    DB:2.48:Sp601 Does Not Start pk



    Hello,

    I experiment a problem with SP601 development kit.

    When I switch it on, the LEDs INIT, DS15 and DS1 are flashing and the board is not recognize by my computer.

    I checked the power supplies goes down to 1.6 V and oscillate at a frequency of 3.6 Hz.

    I attached a jpg screenshot of the +5Vwaveform.

    I absolutely don't know what caused this behavior.

    Thank you in advance for any feedback. And don't hesitate to ask questions if you need more information.

    Olivier Goudard










    Attachments:




    DB:2.48:Sp601 Does Not Start pk

    Thank you for the help.I already open a webcase at AVNET because the board was bought there on 11/27/2012. I no news at the moment.I have to call them to know about the warranty they offer.Best regards and thanks again.o

  • RELEVANCY SCORE 2.48

    DB:2.48:Sp601 Starter Kit Edk/Sdk Programming k1



    I'm current have a SP601 starter kit board and want to run SP601 BIST Flash Application(documentation: XTP041 and file: rdf0045.zip). I was able to load the system file in XPS and export it to SDK. I went through the tutorials and was able to see an output of hello worl on the hypertermail. I want to know if anyone could give advice as to how I add the files that are provided within the zip folder rdf0045.zip to a current software plateform. Currently I've tried addding them by selecting export, however not all of the files are linked and located with errors appearing.

    Any help would be appreciated.

    DB:2.48:Sp601 Starter Kit Edk/Sdk Programming k1


    I'm current have a SP601 starter kit board and want to run SP601 BIST Flash Application(documentation: XTP041 and file: rdf0045.zip). I was able to load the system file in XPS and export it to SDK. I went through the tutorials and was able to see an output of hello worl on the hypertermail. I want to know if anyone could give advice as to how I add the files that are provided within the zip folder rdf0045.zip to a current software plateform. Currently I've tried addding them by selecting export, however not all of the files are linked and located with errors appearing.

    Any help would be appreciated.

  • RELEVANCY SCORE 2.48

    DB:2.48:Labview For Arm Swd Communication Failure sc



    Hi everyone,

    I just got my Labview for ARM cortex M3evaluation kit and I can't download a simple program to the target. I'm using the KeilULink 2 programmer and I get this error when compiling/downloading:

    [4:23:16 PM] Status: Error

    SWD Communication Failure

    Error: Flash Download failed - Target DLL has been cancelledDetail: [UVSC_PRJ_FLASH_DOWNLOAD, MSG: 0X100A, STATUS: Ex.] (1)

    Status: FLASH download error.

    I have read about this error and NI simply refers to Ulink2 user's guide which has this description for this error:

    Serial Wire Debug communication is corrupted. The target SWD interface is not working properly. Mainly caused by the target: debug block not powered or clocked properly. Avoid Deep-Sleep modes while debugging. Lower the Max Clock frequency in the ULINK USB-JTAG/SWD Adapter section.

    I have tried to "Lower the Max Clock frequency in the ULINK USB-JTAG/SWD Adapter section" but it didn't resolve the problem.

    I have also tried to download the program using the usb port on the dev board but instead I get this error:

    [4:51:22 PM] Status: ErrorUnexpected error occurred.[Source: Target is in debug modeDetail: [UVSC_PRJ_ADD_GROUP, MSG: 0x1002,

    STATUS: 0xA] Code: 10]

    What am I supposed to do with that?? I'm wondering if the dev board is defective. And this was supposed to be plug and play...

    Any help is greatly appreciated!

    DB:2.48:Labview For Arm Swd Communication Failure sc


    I have uninstalled Labview 2011 and uvision 4 and then reinstalled it and now it seems to be working fine...

    Thanks for your support guys!

  • RELEVANCY SCORE 2.48

    DB:2.48:Sp601 - Help Interfacing A Ps/2 Keyboard 9j



    I wish to experiment with a keyboard and mouseby attaching a PS/2 interface to the GPIO header on my SP601. Since the PS/2 interface is LVTTL would the built-in GPIO 200 ohm series resistors be enough? Also, since the keyboard I'm planning to attach is open collector I would assume I need to pullup these pins?So from my understanding is it sufficient to do this?

    UCF constraints for SP601 board:

    NET "PS2_DATA1" LOC="N17" | IOSTANDARD = LVCMOS33 | PULLUP; ## GPIO_HDR0

    NET "PS2_CLK1" LOC="M18" | IOSTANDARD = LVCMOS33 | PULLUP; ## GPIO_HDR1

    NET "PS2_DATA2" LOC="A3" | IOSTANDARD = LVCMOS33 | PULLUP; ## GPIO_HDR2

    NET "PS2_CLK2" LOC="L15" | IOSTANDARD = LVCMOS33 | PULLUP; ## GPIO_HDR3

    I'm a hobbyist new to hardware design and prefer not to fry my new board.







    Solved!
    Go to Solution.

    DB:2.48:Sp601 - Help Interfacing A Ps/2 Keyboard 9j


    Thank you for the advice. The keyboard in question is quite old so I'm going to assume 5V TTL thus buffering with the Schmitt trigger is the best choice.

  • RELEVANCY SCORE 2.48

    DB:2.48:Impact Issue With Kc705 c1



    Hi,

    I have designed a program with ISE14.7 and download it to the KC705 board via iMPACT succefully, but when I connected the XM105 Debug Card to the FMC connector on the KC705got an errormessage with "Program failed" in red:

    INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111110INFO:iMPACT:1579 - '1': Expected IDCODE: 00000011011001010001000010010011

    any help?

    thanks







    Solved!
    Go to Solution.

    DB:2.48:Impact Issue With Kc705 c1


    thank you for the reply, the problem has been resolved :)

  • RELEVANCY SCORE 2.48

    DB:2.48:Load Instruction Code From Ddr2 On Sp601 Board a9


    I am using a sp601 board but my program code doesn´t fit anymore on the chip, So i want to use ddr2 ram to debug my code.

    But i cant get it running.

    Can someone tell me excactly how i can set up my project so i can use ddr2 for my instructions and that i can write it to this module with the mdm

    Greetings

    Art







    Solved!
    Go to Solution.

    DB:2.48:Load Instruction Code From Ddr2 On Sp601 Board a9


    I solved it,

    Started a new project in the 12.1 environment and there xilinx connects the ddr2 module correctly to the project.

    tested it with a little hello word app.

  • RELEVANCY SCORE 2.48

    DB:2.48:Sp601 Mig Reference Design On Ise 12.2 x9



    I am attempting to use the SP601 MIG reference design (RDF0005) by following the directions in XTP039. The reference design includes both a ready-to-download bitstream and a ready-to-build design.

    When I use ChipScope to download the pre-built bitstream, everything is fine. The design operates as described, the error LED doesn't illuminate.

    When I run ise_flow.bat for the (unmodified) ready-to-build design and download it with ChipScope, the design doesn't work as it should. The error LED _usually_ (but not always!) illuminates. When I look at the design in ChipScope, the read data doesn't match the expected data. The read data is usually all F's, although occasionally it will just be garbage. The rd_error and wr_error are never asserted, so as far as I can tell, the MCB thinks it's writing and reading correctly. Occasionally (maybe 5% of the time) the calib_done LED won't illuminate. Since the pre-built works, I know the DDR2 and board are working.

    The reference design was produced using ISE 12.1 (MIG 3.4). I'm attempting to build it using ISE 12.2 System Edition. Could this cause a problem?Does Xilinx ever update the reference designs? I will open a webcase if that's the more appropriate support route, but I thought I'd try here first.

    Thanks,

    Carson







    Solved!
    Go to Solution.

    DB:2.48:Sp601 Mig Reference Design On Ise 12.2 x9


    Thanks, I appreciate the help. I had somehow downloaded the 12.1 reference design documents and just assumed that those were the only ones available. Using the reference designs that correspond to my version of ISE fixed the problem.

  • RELEVANCY SCORE 2.47

    DB:2.47:Problem Loading Msc8156ads Board With Cw 10.2.9 k9



    Im getting follwing error while i am trying to load a application in MSC8156ADs board using cw 10.2.9

    Failed to resume target process., CCSProtocolPlugin : Could not connect to the probe (or other debug link)

    The same application is loading without any error when i tried with cw 10.1.1

    whether there is any settings that is to be changed in debug configurations while loading with cw 10.2.9

    DB:2.47:Problem Loading Msc8156ads Board With Cw 10.2.9 k9


    Hi,

    Now its working fine. Thanks a lot for your timely help.

    --

    Best Regards

    Hema H

  • RELEVANCY SCORE 2.46

    DB:2.46:Sp601 Boot Problem a1



    I have a microblaze design which runs on the SP601 development board. I have several of these boards and the design runs on all boards when I program the FPGA with a bootloop and then start my executable. I want the boards to be self-booting, so I built an srec_bootloader design to load the code from BPI PROM following the scheme in AR47909. This works on some of the boards but not all. However, on those boards which do not boot, if I press the CPU RESET button after power up, they start operating. So for some reason the CPU is not starting on these boards, though the FPGA is successfully programmed and the executable is where it should be.

    Any help greatly appreciated

    Rick

    DB:2.46:Sp601 Boot Problem a1


    I wonder if I can get some more attention from Xilinx on this? I see that I can no longer raise a Webcase....

    I have 15 of these boards (SP6010). With the same flash file, some boards boot up almost all the time; some boards never.

    I put a chipscope IBA core in the design and I can see, when the FPGA does not boot successfully, that it goes off the rails while executing code in the DDR2 RAM block (128MB starting at 0x8800_0000). I see the code executing along in an 8800xxxx region, then it jumps to 87ffxxxxx, a region which is empty. This jump happens at different points, seemingly randomly.

    Pretty mysterious, and I'm out of ideas.

    Rick

  • RELEVANCY SCORE 2.45

    DB:2.45:Uart Core For The Sp601 x7



    Does anyone know of a fairly simple UART core which can be implemented on the SP601?

    I've come upon XAPP223, but it says it's only optimized for the Spartan II, although I have seen in used on the Papillio board which is Spartan 3. Would I be able to use this core on the Spartan 6?

    Cheers,

    Andrei

    DB:2.45:Uart Core For The Sp601 x7


    UARTs are a first semester design exercise for first-year logic design students. UARTs may be found in 1000s of sites on the world wide web. If you are a student, you will learn quite a bit by designing (and debugging) your own implementation.

    From the New Users Forum README thread:

    Common Interfaces and FPGA techniques:

    I2C basics link#1 link#2 code examples wiki articles: I2C SMBus MDIO SPD EDID

    SPI (serial peripheral interface) basics Wiki article fpga4fun tutorial the 'other' SPI

    serial/UART wiki async serial article wiki RS-232 article wiki ASCII codes article find code

    -- Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.45

    DB:2.45:Default Test_Peripheral Example Fails 7j



    Hi all,

    I´m starting with Microblaze, and I´ve just found the first problems. I´m working with a SP601 board and I wanted to download the "test_peripheral" example that is available in the SDK. However, when the project is generated and compiled, and error ocurrers:

    "region ilmb_cntlr_dlmb_cntlr is full"

    "section .init [address range] overlaps section text"

    ....similar ones

    "section .rodata lma 0x90 overlaps previous sections"

    I´ve been having a look in the forum and in many threads people suggest to regenerate the linker script. I´ve done it, but with no success. I´m wondering why this is happening since it is the source autogenerated by the SDK. With other examples (HelloWorld, and so) it works fine..

    Can someone give me a clue?

    Thanks a lot

    DB:2.45:Default Test_Peripheral Example Fails 7j


    Hi all,

    Thank you very much for your answer. All of you are rigth and the problem was related to the memory size. Now, after having resized the memory, it works fine

    Thanks again!

  • RELEVANCY SCORE 2.45

    DB:2.45:Programming d1



    Hi, I am trying to debug my program and download it onto my board for Freescale Cup Car. However when I attempt this i get an error message (shown in the screenshot). My board is attached to the battery and connected to the computer correctly as my computer is recognising the board. Anyone know how i fix this ? Thanks

    DB:2.45:Programming d1


    Hello,

    Thank you for your post, however please consider moving it to the right community place (e.g. CodeWarrior Development Tools or University Programs) to get it visible for active members.

    For details please see general advice Where to post a Discussion?

    Thank you for using Freescale Community.

  • RELEVANCY SCORE 2.45

    DB:2.45:[Solved]Built Pacman In Debian, Getting Error Invoking External Downl 98



    Hi, Ive built pacman in Debian and now whenever I try to run any pacman command involving repositories, I get error invoking external downloader. Ive configured repositories, but I feel like the problem is with libfetch. I could only build libdownload which is a fork of libfetch.

    Here is the output of pacman -Syv --verbose:
    debug: config: attempting to read file /usr/local/etc/pacman.conf
    debug: config: new section options
    debug: config: HoldPkg: pacman
    debug: config: HoldPkg: glibc
    debug: config: SyncFirst: pacman
    debug: config: Architecture: i686
    debug: config: new section main
    debug: registering sync database main
    debug: adding new server URL to database main: http://cake.lib.fit.edu/archlinux/main/os/i686
    debug: setlibpaths() called
    debug: option cachedir = /usr/local/var/cache/pacman/pkg/
    debug: config: finished parsing /usr/local/etc/pacman.conf
    Root : /
    Conf File : /usr/local/etc/pacman.conf
    DB Path : /usr/local/var/lib/pacman/
    Cache Dirs: /usr/local/var/cache/pacman/pkg/
    Lock File : /usr/local/var/lib/pacman/db.lck
    Log File : /usr/local/var/log/pacman.log
    Targets : None
    :: Synchronizing package databases...
    debug: database path for tree local set to /usr/local/var/lib/pacman/local/
    debug: local database version 2
    debug: returning error 47 from download : error invoking external downloader
    debug: failed to sync db: error invoking external downloader
    error: failed to update main (error invoking external downloader)
    error: failed to synchronize any databases
    debug: unregistering database local
    debug: unregistering database main

  • RELEVANCY SCORE 2.44

    DB:2.44:Function Of Cpu Reset Pin ma



    hello all,

    i have spartan 6 (lx16csg324) fpga with sp601 board...i want to know what is the function of IO_LO1P_3_N4 cpu reset pin in bank3...??

    thanks

    DB:2.44:Function Of Cpu Reset Pin ma


    hello all,

    i have spartan 6 (lx16csg324) fpga with sp601 board...i want to know what is the function of IO_LO1P_3_N4 cpu reset pin in bank3...??

    thanks

  • RELEVANCY SCORE 2.44

    DB:2.44:Debuging Win Ce 5.0 With Evc 4 On Custom Board za


    I'm using eVC++ 4 SP4 to build a Win32 application on Windows CE 5. I made an OS image with Platform Builder 5 and got it running on my evaluation board (Atmel AT91SAM9261 processor). When I try to debug my application, I get an error message : Platform Manager failed to queue CEMON package for download. 72B8A756 44C1A6A6 43305494 F484AF8D.I can execute the app without problems, just can't debug. I searched this forum and read the eVC++ 4 does not support Windows Mobile 5 for debugging, but I'm not sure if this applies to Win CE 5? Did anybody manage to get debugging working in this combination (Win CE + eVC++ 4)?

    DB:2.44:Debuging Win Ce 5.0 With Evc 4 On Custom Board za

    I'm using eVC++ 4 SP4 to build a Win32 application on Windows CE 5. I made an OS image with Platform Builder 5 and got it running on my evaluation board (Atmel AT91SAM9261 processor). When I try to debug my application, I get an error message : Platform Manager failed to queue CEMON package for download. 72B8A756 44C1A6A6 43305494 F484AF8D.I can execute the app without problems, just can't debug. I searched this forum and read the eVC++ 4 does not support Windows Mobile 5 for debugging, but I'm not sure if this applies to Win CE 5? Did anybody manage to get debugging working in this combination (Win CE + eVC++ 4)?

  • RELEVANCY SCORE 2.44

    DB:2.44:Usbdm Arm Transaction Fault? c1



    I am trying to use USBDM to debug a custom board.

    The board uses the MKL25Z128 processor, the same as on the FRDM-KL25Z board, however it is in the smaller 48 pin QFN package.

    I've been able to go thought the debugging examples with USBDM on the FRDM board via KDS with no issues..

    Alas when I try to use the FRDM board to debug the custom board I get "GDB Handler initialization failed, reason: ARM transaction Fault".

    I can use the FDRM board to program the custom board flash with no issues so I feel the hardware is all talking okay?

    Can someone point me in a direction to over come this transaction error please?

    DB:2.44:Usbdm Arm Transaction Fault? c1


    I am trying to use USBDM to debug a custom board.

    The board uses the MKL25Z128 processor, the same as on the FRDM-KL25Z board, however it is in the smaller 48 pin QFN package.

    I've been able to go thought the debugging examples with USBDM on the FRDM board via KDS with no issues..

    Alas when I try to use the FRDM board to debug the custom board I get "GDB Handler initialization failed, reason: ARM transaction Fault".

    I can use the FDRM board to program the custom board flash with no issues so I feel the hardware is all talking okay?

    Can someone point me in a direction to over come this transaction error please?

  • RELEVANCY SCORE 2.44

    DB:2.44:Jtag Download On Sp601 3z



    Hi,

    Does anybody use the JTag Download on a Spartan6? If so can you be so kind and share the JTAG_Loader_ROM_form.vhd including the BSCAN_SPARTAN6 instantiation?

    I tried to modify the VIRTEX2/5 versions I found but a little confused since I don't know what to do with the TCK and TSM ports in the BSCAN_SPARTAN6.

    Thanks for any help or suggestions!

    Thomas







    Solved!
    Go to Solution.

    DB:2.44:Jtag Download On Sp601 3z


    Ok, dump question. Those are outputs and can be safely ignored for this purpose.

    Thomas

  • RELEVANCY SCORE 2.44

    DB:2.44:Download Problem With Sp601 Designs k3


    Hello,eveyone.

    I have got a sp601 kit., installed ise11.3 and CP210x USB to UART Bridge driver (installed on line).

    Lunckly ,follow the 《Getting Started with the Diagnostic FLASH Demo》 user guide ,I have passed all the Diagnostic Tests in the demo. and runned the Base System Reference design successfully.

    But ,i can't download my bit file to the FPGA. the detail is :

    As the tool has not support spartan 6 design in BSB.

    SO ,I created a simple BSB design with virtex 4 (the design just include one uart peripheral ), and then changed the hardware properties to "sptarten lx-16, 324 ,-2,", also changed the MHS and corresponding MSS, added ucf.

    Finally,This design generate a bit file successfully. i download this bit file with impact tool in ise 11.3, but ,no print information printed to my HyperTerminal,however ,the software application is just the memory test or peripheral test applications auto generated by the bsb.

    I generated a bit file with "uart test" software application in reference design "SP601 Standalone Applications --rdf 0015 .. but no information printed on Hyper Terminal neither.

    my Terminal Port Settings as follows:

    baud rate : 9600, Data bits : 8, Parity: None, Stop bits : 1, and Flow control: None.

    and the Diagnostic Demo design (BIST) can print information correctly.So i think the uart can work ,

    But why my bit file has no print ? neither did the bit file generated by SP601 Standalone applications provieded by XILINX ?

    Is there any problem with the download process ?

    Sincerely looking forward to your help.

    Thanks for your help.







    Solved!
    Go to Solution.

    DB:2.44:Download Problem With Sp601 Designs k3


    Hi xiaochh

    can u tell me how u have runned the Base System Reference design successfully as i am getting problem my jtag is not recognised and when i connected the ethernet and on setup/ network interface when i select only one option as it comes is broadcom netxtreme ethernet gigapet then it says on status that fpga not connected. i also could not open the MCS file given on the usb of xilinx. pls help...

  • RELEVANCY SCORE 2.44

    DB:2.44:Debug Is Not Started After Platform Builder Downloading, - Oemkitlinit Failed - Trying Again. 1m


    Hi
    After power-cycle my device and attach to the device, platform begins to download the image. It works fine.

    After the download, the debug should begin automatically, sometimes it's as expected, but sometimes the debug never begins. the error message is

    OEMKitlInit failed - trying again.

    I tried kitl mode poll or interrupt, no big difference.

    DB:2.44:Debug Is Not Started After Platform Builder Downloading, - Oemkitlinit Failed - Trying Again. 1m

    Thanks for the response Vinoth.
    It is working well. However, the local boot needs KITL to be disabled in order to proceed. And EBOOT needs KITL to be enabled if we need debugging.

  • RELEVANCY SCORE 2.43

    DB:2.43:Failed To Read One Or More Register Values (Busy) mc



    hi

    setup:

    board-k20d72m

    s/w - IAR embedded wokbenchV6.5.

    need to communicate with TWRK20D72M via USB,

    I am using k20 board , i need to download CAN code to the board. upon running the code got the following information in log

    Fri Jul 25, 2014 12:21:09: Windows NT detected.

    Fri Jul 25, 2014 12:24:43: PE Interface detected - Flash Version 31.21

    Fri Jul 25, 2014 12:24:46: Device is KINETIS.

    Fri Jul 25, 2014 12:24:46: Mode is In-Circuit Debug.

    Fri Jul 25, 2014 12:24:48: CPU reset by debugger.

    Fri Jul 25, 2014 12:24:48:

    Fri Jul 25, 2014 12:24:48: Software reset was performed

    Fri Jul 25, 2014 12:24:49: 12612 bytes downloaded (8.58 Kbytes/sec)

    Fri Jul 25, 2014 12:24:49: Loaded debugee: C:\Freescale\Freescale_MQX_4_1\mqx\examples\can\flexcan\build\iar\flexcan_twrk20d72m\Debug\Exe\c.out

    Fri Jul 25, 2014 12:24:51: CPU reset by debugger.

    Fri Jul 25, 2014 12:24:51: Software reset was performed

    Fri Jul 25, 2014 12:24:51: Target reset

    Fri Jul 25, 2014 12:24:51: Failed to read one or more register values (busy).

    last log states that failed to read one or more registry values

    can you please help me to solve this issue

    thanks in advance

    DB:2.43:Failed To Read One Or More Register Values (Busy) mc


    hi

    setup:

    board-k20d72m

    s/w - IAR embedded wokbenchV6.5.

    need to communicate with TWRK20D72M via USB,

    I am using k20 board , i need to download CAN code to the board. upon running the code got the following information in log

    Fri Jul 25, 2014 12:21:09: Windows NT detected.

    Fri Jul 25, 2014 12:24:43: PE Interface detected - Flash Version 31.21

    Fri Jul 25, 2014 12:24:46: Device is KINETIS.

    Fri Jul 25, 2014 12:24:46: Mode is In-Circuit Debug.

    Fri Jul 25, 2014 12:24:48: CPU reset by debugger.

    Fri Jul 25, 2014 12:24:48:

    Fri Jul 25, 2014 12:24:48: Software reset was performed

    Fri Jul 25, 2014 12:24:49: 12612 bytes downloaded (8.58 Kbytes/sec)

    Fri Jul 25, 2014 12:24:49: Loaded debugee: C:\Freescale\Freescale_MQX_4_1\mqx\examples\can\flexcan\build\iar\flexcan_twrk20d72m\Debug\Exe\c.out

    Fri Jul 25, 2014 12:24:51: CPU reset by debugger.

    Fri Jul 25, 2014 12:24:51: Software reset was performed

    Fri Jul 25, 2014 12:24:51: Target reset

    Fri Jul 25, 2014 12:24:51: Failed to read one or more register values (busy).

    last log states that failed to read one or more registry values

    can you please help me to solve this issue

    thanks in advance

  • RELEVANCY SCORE 2.42

    DB:2.42:1 Us Clk Desired Using 27mhz Clk Signal Using Sp601 Board df



    I'm currently using the new SP601 starter kit board with a 27mhz clk signal. I'm using the following code to implement a 1us clock signal, however when tested with an o-scope the output is about 1 second. Does anyone have an suggestions? (I have also used this same logic using the Spartan 3E 50mhz clock and divided by 49 which worked perfectly)

    one_micro_second_logic: process(clk_27mhz) begin if clk_27mhz'event and clk_27mhz='1' then

    if one_micro_second_count=26 then --divide by 26 is 1us one_micro_second_count = 0; one_micro_second_pulse = '1'; clk_test = '1'; else one_micro_second_count = one_micro_second_count + 1; one_micro_second_pulse = '0'; clk_test = '0'; end if;end if; end process one_micro_second_logic;

    ucf file:

    NET "clk_27mhz" PERIOD = 20.0ns HIGH 50%;

    NET "clk_27mhz" LOC = "V10" | IOSTANDARD = LVTTL;

    DB:2.42:1 Us Clk Desired Using 27mhz Clk Signal Using Sp601 Board df


    Hi,

    I have seen the clip and also your picture, but everything looks quite stable to me.

    Just two things that make me wonder:

    1.) The peak voltage is below 0.3V? Is that intended, a display artifact or how can it be explained?

    2.) On the lower right side you can see the trigger level, I think. It's 0.00V so every little spike can cause a retrigger, and this may look like some pulse is missing.

    Another way to check the correctness of your output signal is using a pulse/frequency counter.

    There you should have a stable display of 1MHz (or 1 mega pulses per second) and if some pulses are missing you will see a deviation of that value.

    Have a nice synthesis

    Eilert

  • RELEVANCY SCORE 2.42

    DB:2.42:Sp601 And Interconnect Types c8



    I'm a FPGA newbie and trying to get started using the "Test Drive" described in the "EDK Concepts, Tools, and Techniques" document.

    I have a SPARTAN-6 SP601.

    My first time through the Test Drive, when I got to the "Crew New XPS Project using BSB Wizard" dialog and I had to specify an Interconnect Type, I chose "PLB System" because it specifies the SP601. However, the Generate Bitstream step later failed with the error "EDK:4133 - IPNAME:plb_v46, INSTANCE:plb_v46_0 - must have atleast 1 slave".

    So I'm wondering whether I could/should have specified AXI as the interconnect type. Is this the case, or should PLB also work? If PLB, what could have caused my error? I did quite a bit of searching on the error but could not pinpoint the cause or how to fix it.

    Advance thanks

    ted in AZ

    DB:2.42:Sp601 And Interconnect Types c8


    "EDK:4133 - IPNAME:plb_v46, INSTANCE:plb_v46_0 - must have atleast 1 slave"

    This has nothing to do with the TYPE of interconnect - I imagine you would have received a similar error if you used AXI. As the error itself points out, your system has (or would appear to have) no SLAVE peripherals, e.g. UARTlite, custom IP, etc.

    Just connect something to it, UART or GPIO would be a good bet, and you should be beyond this problem.

    Regards,

    Howard




    ----------"That which we must learn to do, we learn by doing." - Aristotle

  • RELEVANCY SCORE 2.42

    DB:2.42:Sending Ethernet Packets In Sp601 x3



    I m working with sp601 board.

    I am a beginner. I want to send some data from the fpga to the ethernet port so that i can read the data from pc.

    I m trying to go through trimode Mac pdf but it looks much more complex then what i intend to do.

    I would really appreciate if some one can tell me a simpler way or any idea .

    DB:2.42:Sending Ethernet Packets In Sp601 x3


    I m working with sp601 board.

    I am a beginner. I want to send some data from the fpga to the ethernet port so that i can read the data from pc.

    I m trying to go through trimode Mac pdf but it looks much more complex then what i intend to do.

    I would really appreciate if some one can tell me a simpler way or any idea .

  • RELEVANCY SCORE 2.41

    DB:2.41:If We Can't Use The Jtag Interface Of Sp601 Directly, What's The Meaning Of Tdi, Tdo, Tms... Of J12 Printed On The Board?? 88


    If we can't use the JTAG interface of SP601 directly, what's the meaning of TDI, TDO, TMS... of J12 printed on the board??

    is there a JTAG interface on WINBOND SPI flash? if not, I really dont know why there is JTAG sympol on that board.

    DB:2.41:If We Can't Use The Jtag Interface Of Sp601 Directly, What's The Meaning Of Tdi, Tdo, Tms... Of J12 Printed On The Board?? 88

    Thank you for your reply.

    Can I program the SPI flash memory directly with JTAG cable on J12 by impact ?? or only use other embeddedprocessor to program it?

  • RELEVANCY SCORE 2.41

    DB:2.41:A Custom Board Cable Error 9j



    I design a custom board, referring to the sp601,(with ddr2, ethernet, BPI flash) when I download some EDK .bit it get error:

    I can download .bit of EDK 11.5 well;

    and for EDK12.3, some simple EDK .bit can be downloaded well;

    but some EDK (include ddr2), when download it , it pull down the board power 3.3v-1.3v,0.9v-0.5v,1.8v-1.0v,

    and the impact display"

    "ERROR:Cse - A reference voltage has not been detected on the ribbon cable interface to the target system ( pin 2 ). Check that power is applied to the target system and that the ribbon cable is properly seated at both ends. The status LED on Platform Cable USB will be GREEN if target voltage is in the proper range and applied to the correct pin."

    It looks so strange.

    DB:2.41:A Custom Board Cable Error 9j


    the ccurent of 5v is 250mA, others can't get correctly,I will try

    A 1.25W input power supply likely isn't enough to be able to power the system. If this is a physical measurement this isn't what I was asking for, I was asking for the what the board power supplies are designed to provide.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.40

    DB:2.40:Lwip C Project In Sdk 13.1, Cannot Connect With Host Pc ka



    I am using a Xilinx Spartan SP601 eval board with ISE 13.1.

    I am attempting to design my own microblaze with ethernet lite using XPS 13.1 and use LwIP to connect to a host PC. The system builds ok using XPS. I open SDK 13.1 and create a new C Project, then I select the LwIP echo server Template. When I compile the project I get the following errors:

    ./src/platform_mb.c:34: error: 'XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR​' undeclared (first use in this function)

    I traced 'XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR​' to platform_config.h. It has no declaration.

    What file am I missing?

    Also, if I comment out the offending line, it compiles ok. Then, I download the *.bit and *.bmm files to the board. Next, run the project and the serial port outputs:

    -----lwIP TCP echo server ------TCP packets sent to port 6001 will be echoed backBoard IP: 192.168.1.10Netmask : 255.255.255.0Gateway : 192.168.1.1TCP echo server started @ port 7

    I connect a crossover ethernet cable to a host PC. The host PC has fixed IP address of 192.168.1.100. The ethernet LED's are blinking as expected. However, when I try to Ping the eval board from the host, I get the "host unresolved" error.

    Can anybody shed some light on these problems?

    Thanks, Richard







    Solved!
    Go to Solution.

    DB:2.40:Lwip C Project In Sdk 13.1, Cannot Connect With Host Pc ka

    或着仅仅修改下platform_config.h即可

    在#ifndef __PLATFORM_CONFIG_H_前加入如下

    #ifndef XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR //added manually#define XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR 1//added manually#endif//added manually

    这样更健壮一些

  • RELEVANCY SCORE 2.40

    DB:2.40:Sp 601 Fmc Connector j7


    Hi,

    We are purchasing the xilinx sp601 starter kit and we want to design our own FMC based daughter card. ASP_134603_01 is the part numberof FMC connector used in the board and we want to know the part number of mating part. Is it only available from samtec?



    FPGA freak

    DB:2.40:Sp 601 Fmc Connector j7


    If you want a 10 mm stack hight, lead free low pin count FMC connecter, yes.

  • RELEVANCY SCORE 2.40

    DB:2.40:Ddr2 Memory On Sp601 Board sd



    Hello,

    I am trying to use external RAM (Elpida DDR2 memory) on sp601as i am out of resources for creating any memory in the fpga.

    I have couple of questions.

    1) If i am right , i have to interface the external memory through MCB block on fpga.I coded my design in vhdl.

    Can i generate a vhdl code for the MCB using core generator tool?

    2) As far as the simulation model is concerned, i could see model in verilog on elpida website. Is there a vhdl simulation model out some where?

    3) I am a beginner, Would really appreciate if some one can help with some pdf needed to talk to external memory on sp601.

    4) Also, I m planning to use ISIM simulator that comes with xilinx ISE 12.1. Any suggestions on this?

    Thanks .

    DB:2.40:Ddr2 Memory On Sp601 Board sd

    Is there an equivalent Micron part that you can download a model for?



    ------------------------------------------"If it don't work in simulation, it won't work on the board."

  • RELEVANCY SCORE 2.40

    DB:2.40:Could Sp601 Generate A 500mhz Clock Using Dcm Without External Clock fk



    SP601:

    FPGA:Spartan-6 XC6SLX16-CS324

    Clock Generation There are three clock sources available on the SP601.

    1.Oscillator (Differential)
    The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the boardand wired to an FPGA global clock input.• Crystal oscillator: Epson EG2121CA• PPM frequency jitter: 50 ppm

    2.Oscillator Socket (Single-Ended, 2.5V or 3.3V)
    One populated single-ended clock socket (X2) is provided for user applications. The optionof 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The SP601 board isshipped with a 27MHz 2.5V oscillator installed

    3.SMA Connectors (Differential)
    A high-precision clock signal can be provided to the FPGA using differential clock signalsthrough the onboard 50-ohm SMA connectors J7(P)/J8(N).

    DB:2.40:Could Sp601 Generate A 500mhz Clock Using Dcm Without External Clock fk

    So what do the Spartan 6 User Guide and Data Sheet say about DCM frequencies?



    ----------------------------------------------------------------Yes, I do this for a living.

  • RELEVANCY SCORE 2.40

    DB:2.40:Using Oddr2 To Genenerate Gated Clock On Sp601 And Lx16csg324 zj



    Hi, All:

    I have sp601 (lx16csg324) and my target board probabaly will use lx16ftg256. My applicationrequires lx16 to generate multiple output gated clocks. I have seen post here saying oddr2 is the element to generate output gated clock. I have put one oddr2 and it seems works fine.If I need generate multiple output gated clocks on same bank, what should I do? Could I declare multiple oddr2 on same bank? Has anybody generated multiple gated clocks with spartan-6? Thanks!

    lf

    DB:2.40:Using Oddr2 To Genenerate Gated Clock On Sp601 And Lx16csg324 zj


    robinliuy: thank you for answering me!

    Yes, you are right. I have found out this by now. :smileyhappy:

  • RELEVANCY SCORE 2.40

    DB:2.40:Programmng The Sp601 cx



    Hi, I'm just got a sp601 board and to begin with, I'm still not very familiar with fpgas yet so bear with me.

    I'm trying to learn how to

    1. program the board with my own bitstream

    2.send and receive my own data from the fpga, using software if possible.

    The base reference design provides the HDL code; it uses ICAP_SPARTAN6 to program the fpga if I'm not wrong. I want to study the code to learn how to program it with ICAP_SPARTAN6, but it seems that the data comes in ethernet packets. I'm not familiar with ethernet packets and no source code is provided for the windows-application side, only the executable, so I'm not sure how I'm able to modify it to send my own data. Are there other methods of programming bitstreams?

    Then I checked for an alternative way to send data without using the ethernet. The standalone application examples seems to use EDK to program the fpga and send data with the USB JTAG. However, the sp601 board isn't supported in the EDK yet.

    Can anyone give me advice on how to proceed with this?

    Thanks.

    Ben
    Message Edited by novaelf on 11-26-2009 12:54 AM

    DB:2.40:Programmng The Sp601 cx


    EDK is a design tool for Processor Designs and it uses the ISE tools to actually implement and configure the device.

    EDK 11.4 will have full support creating processer designs for the Spartan-6 devices.

    ISE 11.2 and higher have full support for creating Spartan-6 designs and configuring devices.




    ------------------------------------------------------------------Have you tried typing your question into Google? If not you should before posting.Too many results? Try adding site:www.xilinx.com

  • RELEVANCY SCORE 2.40

    DB:2.40:Programming Spi At Sp601 Board By Platform Cable Usb Ii d7



    Hello all!

    Can anybody help me with such question. I tried to program SPI flash at SP601 board. I use Platform Cable USB II programmer and connect it to J12 socket on board. This socket has marked such as TDI, TDO, TCK etc. I found in documentation that this socket used for programming SPI flash. When I connect programmer to the board I see the led on Platform Cable programmer light green. But when I try to initialize chain in Impact software I get an error - too many unknown devices were found.

    Programmer is fine, i use it for programming my own boards (Spartan^ + Xilinx platfom flash).

    What I do wrong?

    Thanks.

    DB:2.40:Programming Spi At Sp601 Board By Platform Cable Usb Ii d7


    O, Bob, thanx for your answer.

    I knew about indirect programming method, but I could not understand why i can't to program directly. Now I understand it, thanks to your answer.

  • RELEVANCY SCORE 2.40

    DB:2.40:88e1111 Signals For Sp601 s3



    I use sp601 board, connecting xps_ethernetlite IPcore, and find PHY_INTB, PHY_TXER, PHY_GTXCLK are not used in this IPcore but connected in PCB Sch. I wonder if I disconnect the three signals, xps_ethernetlite will be running OK?







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.39

    DB:2.39:Connecting Ml 605 Board With Components On A Bread Board ff



    Hello,

    I'm new to virtex series of devices. I was able to do what I need (mentioned below) with virtex 5, XUPV5 device because there the IO pins are readily available to make connections using wires or pins.

    Need :To connect a few, around 15, IO pins on ML 605 virtex 6 board with components on a bread board.

    Problem : This board, ML 605 apparently uses a different, and new to me, way to connect IO's. From what I found it uses FMC but I have no idea about how to use it.

    Early searches :After doing a lot of search before posting here, I found the following links which seemed relavent.

    http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/SP601-SP605-Breakout-Board-Development/td-p/158998

    http://www.xilinx.com/products/boards_kits/fmc.htm

    http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/SP605-Breakout-Board/m-p/158926/message-uid/158926

    http://www.xilinx.com/products/boards-and-kits/HW-FMC-XM105-G.htm

    There is some take away from the above threads but I'm still confused. Should I be getting aFMC XM105 Debug Card? Or is there an easy way to do this ?







    Solved!
    Go to Solution.

    DB:2.39:Connecting Ml 605 Board With Components On A Bread Board ff


    Thanks a lot for your reply. I wanted to confirm things before I go a head and buy. Thanks again :)

  • RELEVANCY SCORE 2.39

    DB:2.39:Ethernet Send The Data In Sp601 mk



    sp601 ethernet ddr sram

    Dear all

    I build the a project using SP601 Kit Board

    I must use import the singal data to microblaze to calculate for my project

    but the signal have 4096*8192 float data, and in SP601, the fpga has not enough the BRAM to load the signal data

    I have a idea, because the kit board has 128M external memory space,

    I want to use the the Ethernet send the 4096*8192 float data to DDR RAM using MicroBlaze,and read the data from DDR

    How To ?:smileyhappy:

    DB:2.39:Ethernet Send The Data In Sp601 mk


    You'll need mpmc as an interface to DDR and either ethernet_lite or temac for Ethernet. Providing you have an application that can send data from PC using ethernet, the rest should be fairly easy. Receive data from temac/ethernet_lite and write it to DDR. You might want to use DMA to off-load the processor.

  • RELEVANCY SCORE 2.39

    DB:2.39:Use Sp601 With An Edk Eval License 3a


    Hello everybody!I will be using the SP601 for an academic project, and would like to try invoking a MicroBlaze in my design.Since the SP601 only includes the WebPack and the timeline of the project is limited, I came up with the idea of using an Evaluation License of the EDK to do some experiments with the MicroBlaze based designs. Picoblaze is no option, since I also want to try out a protocol stack which is designed exclusively for MicroBlaze.So my question, is it possible to use MicroBlaze with an Evaluation License of EDK on the SP601 board?Looking forward to your replies,Z.

    DB:2.39:Use Sp601 With An Edk Eval License 3a

    Hello everybody!I will be using the SP601 for an academic project, and would like to try invoking a MicroBlaze in my design.Since the SP601 only includes the WebPack and the timeline of the project is limited, I came up with the idea of using an Evaluation License of the EDK to do some experiments with the MicroBlaze based designs. Picoblaze is no option, since I also want to try out a protocol stack which is designed exclusively for MicroBlaze.So my question, is it possible to use MicroBlaze with an Evaluation License of EDK on the SP601 board?Looking forward to your replies,Z.