• RELEVANCY SCORE 3.33

    DB:3.33:Error:Edk:369 - Make Failed For Target "Libs" d9





    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling common"arm-xilinx-eabi-ar: creating ../../../lib/libxil.a"Compiling xadc""Compiling standalone""Compiling axidma"xaxidma_bdring.c: In function 'XAxiDma_BdRingToHw':xaxidma_bdring.c:1068:2: error: 'DATA_SYNC' undeclared (first use in this function)xaxidma_bdring.c:1068:2: note: each undeclared identifier is reported only once for each function it appears inmake[1]: *** [libs]"Compiling iic""Compiling axivdma""Compiling devcfg""Compiling dmaps""Compiling emacps""Compiling gpiops""Compiling iicps""Compiling qspips""Compiling scugic""Compiling scutimer""Compiling scuwdt""Compiling ttcps""Compiling uartps""Compiling usbps""Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a]

    I build a Planhead project using ISE14.3, and export the .bit file to SDK, so comes there two errors.

    The reason of the first error may be the 'DATA_SYNC',it is automatically generated, but I donot know why this error happened.Maybe inxaxidma_bdring.c: In function 'XAxiDma_BdRingToHw', there is something wrong.

    How about the second error?

    I found

    in the directory 'lib' filefolder, i cannot find 'libxil.a'.

    So thank you for your help.

    DB:3.33:Error:Edk:369 - Make Failed For Target "Libs" d9


    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling common"arm-xilinx-eabi-ar: creating ../../../lib/libxil.a"Compiling xadc""Compiling standalone""Compiling axidma"xaxidma_bdring.c: In function 'XAxiDma_BdRingToHw':xaxidma_bdring.c:1068:2: error: 'DATA_SYNC' undeclared (first use in this function)xaxidma_bdring.c:1068:2: note: each undeclared identifier is reported only once for each function it appears inmake[1]: *** [libs]"Compiling iic""Compiling axivdma""Compiling devcfg""Compiling dmaps""Compiling emacps""Compiling gpiops""Compiling iicps""Compiling qspips""Compiling scugic""Compiling scutimer""Compiling scuwdt""Compiling ttcps""Compiling uartps""Compiling usbps""Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a]

    I build a Planhead project using ISE14.3, and export the .bit file to SDK, so comes there two errors.

    The reason of the first error may be the 'DATA_SYNC',it is automatically generated, but I donot know why this error happened.Maybe inxaxidma_bdring.c: In function 'XAxiDma_BdRingToHw', there is something wrong.

    How about the second error?

    I found

    in the directory 'lib' filefolder, i cannot find 'libxil.a'.

    So thank you for your help.

  • RELEVANCY SCORE 3.22

    DB:3.22:Errors: Edk:546, Edk:1907, Edk:440 ca





    Hi,

    I'm using a 30-day evaluation version of Xilinx ISE 14.2. But I can't see the System Assembly View in XPS..!!!

    And, when I try to generate netlist, I'm getting following errors:

    ERROR:EDK:546 - Aborting XST flow execution!ERROR:EDK:1907 - NgcBuild failed!ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system_microblaze_0_wrapper.ngc] Error 2

    How can I resolve these...can anyone help me...

    DB:3.22:Errors: Edk:546, Edk:1907, Edk:440 ca


    Hi,

    I'm using a 30-day evaluation version of Xilinx ISE 14.2. But I can't see the System Assembly View in XPS..!!!

    And, when I try to generate netlist, I'm getting following errors:

    ERROR:EDK:546 - Aborting XST flow execution!ERROR:EDK:1907 - NgcBuild failed!ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system_microblaze_0_wrapper.ngc] Error 2

    How can I resolve these...can anyone help me...

  • RELEVANCY SCORE 3.21

    DB:3.21:Error When Trying To Execute The Project Using Edk 10.1 17





    Hi All,

    I am newbie, I want to make a small application using EDK kind display hello in hyperteminalI have Spartan 3 Starter Board and i'm using EDK 10.1 Service Pack 3I tried but I have this error

    Failed to run ELF executable on Target. Error initializing: XMD couldn't connect to remote target. Error::ERROR: Could Not Detect MDM Peripheral on Hardware. Check: 1. If FPGA is Configured Correctly 2. MDM Core is Instantiated in the Design Error initializing: XMD couldn't connect to remote target. Error::ERROR: Could Not Detect MDM Peripheral on Hardware. Check: 1. If FPGA is Configured Correctly 2. MDM Core is Instantiated in the Design

    Waiting for your help

    Thank You :)

    DB:3.21:Error When Trying To Execute The Project Using Edk 10.1 17


    Hi All,

    I am newbie, I want to make a small application using EDK kind display hello in hyperteminalI have Spartan 3 Starter Board and i'm using EDK 10.1 Service Pack 3I tried but I have this error

    Failed to run ELF executable on Target. Error initializing: XMD couldn't connect to remote target. Error::ERROR: Could Not Detect MDM Peripheral on Hardware. Check: 1. If FPGA is Configured Correctly 2. MDM Core is Instantiated in the Design Error initializing: XMD couldn't connect to remote target. Error::ERROR: Could Not Detect MDM Peripheral on Hardware. Check: 1. If FPGA is Configured Correctly 2. MDM Core is Instantiated in the Design

    Waiting for your help

    Thank You :)

  • RELEVANCY SCORE 3.20

    DB:3.20:Error Mdt With Spartan 3a sa



    Hallo,

    I get the following msg when I try to build my project. Is it because of the 60 days license? Or can't I put a microBlaze on Spartan 3A?

    If you need more information, I will give it to you for sure!

    Thanks

    Joerg

    error msg:

    Generating Block Diagram : C:\edk\test\blkdiagram\system.html...

    Generating Block Diagram : C:\edk\test\blkdiagram\system.html...Generated --- system.svgBlock diagram generated.Copied C:/Xilinx/10.1/EDK/data/xflow/bitgen_spartan3a.ut to etc directoryAt Local date and time: Fri Jan 09 11:29:49 2009xbash -q -c "cd /cygdrive/c/edk/test/; /usr/bin/make -f system.make download; exit;" started...****************************************************Creating system netlist for hardware specification..****************************************************platgen -p xc3s400aft256-4 -lang vhdl system.mhs

    Release Xilinx EDK 10.1 - platgen EDK_K.15Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

    Command Line: platgen -p xc3s400aft256-4 -lang vhdl system.mhs

    WARNING:MDT - You are using an evaluation version of Xilinx Software. In 60 days, hardware generation in this program will not operate. Software applications can still be generated. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!Parse system.mhs ...

    Read MPD definitions ...ERROR:MDT - IPNAME:microblaze INSTANCE:microblaze_0 - C:\edk\test\system.mhs line 22 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:plb_v46 INSTANCE:mb_plb - C:\edk\test\system.mhs line 34 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:lmb_v10 INSTANCE:ilmb - C:\edk\test\system.mhs line 41 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:lmb_v10 INSTANCE:dlmb - C:\edk\test\system.mhs line 48 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:lmb_bram_if_cntlr INSTANCE:dlmb_cntlr - C:\edk\test\system.mhs line 55 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:lmb_bram_if_cntlr INSTANCE:ilmb_cntlr - C:\edk\test\system.mhs line 64 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:bram_block INSTANCE:lmb_bram - C:\edk\test\system.mhs line 73 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:xps_gpio INSTANCE:leds - C:\edk\test\system.mhs line 80 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:clock_generator INSTANCE:clock_generator_0 - C:\edk\test\system.mhs line 93 - not supported for architecture 'spartan3a'!ERROR:MDT - IPNAME:proc_sys_reset INSTANCE:proc_sys_reset_0 - C:\edk\test\system.mhs line 108 - not supported for architecture 'spartan3a'!ERROR:MDT - platgen failed with errors!Done!

    DB:3.20:Error Mdt With Spartan 3a sa


    Thanks for your help! I forgot to install the latest SP. Thanks for the link!

    Joerg

  • RELEVANCY SCORE 3.10

    DB:3.10:Login Dialog k9


    I have 2 deployment profiles 'Local' and '9iAS' which is the deployment of the BC4J as an EJB session bean.
    for both connections jbo.security.enforce is set to must.
    In the tester we are prompted for a username/password if we use the 'Local' profile. it we use '9iAS' we do not get a loginbox but :
    java.lang.NullPointerException

    void oracle.jbo.jbotester.BaseTree.setAppModule(oracle.jbo.ApplicationModule)

    BaseTree.java:162

    void oracle.jbo.jbotester.MainFrame.connected()

    MainFrame.java:404

    void oracle.jbo.jbotester.MainFrame.init()

    MainFrame.java:369

    void oracle.jbo.jbotester.MainFrame.main(java.lang.String[])

    MainFrame.java:340

    if we use a form with the JCLoginDialog.java. Then the 'local' profile gives us an error if the credentials or not correct. JBO-30003, JBO-25222 and JBO-33021: Failed authenticate user qsfdn
    Why doesn't it just return the loginbox again?

    the '9iAS' gives us(without a loginbox) the following error JBO-33021: Failed authenticate user admin

    What can i do to make this work ok,
    thanks,
    Bert.

    DB:3.10:Login Dialog k9

    Bert,

    What you did is correct. Do not throw exception in modifyInitialContext. This method is called just before getInfo and the object initialContext is the environment hashtable which may be modified by getInfo to provide dynamic application module context.

    Thanks,
    Yvonne

  • RELEVANCY SCORE 3.07

    DB:3.07:Missing Script "Edk11_2_Revup_Xmp.Pl" x1



    I'm trying to upgrade a project from ISE 9.x to ISE 11.4 I've had a number of minor

    problems, but now I've reached a point where EDK gives the following complaint:

    WARNING:EDK - This project was created with version older than EDK 11.4!!WARNING:EDK - XPS will update the project to EDK 11.4WARNING:EDK - Your current files will be saved with .old version extensionReving up design to EDK 11.4...Can't open perl script"c:\apps\Xilinx_ISE_11\EDK\data\xps\scripts\edk11_2_revup_xmp.pl": No such fileor directoryERROR:EDK - Revup to 11.4 failedERROR:EDK - Error(s) were encountered while updating your project.ERROR:EDK - while running revupProcess "Updating XPS project device settings" failed

    Has anyone run into this and solved it?

    Thanks!

    John P.

    DB:3.07:Missing Script "Edk11_2_Revup_Xmp.Pl" x1


    I see the edk11_4_revup_xmp.pl in my 11.4 install. You might want to reinstall if you are missing files.

  • RELEVANCY SCORE 3.04

    DB:3.04:Problems Using Chipscope 33


    Hello,I'm doing the ChipScope Embedded Processor Lab to learn how to use the ChipScope in a XPS project. I went to Debug-Debug Configuration.... in order to add a chipscope to the project. I took the folows options:1)Click the Add Chipscope Peripheral... button2)Selected the first option, To monitor OPB bus signals (adding OPB IBA)3)Click to put a check mark in the Enable Hardware/Software Co-debug fieldWith that I creteted two peripherals named chipscope_icon_0 and chipscope_plbv46_iba_0.Then I want to generate the Netlist but there are errors. The XPS Output saysRunning DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...Check platform configuration ...IPNAME:plb_v46 INSTANCE:mb_plb - C:\EDKprojects\EDK-Labs\LAB6-2\system.mhs line48 - 2 master(s) : 9 slave(s)make: *** [implementation/microblaze_0_wrapper.ngc] Error 2IPNAME:lmb_v10 INSTANCE:ilmb - C:\EDKprojects\EDK-Labs\LAB6-2\system.mhs line 55- 1 master(s) : 1 slave(s)IPNAME:lmb_v10 INSTANCE:dlmb - C:\EDKprojects\EDK-Labs\LAB6-2\system.mhs line 62- 1 master(s) : 1 slave(s)ERROR:MDT - IPNAME:mdm INSTANCE:debug_module BUS_INTERFACE:SPLB - C:\EDKprojects\EDK-Labs\LAB6-2\system.mhs line 137 - invalid bus interface in use when ISVALID="((C_INTERCONNECT == 1) (C_USE_UART == 1))" evaluates to FALSE. Please remove the bus interface from your design!ERROR:MDT - platgen failed with errors!Done!What can I do to fix the problem?I'm using the 10.1 version with the last update.Thanks

    DB:3.04:Problems Using Chipscope 33


    Hello,

    you can get past the error by setting the C_USE_UART = 1 for the mdm module. Either edit the .mhs file directly or right click the mdm/ debug module in XPS and select "configure IP..." and check "Enable JTAG UART".

    I don't know if doing this it will cause any other problems later...

    HTH

    --

    Magne

  • RELEVANCY SCORE 3.01

    DB:3.01:Booting From Flash To Fpga jc



    Hi ,

    I am using Virtex5LX110 fpga and EDK 9.2 version.In my proj i want to boot the code from flash.

    So, I am creating a MDM module in my proj.But am facing an error in console window while update the bitstream.
    I mentioned the error below as follows..Check platform configuration ...IPNAME:plb_v46 INSTANCE:mb_plb -I:\ISE_XPS\Flas_bootloader\system.mhs line 60 - 2 master(s) : 5 slave(s)IPNAME:lmb_v10 INSTANCE:ilmb -I:\ISE_XPS\Flas_bootloader\system.mhs line 67 - 1 master(s) : 1 slave(s)IPNAME:lmb_v10 INSTANCE:dlmb -I:\ISE_XPS\Flas_bootloader\system.mhsline 74 - 1 master(s) : 1 slave(s)Check port drivers...WARNING:MDT - INST:mdm_0 PORT:Debug_SYS_Rst CONNECTOR:mdm_0_Debug_SYS_Rst -I:\ISE_XPS\Flas_bootloader\system.mhsline 256 - floating connection!ERROR:MDT - SIGNAL:Ext_BRK - multiple drivers found: INST:debug_module PORT:Ext_BRK - F:\edk\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 69! INST:mdm_0 PORT:Ext_BRK - F:\edk\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 69!ERROR:MDT - SIGNAL:Ext_NM_BRK - multiple drivers found: INST:debug_module PORT:Ext_NM_BRK -F:\edk\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 70! INST:mdm_0 PORT:Ext_NM_BRK -F:\edk\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 70!Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...ERROR:MDT - platgen failed with errors!make: *** [implementation/system.bmm] Error 2Done!ERROR location in .mpd file## PortsPORT Interrupt = "", DIR = O, EDGE = RISINGPORT Debug_SYS_Rst = "", DIR = OPORT Ext_BRK = Ext_BRK, DIR = OPORT Ext_NM_BRK = Ext_NM_BRK, DIR = OPORT SPLB_Clk = "", DIR = I, SIGIS = Clk, BUS = SPLBPORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = Rst, BUS = SPLBPlease give me the solution for the above mentioned error.Regards,Muthu

    DB:3.01:Booting From Flash To Fpga jc


    Dear Muthu,

    Can you share the HMS, MSS file

    thanks,

    rajesh.

  • RELEVANCY SCORE 3.00

    DB:3.00:Encountered Errors During Running Xps In Planahead(14.7 Web) s9



    Checking platform address map ...process_begin: CreateProcess(E:\TEMP\make25144-1.bat, E:\TEMP\make25144-1.bat, ...) failed.make (e=2): The system cannot find the file specified。make: *** [simulation/behavioral/system_setup.tcl] error 2ERROR:EDK - Error while running "make -f system.make simmodel".ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [E:/WORK_P/Learning_ZedBoard/HelloZed1010/HelloZed​1010.srcs/sources_1/edk/system/__xps/pa/_system_si​m.tcl]

    ==================================

    I have overviewd some websites about this issue, but can not resolve it.

    May it have something to do with mingw(a compiler in Windows?)

  • RELEVANCY SCORE 2.98

    DB:2.98:Slow Syntax Check In Edk zf



    hi,

    whenever I change a HDL code in EDK in my own custome IP , I should regenerate ( sometime clean up all project files to make EDK know that somethings has changed! ) it goes deeply into syntesis process file by file and takes so long time EVEN when I had a syntax error in HDL files.

    is there a faster way to check HDL codes syntax faster? or make EDK firts check HDLs syntax and then goes to synthesis process?

    DB:2.98:Slow Syntax Check In Edk zf

    moving newly edited IP cores to top of MHS file was good solution for fast syntax check

    but now after I moved to ISE 13.2 something has changed and this solution is not usefull.

    does anybody know why EDK is so slow in syntax check? how this problem can be solved?

    to lockiegrogan : what is CIP wizard? altough I can open HDL file of my EDK project inside ISE but EDK HDL file are not directly visible to ISE. soemtime when I change a custom IP core HDL file, ISE and EDK does not recognize project has changed!

  • RELEVANCY SCORE 2.93

    DB:2.93:Synthesis Problem Of Edk Project Attached In The Ise 12.4 8p



    Xilinx Port::Process Exec Failed:2ERROR:EDK - Error while running "gmake -f system.make netlist".ERROR: synthesizing XPS module failed!Process "XPS Process: Synthesize XPS Source" failed

    Best wishes !

  • RELEVANCY SCORE 2.92

    DB:2.92:Error:Edk:440 - Platgen Failed With Errors! (Virtex 4 Fx 12 Lc Developmentboard sa



    Hi

    My board: Virtex 4 FX 12 LC Developmentboard.

    I tried to do the mandelbrot example for the ML 403.

    I am working with EDK11.1

    When I finished to create everythingI tried to generate the bitstream for the download.

    ButI get the message:

    ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system.bmm] Error 2

    Does anyone know how to fix it?

    DB:2.92:Error:Edk:440 - Platgen Failed With Errors! (Virtex 4 Fx 12 Lc Developmentboard sa


    The problem was that I forgot to connect the MFCB with the ppc405_0

    Sorry, but Thank you for your reply

    Ramona

  • RELEVANCY SCORE 2.90

    DB:2.90:Error When Making Edk Library a7


    hello
    there are two errors when I make xilinx library to modelsim.All occurs when make edk library showing in the pictures.
    And I install ise 14.7 and modelsim 10.1a SE.
    please tell me how to solve them.

    Thank you very much









    Attachments:




    DB:2.90:Error When Making Edk Library a7

    Can you post the complete compxlib.log? I want to check the options which you have used while compiling this?



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.89

    DB:2.89:Edk Licensing Within Vivado 2013.4 s1



    Hi folks,

    I'm using Vivado 2013.4 on Win7-64. I do have a project that is embedding a Microblaze AXI platform. However, "Generate Output Products" command is failing with the following message:

    ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [W:/EGP0023/Vivado/Vivado.srcs/sources_1/edk/DMAIn​terconnectCore/__xps/pa/_DMAInterconnectCore_synth​.tcl]

    The problem is an EDK-licensing one. For some reason, the tool is not getting the license. This is the exact same problem as for Vivado 2012.2 (http://www.xilinx.com/support/answers/51222.html). However, the solution described in AR51222 doesn't work for 2013.4. I no longer have ISE and EDK installed; just Vivado 2013.4.

    The full message log appears below:

    generate_target all [get_files W:/EGP0023/Vivado/Vivado.srcs/sources_1/edk/DMAInt​erconnectCore/DMAInterconnectCore.xmp]

    INFO: [Edk 24-181] Generating synthesized netlists for the XPS sub-design source 'DMAInterconnectCore'...

    Xilinx Platform Studio Xilinx EDK 14.7 Build EDK_2013.4.20131205 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    XPS% Evaluating file W:\EGP0023\Vivado\Vivado.srcs\sources_1\edk\DMAInt​erconnectCore\__xps\pa\_DMAInt erconnectCore_synth.tcl

    Overriding IP level properties ... INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axilite_0 - tcl is overriding PARAMETER C_BASEFAMILY value to kintex7 - E:\Xilinx\Vivado\2013.4\ids_lite\EDK\hw\XilinxProc​essorIPLib\pcores\axi_inter connect_v1_06_a\data\axi_interconnect_v2_1_0.mpd line 81

    Computing clock values...

    Performing IP level DRCs on properties...

    Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

    Checking platform address map ... "*************************************************​***" "Creating system netlist for hardware specification.." "*************************************************​***" platgen -p xc7k325tffg676-1 -lang vhdl -intstyle vivado -st rst -toplevel no -ti DMAInterconnectCore_i -msg __xps/ise/xmsgprops.lst DMAInterconnectCore.mhs

    Command Line: platgen -p xc7k325tffg676-1 -lang vhdl -intstyle vivado -st rst -toplevel no -ti DMAInterconnectCore_i -msg __xps/ise/xmsgprops.lst DMAInterconnectCore.mhs

    ERROR:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2492@verdi'. INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to '2492@verdi'. INFO:Security:71 - If a license for part 'xc7k325t' is available, it will be possible to use 'XPS_TDP' instead of 'XPS'. INFO:Security:7a - A feature for XPS was found but is for an older version. INFO:Security:68a - user is user0676, on host STATION-E2544. WARNING:Security:43 - No license file was found in the standard Xilinx license directory. WARNING:Security:44 - Since no license file was found, please run the Xilinx License Configuration Manager (xlcm or "Manage Xilinx Licenses") to assist in obtaining a license. WARNING:Security:9b - No 'XPS' feature version 2013.12 was available for part 'xc7k325t'. ERROR:Security:12 - No 'xc7k325t' feature version 2013.12 was available (-5), so 'XPS_TDP' may not be used.

    License file does not support this version. Feature: XPS Application version License version: 2013.12 2013.11 License path: 2492@verdi;C:\Xilinx\13.3\ISE_DS\EDK\data\core_lic​enses;H:/.Xilinx;E:/Xilinx/ Vivado/2013.4/ids_lite/ISE/coregen/core_licenses\X​ilinx.lic;E:/Xilinx/Vivado/ 2013.4/ids_lite/ISE/coregen/core_licenses\XilinxFr​ee.lic;E:/Xilinx/Vivado/201 3.4/ids_lite/EDK/data/core_licenses\Xilinx.lic; FLEXnet Licensing error:-21,126 For further information, refer to the FLEXnet Licensing documentation, available at "www.flexerasoftware.com".No such feature exists. Feature: xc7k325t License path: 2492@verdi;C:\Xilinx\13.3\ISE_DS\EDK\data\core_lic​enses;H:/.Xilinx;E:/Xilinx/ Vivado/2013.4/ids_lite/ISE/coregen/core_licenses\X​ilinx.lic;E:/Xilinx/Vivado/ 2013.4/ids_lite/ISE/coregen/core_licenses\XilinxFr​ee.lic;E:/Xilinx/Vivado/201 3.4/ids_lite/EDK/data/core_licenses\Xilinx.lic; FLEXnet Licensing error:-5,412 For further information, refer to the FLEXnet Licensing documentation, available at "www.flexerasoftware.com". ERROR:EDK:440 - platgen failed with errors! make: *** [implementation/DMAInterconnectCore.edf] Error 2 ERROR:EDK - Error while running "make -f DMAInterconnectCore.make netlist".

    ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [W:/EGP0023/Vivado/Vivado.srcs/sources_1/edk/DMAIn​terconnectCore/__xps/pa/_DMAInterconnectCore_synth​.tcl]

    Any hint???

    Cheers!

    Claude

    DB:2.89:Edk Licensing Within Vivado 2013.4 s1


    Hello all,

    Finally, my IT folks said they "regenerated" the licence file and everything is now OK. I'm not too sure what that means, but it worked!

    Problem solved, even though I don't have a "clear" solution to post here.

    Claude

  • RELEVANCY SCORE 2.88

    DB:2.88:Edk 11.4 - Xps Ethernet Lite - Platgen Error 1m



    I'm trying to use the XPS 10/100 Ethernet MAC Lite core with Microblaze in a Spartan 3E, but I keep getting the following error in EDK 11.4. I've tried adding the core to an already working project and also starting from scratch and the result is the same. Anyone have success doing this before? I can't tell if this an EDK problem or if I'm just missing something.

    Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...ERROR:EDK - xget_value name : a null handle was providedERROR:EDK - xps_ethernetlite_0 (xps_ethernetlite) - expected integer but got "" ERROR:EDK:440 - platgen failed with errors!

    DB:2.88:Edk 11.4 - Xps Ethernet Lite - Platgen Error 1m


    Hi,

    check out my previous post http://forums.xilinx.com/xlnx/board/message?board.​id=EDKmessage.id=14109

    I had a very similar problem

    Regards

    Lachlan.

  • RELEVANCY SCORE 2.87

    DB:2.87:Could Not Find Bestrun In System_Xplorer.Rpt File. 8z



    Hi Everyone,

    When I'm generating the bitstream for Virtex5, I receive the following error:

    Executing 'ngdbuild -sd . -p xc5vfx70tff1136-1 -dd [PATH] ...run1.log RETURN CODE: 2

    Initial ngdbuild failed.
    ERROR: Could not find BestRun in system_xplorer.rpt file.
    Possible reasons :
    1. There were errors in ngdbuild.
    2. There were timing errors.
    at D:/Xilinx/10.1/EDK/data/fpga_impl/edk_xplorer.pl line 128, XPLORER_RPT line 11.
    make: *** [__xps/system_routed] Error 2

    Initial ngdbuild failed.

    ERROR: Could not find BestRun in system_xplorer.rpt file.Possible reasons :

    1. There were errors in ngdbuild.

    2. There were timing errors.

    at D:/Xilinx/10.1/EDK/data/fpga_impl/edk_xplorer.pl line 128, XPLORER_RPT line 11.

    make: *** [__xps/system_routed] Error 2

    Could anyone help me with this?

    Thanks

    DB:2.87:Could Not Find Bestrun In System_Xplorer.Rpt File. 8z


    Hi,

    Are you trying to run smartXplorer for a EDK based design ?

    If yes, have you tried to run it from Project Navigator.

    Thnx




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.86

    DB:2.86:Edk 10.1 -Bfm Simulation mz



    Hi All,

    I have EDK 10.1 and modelsim6.1e version.

    Are these compatible?

    Please let me know which version of Modelsim SE should be used with EDK 10.1

    When I run Simulatiom Library compilation wizard, ISE libraries get compiled without any errors.

    When I run EDK simulation libraries, it gets compiled but but shows

    "No. of compile errors found:85". Doesn't say what is the error.

    I have pasted the summary below

    ISE Simulation Library Path: C:\edk_ise_sim_lib_10\ISE\Number of compile errors found: 0

    EDK Simulation Library Path: C:\edk_ise_sim_lib_10\EDK\Compilation Option: Deprecated and obsolete components are not compiled.

    After doing this, when I execute this command in the EDK_shell,

    Number of compile errors found: 85

    Simulator: mtiSimulator Version: Model Technology ModelSim SE vsim 6.1e Simulator 2006.03 Mar 8 2006

    Supported HDL: both VHDL and Verilog

    Smartmodel Installation Path: C:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\

    After executing the below command in the EDK_shell

    'make -f bfm_sim_cmd.make sim' , I get the following errors in the modelsim window

    -- Loading package std_logic_1164# -- Loading package std_logic_arith# -- Loading package std_logic_unsigned# ** Error: (vcom-19) Failed to access library 'unisim' at "unisim".# No such file or directory. (errno = ENOENT)# ** Error: c:/Modeltech_6.1e/win32/vcom failed.# Error in macro ./bfm_system.do line 48# c:/Modeltech_6.1e/win32/vcom failed.# while executing# "vcom -novopt -93 -work proc_common_v1_00_b "C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores​/proc_common_v1_00_b/hdl/vhdl/pselect.vhd""

    Please let me know is there is any setting required to run this? Or should I go for a different version of modelsim..

    Thanks,

    Shilpa

    DB:2.86:Edk 10.1 -Bfm Simulation mz


    Hi,

    When I simulate my model (schematic) after giving levels to my input. I am getting the following error in modelsim when I am clicking on "Simulate behavioral VHDL model".

    ** Error: (vcom-19) Failed to access library 'unisim' at "unisim".# No such file or directory. (errno = ENOENT)# ** Error: C:/Modeltech_6.1e/win32/vcom failed.# Error in macro ./bilal.fdo line 5# C:/Modeltech_6.1e/win32/vcom failed.# while executing# "vcom -explicit -93 "syed.vhf""

    Using following versions

    Xilinx:10.1i, ModelSim: 6.1e

    Thanks

    Syed

  • RELEVANCY SCORE 2.85

    DB:2.85:Edk Failed To Move File, What's Wrong? mj



    I create a normal project. when i update bitstream, the following error are counted.

    unning XST synthesis ...INFO:MDT - The following instances are synthesized with XST. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.INSTANCE:microblaze_0 - D:\work\xilinx_xps\2010NEC\mbtestv4\system.mhs line 34 -Running XST synthesisERROR:MDT - Aborting XST flow execution!INFO:MDT - Refer to D:\work\xilinx_xps\2010NEC\mbtestv4\synthesis\microblaze_0_wrapper_xst.srp for detailsRunning NGCBUILD ...ERROR:MDT - IPNAME:rs232_port_wrapper INSTANCE:rs232_port - D:\work\xilinx_xps\2010NEC\mbtestv4\system.mhs line 133 - failed to move D:\work\xilinx_xps\2010NEC\mbtestv4\implementation\rs232_port_wrapper.ngc to D:\work\xilinx_xps\2010NEC\mbtestv4\implementation\rs232_port_wrapper\rs232_p ort_wrapper.ngcRebuilding cache ...ERROR:MDT - platgen failed with errors!make: *** [implementation/microblaze_0_wrapper.ngc] Error 2Done!

    Does someone know the reason?

    DB:2.85:Edk Failed To Move File, What's Wrong? mj


    Actually, I've experienced similar errors due to EDK creating folders without write properties for one or more accounts (and no, being on an administrator does not automatically give you access to everything sadly).

    But if you go into Properties-Security for the folder(s) in question, try fiddling around with the access privileges - it's been some time since I had the problem, so I can't remember exactly what was wrong, just that I was able to fix it in there. You might also have to turn off simple file sharing for this to work.

  • RELEVANCY SCORE 2.84

    DB:2.84:Error:Edk:3424 - Failed To Copy From.. ma



    Hi All,

    I hope someone can help me with this. I am working with zedboard on SDK 14.5 on ubuntu12.04.

    I had a working version of my design in SDK with hw_platform, bsp and my SW. I did some changes in HW and exported the HW to SDK. Once the SDK was launched the BSP was rebuilt and It gave me the error while staging sources as follows.

    14:33:07 **** Build of project standalone_bsp_0 ****
    make -k all
    libgen -hw ../zed_hw_platform/system.xml\
    \
    -pe ps7_cortexa9_0 \
    -log libgen.log \
    system.mss
    libgen
    Xilinx EDK 14.5 Build EDK_P.58f
    Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../zed_hw_platform/system.xml -pe
    ps7_cortexa9_0 -log libgen.log system.mss

    Staging source files.
    ERROR:EDK:3424 - Failed to copy from
    /ise_local2/umair_temp/14.5/ISE_DS/EDK/sw/lib/bsp/standalone_v3_09_a/src/
    into
    /nfs/SystemDesign/work/zynq/umair/MyDesigns/cf_adv7511
    _cam/zed/SDK/SDK_Workspace/standalone_bsp_0/ps7_cortexa9_0/libsrc/
    standalone_v3_09_a/src/.
    ERROR:EDK:3419 - Error(s) while staging sources.
    make: *** [ps7_cortexa9_0/lib/libxil.a] Error 2
    make: Target `all' not remade because of errors.

    I would like to mention that I had been exporting hardware to SDK earlier for the same design and sometimes it got exported without errors and sometimes it gave errors like this. When I got these errors earlier I used to re-export and regenerate the BSP but this work-around is also not helping this time.

    I get following errors when I recreate the BSP.

    Staging source files.
    ERROR:EDK:3424 - Failed to copy from
    /ise_local2/umair_temp/14.5/ISE_DS/EDK/sw/lib/bsp/standalone_v3_09_a/src/
    into
    /nfs/SystemDesign/work/zynq/umair/MyDesigns/cf_adv7511
    _cam/zed/SDK/SDK_Workspace/standalone_bsp_1/ps7_cortexa9_0/libsrc/
    standalone_v3_09_a/src/.
    ERROR:EDK:3424 - Failed to copy from
    /ise_local2/umair_temp/14.5/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/devcfg
    _v2_02_a/src/ into
    /nfs/SystemDesign/work/zynq/umair/MyDesigns/cf_adv7511
    _cam/zed/SDK/SDK_Workspace/standalone_bsp_1/ps7_cortexa9_0/libsrc/
    devcfg_v2_02_a/src/.
    ERROR:EDK:3424 - Failed to copy from
    /ise_local2/umair_temp/14.5/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/scugic
    _v1_03_a/src/ into
    /nfs/SystemDesign/work/zynq/umair/MyDesigns/cf_adv7511
    _cam/zed/SDK/SDK_Workspace/standalone_bsp_1/ps7_cortexa9_0/libsrc/
    scugic_v1_03_a/src/.

    Why is do i see these errors and how to get rid of these? Thanks

    Umair

    DB:2.84:Error:Edk:3424 - Failed To Copy From.. ma


    I don't know what makes it "too long" Is there a discrete character limit to watch out for, or do people know that there seems to be issues with longer names? I don't have a space, but I do have a period in one of the folder names (which I just saw someone saying could be a problem if you use more than 3 characters after the period). I pulled out the period and am trying to rebuild as we speak.

    edit

    OK, still no dice. It seemed like it compiled, but when I went to open one of my .c files, it claimed to not be able to find it. After I cleaned everything out, and rebuilt, I got a bunch of errors again. The workspace sits at:

    C:\ltsdelayedtaps\src\fpga\SCM\ublaze_workspace\

    Now the libgen.log shows a slightly different:

    Release 14.2 - libgen Xilinx EDK 14.2 Build EDK_P.28xd
    (nt64)
    Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../ublaze_hw_platform/system.xml -pe microblaze_0 -log
    libgen.log system.mss

    Staging source files.
    Running DRCs.
    Running generate.
    Running post_generate.
    Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
    "COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift
    -mxl-pattern-compare -mcpu=v8.40.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
    "COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift
    -mxl-pattern-compare -mcpu=v8.40.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
    ERROR:EDK:369 - make failed for target "libs"
    ERROR:EDK:3418 - Error(s) while running make.

  • RELEVANCY SCORE 2.82

    DB:2.82:Failed To Open Elf File In Linux 1k



    Hi,

    I am trying to build a EDK project in project navigator.

    I make a new ISE project and include the EDK project. Then I click Update Bitstream with Processor Data. It chucks away nicely until it comes to the software part where I get this error:

    Checking ELFs associated with MICROBLAZE instance interface_cpu for overlap...

    ERROR:MDT - Failed to open elf file
    SDK_Projects/interface_sw/Release/interface_sw.elf for reading

    gmake: *** [implementation/download.bit] Error 1

    ERROR:MDT - Error while running "gmake -f system.make init_bram"

    No changes to be saved in MSS file

    No changes to be saved in XMP file

    ERROR: Bitstream update failed, XPS did not generate ./implementation/download.bit

    Have anybody else had this problem?

    I have checked the SDK_Projects/interface_sw/Release/interface_sw.elf file, and it is there and readable. One thing it might be is, that the absolute path is wrong, so I have tried to check which file it tries to open using strace. Is there any way to debug the build process to see which files it tries to open?

    Thanks,

    Nikolaj Fogh

    DB:2.82:Failed To Open Elf File In Linux 1k


    Hi,

    I am trying to build a EDK project in project navigator.

    I make a new ISE project and include the EDK project. Then I click Update Bitstream with Processor Data. It chucks away nicely until it comes to the software part where I get this error:

    Checking ELFs associated with MICROBLAZE instance interface_cpu for overlap...

    ERROR:MDT - Failed to open elf file
    SDK_Projects/interface_sw/Release/interface_sw.elf for reading

    gmake: *** [implementation/download.bit] Error 1

    ERROR:MDT - Error while running "gmake -f system.make init_bram"

    No changes to be saved in MSS file

    No changes to be saved in XMP file

    ERROR: Bitstream update failed, XPS did not generate ./implementation/download.bit

    Have anybody else had this problem?

    I have checked the SDK_Projects/interface_sw/Release/interface_sw.elf file, and it is there and readable. One thing it might be is, that the absolute path is wrong, so I have tried to check which file it tries to open using strace. Is there any way to debug the build process to see which files it tries to open?

    Thanks,

    Nikolaj Fogh

  • RELEVANCY SCORE 2.82

    DB:2.82:Fatal Error With Edk 11.3 mj



    hi,

    i am using EDK 11.3 with my custom board, recently i updated it from 11.1.

    i created a small project(microblaze processor without any peripherals) in EDK and i tried to generate bitstream. i gave the command 'update

    bitstream' to generate bitfile,

    then i got the following error and tool execution is stopped.

    ERROR:EDK:440 - platgen failed with errors!FATAL_ERROR:Portability:PortDynamicLib.c:399:1.32 - dll open of library C:/Xilinx/11.1/ISE\lib\nt\libGenXstTask.dll failed due to The specified procedure could not be found. . Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.make: *** [implementation/microblaze_0_wrapper.ngc] Error 2

    what might be the reason for this error?

    how to solve that ?

    thanks in advance ,

    regards,

    Varun.G







    Solved!
    Go to Solution.

    DB:2.82:Fatal Error With Edk 11.3 mj


    For an install you need 2x the install size + an extra 2 GB. Unfortunately, the installer doesn't check this size, per AR32488:

    "The ISE Design Suite installer/updater estimates the amount of space that ISE Design Suite uses to install the tools. This value only takes into consideration the disk space used by the installed tools and not the size required for the installer/updater files. "

    When the installer runs out of disk space during the install, the DLLs or SO files are just not installed... hence:

    "failed due to The specifiedprocedure could not be found"

    The tools must be reinstalled with enough room ~ 15 GB free space to resolve this issue.

    Message Edited by nikc on 04-26-2010 11:56 AM

  • RELEVANCY SCORE 2.82

    DB:2.82:Xilinx Ise Design Suite 11.1 Problem License c7



    Hi,

    I have ISE 11.1 (including DSP Tools 11.1) and Matalb 2008b installed on my PC (Win XP 32bit). But i get a "Xilinx License Error" when i start 'Manage Xilinx licenses'.

    It says''

    --------------------------------- Version Log ----------------------------------Version PathSystem Generator 11.1.1666 C:/Xilinx/11.1/DSP_Tools/nt/sysgenAccelDSP 11.1.1666 C:/Xilinx/11.1/DSP_Tools/nt/AccelDSPMatlab 7.7.0.471 (R2008b) C:/Programme/MATLAB/R2008bISE 11.1.i C:/Xilinx/11.1/ISE--------------------------------------------------​------------------------------Summary of Errors:Error 0001: ERROR: A license check out has failed for product: System... Block: Unspecified--------------------------------------------------​------------------------------Error 0001:Reported by: UnspecifiedDetails:ERROR: A license check out has failed for product: SystemGenerator for DSP (SysGen) ------------------- A message from the license manager --------------INFO:Security:61 - The XILINXD_LICENSE_FILE environment variableis not set.INFO:Security:63 - The LM_LICENSE_FILE environment variable isnot set.INFO:Security:68 - Please run the Xilinx License Configuration Manager (xlcm or "Manage Xilinx Licenses") to assist in obtaining a license.ERROR:Security:14 - No feature was available for 'SysGen'.--------------------------------------------------​------------------Cannot connect to license server system.The license server manager (lmgrd) has not been started yet,the wrong port@host or license file is being used, or theport or hostname in the license file has been changed.Feature: SysGenServer name: 141.24.121.196License path: C:/.Xilinx\license.lic;C:/.Xilinx\Xilinx.lic;C:\Xi​linx\11.1\ISE/data\*.lic;C:\Xilinx\11.1\EDK/data/c​ore_licenses\apu_fpu_v2_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\apu_fpu_virtex5_v1_flexlm.l​ic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_atmc_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_atmc_v2_00_a_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\opb_can_v1_flexlm.lic;C:\Xi​linx\11.1\EDK/data/core_licenses\opb_ethernetlite_​v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_ethernetlite_v1_flexlm.lic;C:\Xilinx\11​.1\EDK/data/core_licenses\opb_ethernet_v1_00_j_fle​xlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_​ethernet_v1_00_k_flexlm.lic;C:\Xilinx\11.1\EDK/dat​a/core_licenses\opb_ethernet_v1_00_l_flexlm.lic;C:​\Xilinx\11.1\EDK/data/core_licenses\opb_ethernet_v​1_00_m_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_lic​enses\opb_ethernet_v1_01_a_flexlm.lic;C:\Xilinx\11​.1\EDK/data/core_licenses\opb_ethernet_v1_flexlm.l​ic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_hdlc_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_hdlc_v1_flexlm.lic;C:\Xilinx\11.1\EDK/d​ata/core_licenses\opb_hdlc_v2_00_a_flexlm.lic;C:\X​ilinx\11.1\EDK/data/core_licenses\opb_hdlc_v2_flex​lm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_i​ic_v1_01_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core​_licenses\opb_iic_v1_01_b_flexlm.lic;C:\Xilinx\11.​1\EDK/data/core_licenses\opb_iic_v1_flexlm.lic;C:\​Xilinx\11.1\EDK/data/core_licenses\opb_pci_v1_00_a​_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\​opb_pci_v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data​/core_licenses\opb_pci_v1_00_c_flexlm.lic;C:\Xilin​x\11.1\EDK/data/core_licenses\opb_pci_v1_flexlm.li​c;C:\Xilinx\11.1\EDK/data/core_licenses\opb_uart16​550_v1_00_c_flexlm.lic;C:\Xilinx\11.1\EDK/data/cor​e_licenses\opb_uart16550_v1_flexlm.lic;C:\Xilinx\1​1.1\EDK/data/core_licenses\opb_usb2_device_v1_flex​lm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\plbv4​6_pcie_v3_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_​licenses\plbv46_pci_v1_flexlm.lic;C:\Xilinx\11.1\E​DK/data/core_licenses\plb_atmc_v1_00_a_flexlm.lic;​C:\Xilinx\11.1\EDK/data/core_licenses\plb_ethernet​_v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_l​icenses\plb_ethernet_v1_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\plb_gemac_v1_00_a_flexlm.li​c;C:\Xilinx\11.1\EDK/data/core_licenses\plb_gemac_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\plb_gemac_v1_01_a_flexlm.lic;C:\Xilinx\11.1​\EDK/data/core_licenses\plb_gemac_v2_flexlm.lic;C:​\Xilinx\11.1\EDK/data/core_licenses\plb_pci_v1_fle​xlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\plb_​rapidio_lvds_v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK​/data/core_licenses\plb_rapidio_lvds_v1_flexlm.lic​;C:\Xilinx\11.1\EDK/data/core_licenses\plb_temac_v​1_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses​\plb_uart16550_v1_00_b_flexlm.lic;[...]FLEXnet Licensing error:-15,10. System Error: 10061 "WinSock:Connection refused"For further information, refer to the FLEXnet Licensing documentation,available at "www.acresso.com". ''

    Any ideas what might be the problem ?

    thanks in advance

    DB:2.82:Xilinx Ise Design Suite 11.1 Problem License c7


    Hi Enigmaice,

    Try running "xlcm" from command line and then click over to the Manage Xilinx Licenses tab after the GUI opens. This will get you to the place that "Manage Xilinx Licenses" is trying to get you to.

    Do you have a license already?

  • RELEVANCY SCORE 2.81

    DB:2.81:Failed To Read Dll File During Project-Generate_Netlist For New Xps-Bsb Build. Happens After Reinstalling Ise 11.4 And Multiple New Projects p3



    Hello,

    My XPS-BSB wizarddefines a netlist correctly, but when IGenerateNetlist I get the faileddll file access for an unknown reason (see error message below).I've spent 1/2 a day uninstalling and reinstalling my tools and I still get this error on any EDK netlist I generate. (I've done several.)

    ANY IDEAS???

    scott.kilcoyne@covidien.com

    ERROR MESSAGE

    ==========================

    Rebuilding cache ...

    Total run time: 834.00 seconds

    Running synthesis...

    bash -c "cd synthesis; ./synthesis.sh"

    xst -ifn system_xst.scr -intstyle silent

    Running XST synthesis ...

    dll open of library C:\Xilinx\11.1\ISE\lib\nt\libUtilC_MessageDispatcher.dll failed due to an unknown reason.

    make: *** [implementation/system.ngc] Error 1

    Done!

    ==========================







    Solved!
    Go to Solution.

    DB:2.81:Failed To Read Dll File During Project-Generate_Netlist For New Xps-Bsb Build. Happens After Reinstalling Ise 11.4 And Multiple New Projects p3


    Hi Felix,

    Thanks for the reply.

    I have a legacy ISE 9.2i version on my machine along with ISE 11.4.

    Chistophe@xilinx found the problem was a bad path.

    ===========================================
    Environment variable = PATH contains the string “C:\Xilinx92i\bin\nt;” //if this string is removed from the path the 11.4 XPS build completes without error. For me this was about 75% into a four line long path setting. All of the Xilinx 11.1/11.4 paths were in front of this path and have higher priority, but this did not prevent the problem. This explains why an uninstall and reinstall process did not fix the problem. Strangely enough, during our debug session Christophe and I found that running the ‘xst’ command (cut pasted from the log file) that fails in a DOS window works just fine, but when the command is run in the bash window it fails (EDK uses a bash window). Xilinx may want to add this to their user error knowledge database.

    ===========================================
    This solved the problem, which was that the ISE 11.4 synthesis (xst) called the ISE 9.2i libUtilC_MessageDispatcher.dll which is an old one. The error message was useless.Thanks for the effort. Scott Kilcoyne.

  • RELEVANCY SCORE 2.81

    DB:2.81:Problem Creating Xilkernel Bsp With Sdk 13.2 cd



    Hi every one,

    I am using SDK 13.2 running on a Windows XP machine trying to create Xilkernel board support package for the Digilent Atlys Board.

    When I convert my design to the SDK I always get these errors which are presented in the log file.

    My log file is:

    make -k all libgen -hw ../NEW_hw_platform/system.xml\ \ -pe microblaze_0 \ -log libgen.log \ system.msslibgenXilinx EDK 13.2 Build EDK_O.61xdCopyright (c) 1995-2011 Xilinx, Inc. All rights reserved.Command Line: libgen -hw ../NEW_hw_platform/system.xml -pe microblaze_0 -loglibgen.log system.mss Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.Compiling standaloneCompiling common/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [arch-libs] Error 258make[2]: Target `libs' not remade because of errors.make[1]: *** [dir_syscall] Error 2/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_arch] Error 258/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_sys] Error 258/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_ipc] Error 258make[2]: Target `all' not remade because of errors.make[1]: *** [dir_src] Error 2c:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt\bin\mb​-ar.exe: creating ./libsyscall.ac:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt\bin\mb​-ar.exe: ./syscall/arch/microblaze/*.o: Invalid argumentmake[1]: *** [rellibs] Error 1make[1]: Target `libs' not remade because of errors.Compiling emacliteCompiling uartliteCompiling spiCompiling bramCompiling tmrctrCompiling intcCompiling cpuERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [microblaze_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.

    By the way, I found this thread http://forums.xilinx.com/t5/EDK-and-Platform-Studi​o/Errors-making-bsp-when-following-UG670-EDK-13-1/​td-p/139950,

    But that doesn't solve my problem.

    I wonder would you mind please helping me out with this issue. Thanks a lot for reading my thread.

    DB:2.81:Problem Creating Xilkernel Bsp With Sdk 13.2 cd


    Were you able to resolve this problem? I am having the same problem, would really appreciate suggestions...

  • RELEVANCY SCORE 2.80

    DB:2.80:Libxikernel Compiler Error - Newbie c8



    I am getting errors trying to compile avery basicXikernel BSP project. No lwip or other optional components.

    Compiling a standalone BSP works/runs fine. I am new to the xilinx tools anytips appreciated.

    Thanks

    Bill Anderson

    I have

    ISE 14.3 I also get the same problem in 14.2

    Windows7 64bit

    cygWin installed

    The Console output follows.

    make -k all

    libgen -hw ../DLC610_Controller_hw_platform/system.xml\

    \

    -pe microblaze_0 \

    -log libgen.log \

    system.mss

    libgen

    Xilinx EDK 14.3 Build EDK_P.40xd

    Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../DLC610_Controller_hw_platform/system.xml -pe

    microblaze_0 -log libgen.log system.mss

     

    Staging source files.

    Running DRCs.

    Running generate.

    Running post_generate.

    Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"

    "COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift

    -mxl-pattern-compare -mhard-float -mcpu=v8.40.b -O2 -c"

    "EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"

    "COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift

    -mxl-pattern-compare -mhard-float -mcpu=v8.40.b -O2 -c"

    "EXTRA_COMPILER_FLAGS=-g"'.

    Compiling standalone

    Compiling common

    /bin/sh: -c: line 3: syntax error: unexpected end of file

    make[2]: *** [arch-libs] Error 258

    make[2]: Target `libs' not remade because of errors.

    make[1]: *** [dir_syscall] Error 2

    /bin/sh: -c: line 3: syntax error: unexpected end of file

    make[2]: *** [dir_arch] Error 258

    /bin/sh: -c: line 3: syntax error: unexpected end of file

    make[2]: *** [dir_sys] Error 258

    /bin/sh: -c: line 3: syntax error: unexpected end of file

    make[2]: *** [dir_ipc] Error 258

    make[2]: Target `all' not remade because of errors.

    make[1]: *** [dir_src] Error 2

    c:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt64\bin\mb-ar.exe: creating ./libsyscall.a

    c:\Xilinx\14.3\ISE_DS\EDK\gnu\microblaze\nt64\bin\mb-ar.exe: ./syscall/arch/microblaze/*.o: Invalid argument

    make[1]: *** [rellibs] Error 1

    make[1]: Target `libs' not remade because of errors.

    Compiling bram

    Compiling spi

    Compiling tmrctr

    Compiling uartlite

    Compiling iic

    Compiling gpio

    Compiling intc

    Compiling cpu

    ERROR:EDK:369 - make failed for target "libs"

    ERROR:EDK:3418 - Error(s) while running make.

    make: *** [microblaze_0/lib/libxil.a] Error 2

    make: Target `all' not remade because of errors.

    DB:2.80:Libxikernel Compiler Error - Newbie c8


    The syntax problem Iencountered is due to the SDK Make rulescalling the "sh" command when building on a Windows platform. It is not a conflict between sh versions as I have read elsewhere. It really is more of a bug in the make rules .

    Obviously a standard windows platform does not supply sh so I have no idea why the make rules try and call it. If Xilinx

    would fix this it would be a great help to those that have to use other SDKs on the same machine. To see if this is causing you similar problems. Open up a ISE Design Suite 64/32 Bit Command Prompt window and see if the sh comand is found. If it is you will need to modify your PATH environment varilable to avoid the SDK from finding it.After removing the other tools path was able to compile and the headache went away.

    C:\Xilinx\14.3\ISE_DSwhich sh

    which: no sh in (.;C:\Xilinx\Vivado_HLS\2012.3\bin;C:\Xilinx\14.3\ISE_DS\ISE\bin \nt64;C:\Xilinx\14.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.3\ISE_DS\ISE\..\..\..\DocN av;C:\Xilinx\Vivado\2012.3\bin;C:\Xilinx\14.3\ISE_DS\PlanAhead\bin;C:\Xilinx\14. 3\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.3\ISE_DS\E DK\gnu\microblaze\nt64\bin;C:\Xilinx\14.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C :\Xilinx\14.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt64\bin;C :\Xilinx\14.3\ISE_DS\common\bin\nt64;C:\Xilinx\14.3\ISE_DS\common\lib\nt64;C:\MC C18\mpasm;C:\MCC18\bin;C:\Program Files\Common Files\Microsoft Shared\Microsoft Online Services;C:\Program Files (x86)\Common Files\Microsoft Shared\Microsoft O nline Services;C:\Program Files\Common Files\Microsoft Shared\Windows Live;C:\Pr ogram Files (x86)\Common Files\Microsoft Shared\Windows Live;c:\Program Files (x 86)\Intel\iCLS Client\;c:\Program Files\Intel\iCLS Client\;C:\Program Files (x86 )\NVIDIA Corporation\PhysX\Common;C:\Windows\system32;C:\Windows;C:\Windows\Syst em32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Win dows Live\Shared;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Microch ip\MPLAB C32 Suite\bin;C:\MCC18\mpasm;C:\MCC18\bin)

    C:\Xilinx\14.3\ISE_DS

  • RELEVANCY SCORE 2.80

    DB:2.80:Can't Synthesize Microblaze System In Edk 14.2 zp



    I've tried this separately as an ISE project and later starting from PlanAhead. In both cases, generating the netlist fails with the first module (typically proc_sys_reset) in EDK. In Planahead, the following indescript error message is generated:

    [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [D:/Projects/ANL/V7_microblaze/planahead/planahead.srcs/sources_1/edk/microblaze/__xps/pa/_microblaze_synth.tcl

    Does anyone have an idea what this error message means?

    Thanks,

    Tony

    DB:2.80:Can't Synthesize Microblaze System In Edk 14.2 zp


    prateeks,

    No, i think you may have misunderstood. The file that you attached is the actual Tcl script that runs the synthesis on your project. You need to look at the results of the synthesis, in the Tcl Console. It will show you all notes, warnings, and errors generated during the synthesis of your project. You then need to scroll through to find what source file caused the script to exit with an error. Fix that source file.

  • RELEVANCY SCORE 2.79

    DB:2.79:Edk 14.4 ,Error In Sdk While Building Device Tree Bsp x9



    Can anybody help to resolve the below error

    ERROR:EDK - device-tree () - can't read "overrides": no such variable ERROR:EDK:3416 - Error(s) while running TCL procedure generate().make: *** [microblaze_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.

  • RELEVANCY SCORE 2.76

    DB:2.76:Xapp890 Systhesis Problem 88



    hi

    i use zedboard, when i follow xapp1167, encounter many problem.

    so, i follow xapp890, because the TRD had migrated to zedboard.

    when i open the project in thelogiREF-BTRD-14.3-ZED_130513.7z and sythesis, it turn up some problem.

    ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system_ps7_0_wrapper.ngc] 错误 2ERROR:EDK - Error while running "make -f system.make netlist".ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [E:/logiREF-BTRD-14.3-ZED_130513/hw/pa_proj/zynq_base_trd.srcs/sources_1/edk/xps_proj/__xps/pa/_system_synth.tcl]

    hope someone can help me.

    thanks!

    DB:2.76:Xapp890 Systhesis Problem 88

    From the error, it looks like that you are missing the libSecurity_FNP library. XAPP1167 requires Vivado 2013.2 - please use this version. If you want to use ISE, I would suggest that you use 14.6 version, since these libraries were included in the 14.6 install.

  • RELEVANCY SCORE 2.75

    DB:2.75:Error In Generating Programming File In Xilinx Edk j9


    I am working on Xilinx EDK, I created a project in xilinx ise, then added an embedded procesor using xps, but when I am trying to generate programming file , I get the following error.

    ERROR:EDK - INFO:Security:67 - XILINXD_LICENSE_FILE is set to '/opt/Xilinx/12.1/ISE_DS/EDK/data/core_licenses' in /home/h2o/.flexlmrc. INFO:Security:68 - Please run the Xilinx License Configuration Manager ERROR:Security:14 - No feature was available for 'XPS'.ERROR:EDK:440 - platgen failed with errors!ERROR:EDK - Error while running "gmake -f system.make netlist".ERROR: synthesizing XPS module failed!

    I have created an link to make for gmake already, and its there working successfully for sdk,

    h2o@h2o-Vostro-1015:~$ sudo ln -s /usr/bin/make /usr/bin/gmake[sudo] password for h2o: ln: failed to create symbolic link `/usr/bin/gmake': File exists

    how to resolve this error.

    also on the license front I am facing the problem, every time I open xps it shows me that license is not present and opens the xilinx license manager. I have registered at xilinx website and obtained the .lic license file, only few days ago.

    every time I open xps, I have to follow the same process of adding xilinx.lic file (see attachments)

    is this normal?










    Attachments:




    DB:2.75:Error In Generating Programming File In Xilinx Edk j9


    Hi,Are you targeting your design to Zynq devices?If yes, the license error is expected when using webpack license. See this answer record:http://www.xilinx.com/support/answers/51895.html

    This link provides you the supported tools with ISE webpack license:http://www.xilinx.com/products/design-tools/ise-design-suite/index.htm

    Thanks,

    Vinay




    --------------------------------------------------------------------------------------------Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

  • RELEVANCY SCORE 2.75

    DB:2.75:Edk Importing Hello World Problem mp



    Hello,

    First of all I should mention that I am a new user to the EDK so the problem is most likely something i've missed...

    I've created a very simple microblaze XPS project which contains only the core (microblaze, dlmb_cntlr, ilmb_cntr, lmb_bram and mdm) as well as an RS232 block. I can export this to the EDK quite nicely and create a software platform however when I try to add a "managed Make c application project" to this platform and select any of the predefined programs for instance "hello world" I get an error:

    "Failed to generate source files for project Hello world"

    has anyone any idea what this error could be? Ironically, I initially started out using the ISE to call the XPS to generate the microblaze, which after some initial playing with worked well. I wished to simplify things however due to an error but now I cant get this 'simplified version' working!

    Cheers

    Alan

    DB:2.75:Edk Importing Hello World Problem mp


    a_shippen

    I had the same problem. And it appeared that the problem was SDK did not like long paths. So, I moved my entire hw and sw project files to a shorter path, and re-exported hardware to SDK, and then I made the Hello World project, and everything worked fine (no fail message). So the solution is to simply move your project files to somewhere else with a shorter path and try it again. It should work

    aminfar

  • RELEVANCY SCORE 2.74

    DB:2.74:Errors Generated By Sdk Tool mk



    Hi friends;I'm working on Virtex-5 PPC440 using SDK tool.the system generate thesse errors below:----------------------------------make -k clean allrm -rf ppc440_0/code/rm -rf ppc440_0/include/rm -rf ppc440_0/lib/rm -rf ppc440_0/libsrc/rm -f libgen.loglibgen \-hw C:/LAHRACH/TP-PowerPC/PPCtest/SDK/SDK_Export/hw/system.xml \-pe ppc440_0 \-od . \-lp C:/LAHRACH/TP-PowerPC/PPCtest/SDK/SDK_Export \-log libgen.log testt.msslibgenXilinx EDK 11.4 Build EDK_LS4.68Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.Command Line: libgen -hwC:/LAHRACH/TP-PowerPC/PPCtest/SDK/SDK_Export/hw/system.xml -pe ppc440_0 -od .-lp C:/LAHRACH/TP-PowerPC/PPCtest/SDK/SDK_Export -log libgen.log testt.mssINFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: - LEDs_8Bit - RS232_Uart_1 - xps_bram_if_cntlr_1Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=powerpc-eabi-gcc""ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc""ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Compiling commonmake[1]: *** [libs] Error 57Compiling lldmamake[1]: *** [libs] Error 57Compiling standalonemake[1]: *** [standalone_libs] Error 57make[1]: Target `libs' not remade because of errors.Compiling gpiomake[1]: *** [libs] Error 57Compiling uartlitemake[1]: *** [libs] Error 57Compiling cpu_ppc440make[1]: *** [libs] Error 57ERROR:EDK:369 - make failed for target "libs"ERROR:EDK:1189 - Error(s) while running "make" for processor ppc440_0.make: *** [ppc440_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.-----------------------------Can you help to resolve this problemBest regards




    --------------------------PhD studentE-mail: f.lahrach@gmail.com

    DB:2.74:Errors Generated By Sdk Tool mk


    lahrach,

    Have you checked your permissions on this folder? It is possible that the driver files are not getting copied to the folder, or that they are unable to write to this folder ppc440_0/. Can you inspect this folder to confirm that the drivers are indeed getting copied?

    If its not a permission issue, it could also be a Cygwin issue. Do you have an independent version of Cygwin installed? Which version is being used by SDK?

  • RELEVANCY SCORE 2.74

    DB:2.74:Ise And Edk (Xps) fd



    I want to include a microblaze in my FPGA design, so I make the
    following steps when I create my ISE project: new source --
    Embedded Processor -- File name: Microblaze. But the following
    error appears:" Microblaze.xmp file:does not exist or cannot be opened
    for reading."

    Regards

    Garazi

    DB:2.74:Ise And Edk (Xps) fd


    Hello,

    Do you have EDK design built in the project location ? It looks you want to add a new XMP file to your project.

    You can refer to the procedure mentioned in the link http://www.xilinx.com/support/documentation/tutorials/EDK_92_MB_Tutorial.pdf

    Regards




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.74

    DB:2.74:How To Include Windows.H File In A Edk Software Project? kf



    I have seen some edk software c file include windows.h file,

    In my project, I tried to include the windows.h file but failed.

    the error message is : error: windows.h: No such file or directory.

    how to include windows.h file in a edk software project?

    DB:2.74:How To Include Windows.H File In A Edk Software Project? kf


    The windows.h file is a file specifically for the Windows API. Windows has not been ported to PPC nor MicroBlaze (and I seriously doubt that it will ever happen) so you will not be able to compile the code even with the windows.h file.

  • RELEVANCY SCORE 2.73

    DB:2.73:Edk: Generate Block Diagram Failed With Custom Ip Core 9j



    If i generate a block diagram in EDK with my custom ip cores the process failed. If i remove them from my design generating an block diagram works greate.

    ISE 13.2

    EDK 13.2

    DB:2.73:Edk: Generate Block Diagram Failed With Custom Ip Core 9j


    If i generate a block diagram in EDK with my custom ip cores the process failed. If i remove them from my design generating an block diagram works greate.

    ISE 13.2

    EDK 13.2

  • RELEVANCY SCORE 2.73

    DB:2.73:Synthesis.Cmd Not Found When Generating Netlist In Xps 7f



    I have a project in ISE (14.6) that i am adding a microblaze embedded processor. i configure the uB in xilinx platform studio (after it is launched from the ISE). In XPS i click Hardware Generate Netlist and XPS starts working away with the mhs file. at the end i get the following error:

    make -f blaze.make netlist started..."Running synthesis..."cd synthesis synthesis.cmdThe system cannot find the path specified.'synthesis.cmd' is not recognized as an internal or external command,operable program or batch file.make: *** [implementation/blaze.ngc] Error 1Done!

    i have a synthesis folder in the directory for the microblaze processor (C:\Xilinx\workspace\soc\t2\blaze\synthesis) so you can see there isn't any spaces in the path. there is a synthesis.cmd file in that directory as well. i can run the synthesis.cmd using my command line (i send the output to a text file) and i get this:

    "xst -ifn "ublaze_xst.scr" -intstyle silent""Running XST synthesis ...""XST completed"

    but when i go back to ISE and select the microblaze, then in the Processes window i expand the Design Utilities and double click View HDL Instantiation Template i get the following errors:

    Started : "XPS Process: View HDL Instantiation Template".Xilinx Platform StudioXilinx EDK 14.6 Build EDK_P.68dCopyright (c) 1995-2012 Xilinx, Inc. All rights reserved.XPS% Evaluating file C:\Xilinx\workspace\soc\t2\blaze.gentemplate.tclOverriding IP level properties ...INFO:EDK - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ENDIANNESS value to 1 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\microblaze_v8_50_b\d ata\microblaze_v2_1_0.mpd line 198 INFO:EDK - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ICACHE_USE_FSL value to 0 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\microblaze_v8_50_b\d ata\microblaze_v2_1_0.mpd line 339 INFO:EDK - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_DCACHE_USE_FSL value to 0 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\microblaze_v8_50_b\d ata\microblaze_v2_1_0.mpd line 369 INFO:EDK - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\axi_interconnect_v1_ 06_a\data\axi_interconnect_v2_1_0.mpd line 81 Computing clock values...INFO:EDK - Cannot determine the input clock associated with port : microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. INFO:EDK - Cannot determine the input clock associated with port : microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. Performing IP level DRCs on properties...Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...Address Map for Processor microblaze_0 (0000000000-0x00007fff) microblaze_0_d_bram_ctrl microblaze_0_dlmb (0000000000-0x00007fff) microblaze_0_i_bram_ctrl microblaze_0_ilmb (0x40000000-0x4000ffff) DIP_Switches axi4lite_0 (0x40600000-0x4060ffff) RS232 axi4lite_0 (0x41400000-0x4140ffff) debug_module axi4lite_0INFO:EDK - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\lmb_v10_v2_00_b\data \lmb_v10_v2_1_0.mpd line 82 INFO:EDK - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\lmb_v10_v2_00_b\data \lmb_v10_v2_1_0.mpd line 82 INFO:EDK - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is overriding PARAMETER C_MEMSIZE value to 0x8000 - C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\bram_block_v1_00_a\d ata\bram_block_v2_1_0.mpd line 78 Checking platform address map ...ERROR: failed to read blaze.mhs: No such file or directoryERROR:EDK - Error in running mhs2hdl.plERROR:EDK - Failed to generate HDL fileERROR: generating XPS instantiation template failed!ERROR: the hdl template for blaze.xmp could not be found. Make sure the XPS project is complete.Process "XPS Process: View HDL Instantiation Template" failed

    even though the blaze.mhs file is in the proper location (C:\Xilinx\workspace\soc\t2\blaze)

    I feel like this has something to do with paths. where are these path's configured and how can i change them??

    DB:2.73:Synthesis.Cmd Not Found When Generating Netlist In Xps 7f


    I continue to get errors about ISE not being able to mkdir for a few different folders. It was not able to make the bootloops folder when generating bitfile with my microblaze component. i also was not able to create the folders for launching SDK (the SDK directory in the microblaze folder in my project).

    where do these paths get set???

  • RELEVANCY SCORE 2.72

    DB:2.72:V_Tc Won't Build Under Edk 14.6 df



    when I include a video timing controller in a 14.6 project I get a completely non-descript set of errors (below). Has anyone been able to build v_tc in EDK 14.6? Seems to work build fine in 14.4

    ERROR:EDK:546 - Aborting XST flow execution!ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system.bmm] Error 2







    Solved!
    Go to Solution.

    DB:2.72:V_Tc Won't Build Under Edk 14.6 df


    build up a project in 14.4 and then upgrade it to 14.7. Odd workaround, but it does the trick.

  • RELEVANCY SCORE 2.72

    DB:2.72:Error While Building Software Applications In Xps 12.1 8f



    Hi,

    When i try to build any application in XPS12.1 i am having the below compilation errors. I think its smthing related to the compilation of the libraries. Any idea how to resolve this issue ?

    Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc""ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Compiling commonmake[1]: *** [libs] Error 127Compiling lldmamake[1]: *** [libs] Error 127Compiling standaloneCompiling uartlitemake[1]: *** [standalone_libs] Error 127make[1]: *** [libs] Error 127Compiling intcCompiling cpu_ppc440make[1]: *** [libs] Error 127ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make[1]: *** [libs] Error 127make: *** [ppc440_0/lib/libxil.a] Error 2Done!

    Vineeth

    DB:2.72:Error While Building Software Applications In Xps 12.1 8f


    Also wait for resolutions for it.........

    Best regards.

    Mica Gordon

  • RELEVANCY SCORE 2.72

    DB:2.72:Simulation Error With Modelsim Se 6.3f am



    I'm having some problems compiling the system with EDK 10.1. Can someone tell me if I made a simple mistake?

    thanks.

    # -- Compiling entity or_gate# -- Compiling architecture imp of or_gate# ** Error: (vcom-11) Could not find proc_common_v2_00_a.or_muxcy_f.# ** Error: /opt/xilinx_lcl/10.1/EDK/hw/XilinxProcessorIPLib/p​cores/plb_v46_v1_03_a/hdl/vhdl/or_gate.vhd(134): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.or_muxcy_f".# ** Error: /opt/xilinx_lcl/10.1/EDK/hw/XilinxProcessorIPLib/p​cores/plb_v46_v1_03_a/hdl/vhdl/or_gate.vhd(134): Unknown expanded name.# ** Error: /opt/xilinx_lcl/10.1/EDK/hw/XilinxProcessorIPLib/p​cores/plb_v46_v1_03_a/hdl/vhdl/or_gate.vhd(147): VHDL Compiler exiting# ** Error: /home/msl_av/ce/fpga/modelsim/modeltech/linux/vcom failed.# Error in macro ./system.do line 49# /home/msl_av/ce/fpga/modelsim/modeltech/linux/vcom failed.# while executing# "vcom -novopt -93 -work plb_v46_v1_03_a "/opt/xilinx_lcl/10.1/EDK/hw/XilinxProcessorIPLib/​pcores/plb_v46_v1_03_a/hdl/vhdl/or_gate.vhd""# 1

    DB:2.72:Simulation Error With Modelsim Se 6.3f am

    Did you run compxlib?compxlib needs to be run before compedklib, after running compxlib you need to point ncsim to the unisim, simprim, etc libraries. I know Modelsim uses the ini file, I am not sure how ncsim does it...

  • RELEVANCY SCORE 2.71

    DB:2.71:Build Error Or Sdk Not Finding Tools sd



    Hi all,

    I have been struggling with a build error shown below. I have been thru the forums and answers and tried to make sure I have eliminated the obvious but I am still missing something and was hoping someone could spot it for me.

    Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"

    "COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift

    -mxl-pattern-compare -mcpu=v8.00.b -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.

    Compiling common

    make[1]: *** [libs] Error 127

    Compiling llfifo

    make[1]: *** [libs] Error 127

    Compiling standalone

    make[1]: *** [standalone_libs] Error 127

    make[1]: Target `libs' not remade because of errors.

    Compiling axidma

    make[1]: *** [libs] Error 127

    Compiling gpio

    make[1]: *** [libs] Error 127

    ...

    Compiling axiethernet

    make[1]: *** [libs] Error 127

    Compiling cpu

    make[1]: *** [libs] Error 127

    ERROR:EDK:369 - make failed for target "libs"

    ERROR:EDK:3418 - Error(s) while running make.

    make: *** [microblaze_0/lib/libxil.a] Error 2

    make: Target `all' not remade because of errors.

    I am trying to build a BSP from within the SDK using the SP605 Embedded Kit tutorial projects downloaded from Xilinx. The project also fails to compile the "hello_world" default Cproject but I assume the errors are the same and for some reason the tools either can't be found or are missing.

    I have tried (re)installing 12.4 several times but no change in results. I am running the SDK from the proper shortcut so I believe the correct settings32.bat file is being executed and the proper environment variables exist but not sure how to validate. The following is the path that is given when the XInfoSystem Checkeris executed:

    Path: C:\Xilinx\12.4\ISE_DS\common\\lib\nt;C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;C:\Xilinx\12.4\ISE_DS\common\\bin\nt;C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;C:\Xilinx\12.4\ISE_DS\common\bin\nt;C:\Xilinx\12.4\ISE_DS\common\lib\nt;C:\Program Files\Common Files\Microsoft Shared\Windows;C:\Program Files\Windows Live\Shared;C:\Program Files\CMake 2.8\bin;C:\Program Files\msm2msi

    Two of the above path lines have double slashes "\\" and was not sure if that created an issue or not.

    Thanks in advance,

    Mike







    Solved!
    Go to Solution.

    DB:2.71:Build Error Or Sdk Not Finding Tools sd


    vsiva -

    Thanks for the advice and you figured correctly. It was an older version of the cygwin.dll that was in my system folder from another application that was creating the problem. Once I deleted it and rebooted - everything worked properly.

    I am new to the toolset and was not familar with building/compiling via command shell so in doing some further research on the forums Iturned up other responses regarding multiple versions of cygwin running. Which lead me to do a search on my computer.

    As a follow up question could you point me to some tutorials/guides for building projects via the shell. I think it would be nice to have that capability.

    Thanks again,

    Mike

  • RELEVANCY SCORE 2.70

    DB:2.70:Jtag Adapter Ulink-Me And Openocd mp



    I installed Openocd from opfficial repositories today and am now trying to use it with my JTAG adapter ULINK-ME. I found out that ULINK-ME uses CMSIS-DAP debugging firmware. Openocd has CMSIS-DAP drivers and should therefore be able to communicate with my adapter but after I wrote the command below I got an error. I am connecting ULINK-ME to the board EA3141 which integrates microcontroller LPC3141 - a close relative to LPC3131 for whom I load the configuration file.
    sudo openocd -f /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg -f /usr/local/share/openocd/scripts/target/lpc3131.cfg -d3

    Open On-Chip Debugger 0.8.0-dev-00175-g8b7acca-dirty (2014-10-14-19:53)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
    User : 13 1 command.c:549 command_print(): debug_level: 3
    Debug: 14 1 configuration.c:45 add_script_search_dir(): adding /root/.openocd
    Debug: 15 1 configuration.c:45 add_script_search_dir(): adding /usr/local/share/openocd/site
    Debug: 16 1 configuration.c:45 add_script_search_dir(): adding /usr/local/share/openocd/scripts
    Debug: 17 1 configuration.c:86 find_file(): found /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg
    Debug: 18 1 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_interface cmsis-dap
    Debug: 19 2 command.c:145 script_debug(): command - interface ocd_interface cmsis-dap
    Debug: 21 2 command.c:369 register_command_handler(): registering ocd_cmsis-dap...
    Debug: 22 2 command.c:369 register_command_handler(): registering ocd_cmsis_dap_vid_pid...
    Debug: 23 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 24 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 25 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 26 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 27 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 28 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 29 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 30 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 31 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Info : 32 2 transport.c:118 allow_transports(): only one transport option; autoselect cmsis-dap
    Debug: 33 2 adi_v5_cmsis_dap.c:246 cmsis_dap_select(): CMSIS-ADI: cmsis_dap_select
    Debug: 34 2 command.c:404 register_command(): command cmsis-dap is already registered in global context
    Debug: 35 2 command.c:369 register_command_handler(): registering ocd_cmsis-dap...
    Error: 36 7 cmsis_dap_usb.c:175 cmsis_dap_usb_open(): unable to open CMSIS-DAP device
    Error: 37 7 adi_v5_cmsis_dap.c:266 cmsis_dap_select(): unable to init CMSIS-DAP driver
    Error: 38 7 transport.c:83 transport_select(): Error selecting cmsis-dap as transport
    Debug: 39 7 command.c:631 run_command(): Command failed with error code -4
    User : 40 7 command.c:669 command_run_line(): Runtime Error: /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg:7:
    in procedure script
    at file embedded:startup.tcl, line 58
    in procedure interface called at file /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg, line 7

    DB:2.70:Jtag Adapter Ulink-Me And Openocd mp


    I installed Openocd from opfficial repositories today and am now trying to use it with my JTAG adapter ULINK-ME. I found out that ULINK-ME uses CMSIS-DAP debugging firmware. Openocd has CMSIS-DAP drivers and should therefore be able to communicate with my adapter but after I wrote the command below I got an error. I am connecting ULINK-ME to the board EA3141 which integrates microcontroller LPC3141 - a close relative to LPC3131 for whom I load the configuration file.
    sudo openocd -f /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg -f /usr/local/share/openocd/scripts/target/lpc3131.cfg -d3

    Open On-Chip Debugger 0.8.0-dev-00175-g8b7acca-dirty (2014-10-14-19:53)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
    User : 13 1 command.c:549 command_print(): debug_level: 3
    Debug: 14 1 configuration.c:45 add_script_search_dir(): adding /root/.openocd
    Debug: 15 1 configuration.c:45 add_script_search_dir(): adding /usr/local/share/openocd/site
    Debug: 16 1 configuration.c:45 add_script_search_dir(): adding /usr/local/share/openocd/scripts
    Debug: 17 1 configuration.c:86 find_file(): found /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg
    Debug: 18 1 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_interface cmsis-dap
    Debug: 19 2 command.c:145 script_debug(): command - interface ocd_interface cmsis-dap
    Debug: 21 2 command.c:369 register_command_handler(): registering ocd_cmsis-dap...
    Debug: 22 2 command.c:369 register_command_handler(): registering ocd_cmsis_dap_vid_pid...
    Debug: 23 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 24 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 25 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 26 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 27 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 28 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 29 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 30 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Debug: 31 2 command.c:369 register_command_handler(): registering ocd_jtag...
    Info : 32 2 transport.c:118 allow_transports(): only one transport option; autoselect cmsis-dap
    Debug: 33 2 adi_v5_cmsis_dap.c:246 cmsis_dap_select(): CMSIS-ADI: cmsis_dap_select
    Debug: 34 2 command.c:404 register_command(): command cmsis-dap is already registered in global context
    Debug: 35 2 command.c:369 register_command_handler(): registering ocd_cmsis-dap...
    Error: 36 7 cmsis_dap_usb.c:175 cmsis_dap_usb_open(): unable to open CMSIS-DAP device
    Error: 37 7 adi_v5_cmsis_dap.c:266 cmsis_dap_select(): unable to init CMSIS-DAP driver
    Error: 38 7 transport.c:83 transport_select(): Error selecting cmsis-dap as transport
    Debug: 39 7 command.c:631 run_command(): Command failed with error code -4
    User : 40 7 command.c:669 command_run_line(): Runtime Error: /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg:7:
    in procedure script
    at file embedded:startup.tcl, line 58
    in procedure interface called at file /usr/local/share/openocd/scripts/interface/cmsis-dap.cfg, line 7

  • RELEVANCY SCORE 2.70

    DB:2.70:Error Mdt Mhs No Driver Found pj


    Dear all,

    I'm a new learner of XPS. I try to use the Xilinx XUPV2P Virtex-II Pro FPGA board to design a sopc system. In my design, I use a bram to store the data that can be read and write by both of the software and hardware. As we all known, bram has a pair of ports, porta and portb, I connect porta to the bram controller port by the means of OPB bus, and connect portb to my ip. when I try to generate netlist , error occurs.

    Check port drivers...

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Rst_B CONNECTOR:BRAM_Rst_B -

    E:\EDK\Mtest\system.mhs line 145 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Rst CONNECTOR:BRAM_Rst_B -

    E:\EDK\Mtest\system.mhs line 175 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Clk_B CONNECTOR:BRAM_Clk_B -

    E:\EDK\Mtest\system.mhs line 146 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Clk CONNECTOR:BRAM_Clk_B -

    E:\EDK\Mtest\system.mhs line 176 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_EN_B CONNECTOR:BRAM_EN_B -

    E:\EDK\Mtest\system.mhs line 147 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_EN CONNECTOR:BRAM_EN_B -

    E:\EDK\Mtest\system.mhs line 177 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_WEN_B CONNECTOR:BRAM_WEN_B -

    E:\EDK\Mtest\system.mhs line 148 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_WEN CONNECTOR:BRAM_WEN_B -

    E:\EDK\Mtest\system.mhs line 178 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Addr_B CONNECTOR:BRAM_Addr_B

    - E:\EDK\Mtest\system.mhs line 149 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Addr CONNECTOR:BRAM_Addr_B -

    E:\EDK\Mtest\system.mhs line 179 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Dout_B CONNECTOR:BRAM_Dout_B

    - E:\EDK\Mtest\system.mhs line 150 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Dout CONNECTOR:BRAM_Dout_B -

    E:\EDK\Mtest\system.mhs line 180 - No driver found!

    WARNING:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Din_B CONNECTOR:BRAM_Din_B

    - E:\EDK\Mtest\system.mhs line 151 - floating connection!

    WARNING:MDT - INST:mem_read_write_0 PORT:BRAM_Din CONNECTOR:BRAM_Din_B -

    E:\EDK\Mtest\system.mhs line 181 - floating connection!

    WARNING:MDT - INST:dcm_0 PORT:LOCKED CONNECTOR:dcm_0_lock -

    E:\EDK\Mtest\system.mhs line 166 - floating connection!

    Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

    ERROR:MDT - platgen failed with errors!

    my related *.mhs files as follows:

    BEGIN opb_bram_if_cntlr

    PARAMETER INSTANCE = opb_bram_if_cntlr_1

    PARAMETER HW_VER = 1.00.a

    PARAMETER c_opb_clk_period_ps = 10000

    PARAMETER c_baseaddr = 0x73c10000

    PARAMETER c_highaddr = 0x73c1ffff

    BUS_INTERFACE SOPB = mb_opb

    BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port

    END

    BEGIN bram_block

    PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram

    PARAMETER HW_VER = 1.00.a

    BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port

    PORT BRAM_Rst_B = BRAM_Rst_B

    PORT BRAM_Clk_B = BRAM_Clk_B

    PORT BRAM_EN_B = BRAM_EN_B

    PORT BRAM_WEN_B = BRAM_WEN_B

    PORT BRAM_Addr_B = BRAM_Addr_B

    PORT BRAM_Dout_B = BRAM_Dout_B

    PORT BRAM_Din_B = BRAM_Din_B

    END

    BEGIN myip

    PARAMETER INSTANCE =myip

    PARAMETER HW_VER = 1.00.a

    PARAMETER C_BASEADDR = 0x73c00000

    PARAMETER C_HIGHADDR = 0x73c0ffff

    BUS_INTERFACE SOPB = mb_opb

    PORT BRAM_Rst = BRAM_Rst_B

    PORT BRAM_Clk = BRAM_Clk_B

    PORT BRAM_EN = BRAM_EN_B

    PORT BRAM_WEN = BRAM_WEN_B

    PORT BRAM_Addr = BRAM_Addr_B

    PORT BRAM_Dout = BRAM_Dout_B

    PORT BRAM_Din = BRAM_Din_B

    END

    thanks to your advice.

    DB:2.70:Error Mdt Mhs No Driver Found pj

    Dear all,

    I'm a new learner of XPS. I try to use the Xilinx XUPV2P Virtex-II Pro FPGA board to design a sopc system. In my design, I use a bram to store the data that can be read and write by both of the software and hardware. As we all known, bram has a pair of ports, porta and portb, I connect porta to the bram controller port by the means of OPB bus, and connect portb to my ip. when I try to generate netlist , error occurs.

    Check port drivers...

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Rst_B CONNECTOR:BRAM_Rst_B -

    E:\EDK\Mtest\system.mhs line 145 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Rst CONNECTOR:BRAM_Rst_B -

    E:\EDK\Mtest\system.mhs line 175 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Clk_B CONNECTOR:BRAM_Clk_B -

    E:\EDK\Mtest\system.mhs line 146 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Clk CONNECTOR:BRAM_Clk_B -

    E:\EDK\Mtest\system.mhs line 176 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_EN_B CONNECTOR:BRAM_EN_B -

    E:\EDK\Mtest\system.mhs line 147 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_EN CONNECTOR:BRAM_EN_B -

    E:\EDK\Mtest\system.mhs line 177 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_WEN_B CONNECTOR:BRAM_WEN_B -

    E:\EDK\Mtest\system.mhs line 148 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_WEN CONNECTOR:BRAM_WEN_B -

    E:\EDK\Mtest\system.mhs line 178 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Addr_B CONNECTOR:BRAM_Addr_B

    - E:\EDK\Mtest\system.mhs line 149 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Addr CONNECTOR:BRAM_Addr_B -

    E:\EDK\Mtest\system.mhs line 179 - No driver found!

    ERROR:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Dout_B CONNECTOR:BRAM_Dout_B

    - E:\EDK\Mtest\system.mhs line 150 - No driver found!

    ERROR:MDT - INST:mem_read_write_0 PORT:BRAM_Dout CONNECTOR:BRAM_Dout_B -

    E:\EDK\Mtest\system.mhs line 180 - No driver found!

    WARNING:MDT - INST:opb_bram_if_cntlr_1_bram PORT:BRAM_Din_B CONNECTOR:BRAM_Din_B

    - E:\EDK\Mtest\system.mhs line 151 - floating connection!

    WARNING:MDT - INST:mem_read_write_0 PORT:BRAM_Din CONNECTOR:BRAM_Din_B -

    E:\EDK\Mtest\system.mhs line 181 - floating connection!

    WARNING:MDT - INST:dcm_0 PORT:LOCKED CONNECTOR:dcm_0_lock -

    E:\EDK\Mtest\system.mhs line 166 - floating connection!

    Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

    ERROR:MDT - platgen failed with errors!

    my related *.mhs files as follows:

    BEGIN opb_bram_if_cntlr

    PARAMETER INSTANCE = opb_bram_if_cntlr_1

    PARAMETER HW_VER = 1.00.a

    PARAMETER c_opb_clk_period_ps = 10000

    PARAMETER c_baseaddr = 0x73c10000

    PARAMETER c_highaddr = 0x73c1ffff

    BUS_INTERFACE SOPB = mb_opb

    BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port

    END

    BEGIN bram_block

    PARAMETER INSTANCE = opb_bram_if_cntlr_1_bram

    PARAMETER HW_VER = 1.00.a

    BUS_INTERFACE PORTA = opb_bram_if_cntlr_1_port

    PORT BRAM_Rst_B = BRAM_Rst_B

    PORT BRAM_Clk_B = BRAM_Clk_B

    PORT BRAM_EN_B = BRAM_EN_B

    PORT BRAM_WEN_B = BRAM_WEN_B

    PORT BRAM_Addr_B = BRAM_Addr_B

    PORT BRAM_Dout_B = BRAM_Dout_B

    PORT BRAM_Din_B = BRAM_Din_B

    END

    BEGIN myip

    PARAMETER INSTANCE =myip

    PARAMETER HW_VER = 1.00.a

    PARAMETER C_BASEADDR = 0x73c00000

    PARAMETER C_HIGHADDR = 0x73c0ffff

    BUS_INTERFACE SOPB = mb_opb

    PORT BRAM_Rst = BRAM_Rst_B

    PORT BRAM_Clk = BRAM_Clk_B

    PORT BRAM_EN = BRAM_EN_B

    PORT BRAM_WEN = BRAM_WEN_B

    PORT BRAM_Addr = BRAM_Addr_B

    PORT BRAM_Dout = BRAM_Dout_B

    PORT BRAM_Din = BRAM_Din_B

    END

    thanks to your advice.

  • RELEVANCY SCORE 2.70

    DB:2.70:Edk 13.1 Can't Find Proc_Common_V_3_00_A j7


    Hi, I have a design that is DRC-compilant and I get the following error when trying to generate netlist
    ERROR:HDLParsers:3317 - "C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" Line 114. Library proc_common_v3_00_a cannot be found.
    ERROR:HDLParsers:3014 - "C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" Line 115. Library unit proc_common_v3_00_a is not available in library plbv46_slave_burst_v1_01_a.
    ERROR:EDK:546 - Aborting XST flow execution!
    ERROR:EDK:440 - platgen failed with errors!
    make: *** [implementation/olympus_plb_0_wrapper.ngc] Error 2

    ERROR:HDLParsers:3317 - "C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" Line 114. Library proc_common_v3_00_a cannot be found.ERROR:HDLParsers:3014 - "C:/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" Line 115. Library unit proc_common_v3_00_a is not available in library plbv46_slave_burst_v1_01_a.ERROR:EDK:546 - Aborting XST flow execution!ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/olympus_plb_0_wrapper.ngc] Error 2

    The thing is, the block in error is a PCI core from Xilinx and not a user-logic block. I would expect it to work "as is". Are there any options I could set to make this problem go away?

    Best regards







    Solved!
    Go to Solution.

    DB:2.70:Edk 13.1 Can't Find Proc_Common_V_3_00_A j7


    Thanks for that. I've now changed all refs to 'proc_common_v_2_00_a' in my ip cores (pao and vhd files) to 'proc_common_v_3_00_a' and can now build my netlist :-)

  • RELEVANCY SCORE 2.69

    DB:2.69:Error:Edk:440 - Platgen Failed With Errors! 99



    Hi world,

    when I generate bitstream on XPS, I make errors:

    ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/system.bmm] Error 2

    I attach a file that include errors I make

    Please help me!










    Attachments:







    errors.txt ‏13 KB

    DB:2.69:Error:Edk:440 - Platgen Failed With Errors! 99


    I shall assume that you have read the error messages and are not quite sure what they mean. The crucial lines appear to be:

    ERROR:EDK:4073 - INSTANCE: LEDS, PORT: GPIO_IO_O, CONNECTOR: LEDS_TRI_O - 8bit-width connector assigned to 32 bit-width port - D:\projectEDK\bai3\system.mhs line 215

    ERROR:EDK:4073 - INSTANCE: DIP_Switches, PORT: GPIO_IO_I, CONNECTOR: DIP_Switches_TRI_I - 8 bit-width connector assigned to 32 bit-width port - D:\projectEDK\bai3\system.mhs line 229

    So, looking at your system.mhs at lines 215 and 229, your appear to a have a port width mismatch. That is, you are trying to assign an 8 bit connector to a 32 bit port. The widths need to match.

    Regards,

    Howard




    ----------"That which we must learn to do, we learn by doing." - Aristotle

  • RELEVANCY SCORE 2.69

    DB:2.69:Kde Installation Error Xapian-Core 91



    While trying to download and install KDE, this error gets thrown up :
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.learn.ac.lk : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.cse.iitk.ac.in : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.de.leaseweb.net : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.us.leaseweb.net : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from archlinux.polymorf.fr : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.nl.leaseweb.net : The requested URL returned error: 404 Not Found
    error: failed retrieving file xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz from mirror.chmuri.net : Resolving timed out after 10521 milliseconds
    (369/369) checking keys in keyring [######################] 100%
    (369/369) checking package integrity [######################] 100%
    error: xapian-core: signature from Andrea Scarpino (Arch Linux) andrea@archlinux.org is invalid
    :: File /var/cache/pacman/pkg/xapian-core-1:1.2.17-2-x86_64.pkg.tar.xz is corrupted (invalid or corrupted package (PGP signature)).
    Do you want to delete it? [Y/n] n
    error: failed to commit transaction (invalid or corrupted package)
    Errors occurred, no packages were upgraded.

    DB:2.69:Kde Installation Error Xapian-Core 91

    gvenkat1994 wrote:
    I had updated my repos only a day before

  • RELEVANCY SCORE 2.69

    DB:2.69:Getting Errors While Building Software Project 3k



    Hi all,

    i am getting the errors in EDK while building the project,

    mb-gcc -O2 src/main.c -o ml507_sw/executable.elf \
    -mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.00.a -g -I./microblaze_0/include/ -Isrc/ -L./microblaze_0/lib/ \

    /cygdrive/c/DOCUME~1/vinodk/LOCALS~1/Temp/ccWbtU4l.o: In function `XHwIcap_ReadHeader':
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:159: undefined reference to `sysace_fopen'
    /cygdrive/c/DOCUME~1/vinodk/LOCALS~1/Temp/ccWbtU4l.o: In function `XHwIcap_CF2Icap':
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:180: undefined reference to `sysace_fread'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:180: undefined reference to `sysace_fclose'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:190: undefined reference to `sysace_fopen'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:202: undefined reference to `sysace_fread'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:205: undefined reference to `sysace_fread'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:253: undefined reference to `sysace_fread'
    /cygdrive/d/PR/Ref_design/Colors/backup/Colors/EDK/src/main.c:253: undefined reference to `sysace_fclose'
    collect2: ld returned 1 exit status
    make: *** [ml507_sw/executable.elf] Error 1

    Done!

    I have mentioned all the Headers files correctly.

    I have attached my .c file also u check that once pls

    can any1 help me in this issue







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.69

    DB:2.69:Error Occured While Creating A Custom Ip Using Edk 10.1 Tools -Reg m3



    Dear Sir,

    I am srinivas,working with EDK10.1 Tools to design a
    custom based IP to my board ML501.I have created my IP and interface my IP to PLBV46_Slave(SPLB) using XPS 10.1
    (Create or Import Pheriperal) sucessfully.After that I added my IP to my
    project.But When I was trying to Generate bitstreem for my project I
    got the following error.

    ERROR MDT-

    F:\xillinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_03_adata\plb_v46_v2_1_0.mpd
    line 34 PARAMETER C_PLB46_NUM_MASTERS has value 0 which doesn't fall in
    the range (1:16) specified in MPD

    ERROR MDT - platgen failed with errors!

    My EDK Tools loaded in F drive.

    I am new to these tools,I will be very gracefull to you if get any solution for my problem.

    thanks in advance

    Regards,

    Srinivas

    DB:2.69:Error Occured While Creating A Custom Ip Using Edk 10.1 Tools -Reg m3


    I haven't seen this error before...

    Did you build your processor subsystem with BSB? Did it build successfully before your added your custom IP?

    Did you change the default parameters in the mhs file?

    I would have expected something simple like this for the processor and bus in the mhs:

    /*

    BEGIN microblazePARAMETER INSTANCE = microblaze_0PARAMETER C_INTERCONNECT = 1PARAMETER HW_VER = 7.10.dPARAMETER C_DEBUG_ENABLED = 1BUS_INTERFACE DLMB = dlmbBUS_INTERFACE ILMB = ilmbBUS_INTERFACE DPLB = mb_plbBUS_INTERFACE IPLB = mb_plbBUS_INTERFACE DEBUG = microblaze_0_dbgPORT MB_RESET = mb_resetEND

    BEGIN plb_v46PARAMETER INSTANCE = mb_plbPARAMETER HW_VER = 1.03.aPORT PLB_Clk = sys_clk_sPORT SYS_Rst = sys_bus_resetEND

    */

  • RELEVANCY SCORE 2.69

    DB:2.69:Error In Edk xa



    Compiling gamma_plbwgamma_plbw_g.c:48: error: 'XPAR_VIDEO_TO_VFBC_0_BASEADDR' undeclared here (not in a function)make[1]: *** [libs] Error 1Compiling mpmcCompiling cpuERROR:MDT - make failed for target "libs" ERROR:MDT - Error while running "make" for processor microblaze_0...make: *** [microblaze_0/lib/libxil.a] Error 2Done!

    i work with spatan3 Video Starter kit

    when I try to "build project" in EDK

    the above message has show up

    Help me please.

    DB:2.69:Error In Edk xa


    Try to clean all generated files then generate adressesand generate simulation files, may be u added a newIP and its not yet included in xparameters.

    -----

    K.Tahraoui




    ----------Khlitoshi

  • RELEVANCY SCORE 2.68

    DB:2.68:Problem Mpmc Instance 8z



    Hi,

    I'm new to EDK and I'm trying to use a project that was created with 10.1, and was working fine. After an ISE update we had to recreate the project ( and update peripherals).

    When trying to generate a netlist with EDK we've got this error.

    ERROR:EDK:3900 - issued from TCL procedure "init_control" line 69 C_NCK_PER_CLK (IPNAME:mpmc, INSTANCE:DDR2_SDRAM) - File E:/Workspace/test_xps/test4/__xps/DDR2_SDRAM_ctrl_path_params.v is not found or unable to open for reading. ERROR:EDK - IPNAME: mpmc, INSTANCE: DDR2_SDRAM - error computing override value for C_NCK_PER_CLK using tcl - C:\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v6_03_a\data\mp mc_v2_1_0.mpd line 756 ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/ppc440_0_wrapper.ngc] Erreur 2

    We found the DDR2_SDRAM_ctrl_path_params.v file and it looks fine.

    2. When creating a new peripheral we don't see its ports in the Port tab.

    Thanks for help

    CC

    ISE 13.1

    VirtualBox

    MAC os X host

    Windows XP guest

    DB:2.68:Problem Mpmc Instance 8z


    well, on my side the error happened in platgen if the prvious run of synthesys was done with that option....

  • RELEVANCY SCORE 2.68

    DB:2.68:Edk Commands For Make The System.Make In Cmd js



    I generate a project of EDK, and I want to make its system.make in cmd commands without opening the EDK operation window. How to set the make.cmd file?

    DB:2.68:Edk Commands For Make The System.Make In Cmd js


    Hi, stutongqi

    I tryied under the cmdby steps:

    cd C;/xilinx/11.1/edk/cygwin/bin

    xbash

    $cd D;/v5/testmake

    $make -f system.make bits

    it worked well;

    but how to merge them into one cmd without stop; I tried some "xbash -c cd D;/v5/testmake"

    it was wrong commands.

  • RELEVANCY SCORE 2.68

    DB:2.68:Error:Mdt - Signal:Dbg_Tdo - Multiple Drivers Found: sz



    Hi, I'm trying to create a dual Mircoblaze processor system with XMD debug. I got the following error when i try to generate the bitstream.

    Check port drivers...ERROR:MDT - SIGNAL:Dbg_TDO - multiple drivers found: INST:microblaze_0 PORT:DBG_TDO CONNECTOR:Dbg_TDO - C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v6_00_b\data\microblaze_v2_1 _0.mpd line 171! INST:microblaze_1 PORT:DBG_TDO CONNECTOR:Dbg_TDO - C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v6_00_b\data\microblaze_v2_1 _0.mpd line 171!

    Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...ERROR:MDT - platgen failed with errors!

    make: *** [implementation/microblaze_0_wrapper.ngc] Error 2

    I have created additional LMB for the second processor and link them up accordingly.

    Anyone came across this problem before?

    Thank you!

    Dexter

    DB:2.68:Error:Mdt - Signal:Dbg_Tdo - Multiple Drivers Found: sz


    I am sorry,I ignore “PORT xps_epc_0_PRH_Data_I_pin = xps_epc_0_PRH_Data_I, DIR = I, VEC = [0:31]”,changeDIR=O,success.

    Thanks!

  • RELEVANCY SCORE 2.68

    DB:2.68:Libgen Fails At Make Stage (Cant Execute Rm -Rf *.O) 14.2 k7



    Hello. Using EDK 14.2

    Trying to run libgen with my bsp. Makefile generated by libgen does not work!

    libgen run so:

    libgen -hw SDK\gd_ppc_hw_platform\system.xml -lp . -log bsp\libgen.log bsp\system.mss

    post_generate stage passes and make running

    c:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin\rm.exe: unable execute lstat for '*.o'': Invalid argument

    make: *** [clean] Error 1Compiling gpioCompiling spiCompiling intcCompiling uartliteCompiling bramCompiling iicCompiling lltemacxlltemac.c: In function 'XLlTemac_CfgInitialize':xlltemac.c:127: warning: incompatible implicit declaration of built-in function'memset'xlltemac.c:128: warning: incompatible implicit declaration of built-in function'memcpy'Compiling sysaceCompiling tmrctrCompiling cpu_ppc440ERROR:EDK:369 - make failed for target "libs"ERROR:EDK:3418 - Error(s) while running make.

    Your new rm does not work with rm -f *.o if there are not *.o files in remove path. This makefile generated automatically by libgen so I cant change command. What can I do?

    Thank you.

    DB:2.68:Libgen Fails At Make Stage (Cant Execute Rm -Rf *.O) 14.2 k7


    Hello. Using EDK 14.2

    Trying to run libgen with my bsp. Makefile generated by libgen does not work!

    libgen run so:

    libgen -hw SDK\gd_ppc_hw_platform\system.xml -lp . -log bsp\libgen.log bsp\system.mss

    post_generate stage passes and make running

    c:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin\rm.exe: unable execute lstat for '*.o'': Invalid argument

    make: *** [clean] Error 1Compiling gpioCompiling spiCompiling intcCompiling uartliteCompiling bramCompiling iicCompiling lltemacxlltemac.c: In function 'XLlTemac_CfgInitialize':xlltemac.c:127: warning: incompatible implicit declaration of built-in function'memset'xlltemac.c:128: warning: incompatible implicit declaration of built-in function'memcpy'Compiling sysaceCompiling tmrctrCompiling cpu_ppc440ERROR:EDK:369 - make failed for target "libs"ERROR:EDK:3418 - Error(s) while running make.

    Your new rm does not work with rm -f *.o if there are not *.o files in remove path. This makefile generated automatically by libgen so I cant change command. What can I do?

    Thank you.

  • RELEVANCY SCORE 2.68

    DB:2.68:Warnings In Mui Logs z9



    Any idea what would be causing these error messages in the Log files in the MUI? This is a 2.5.2 ESX Server. Thanks.

    Aug 17 08:23:33 USMGHAPPS075 vmkernel: 0:22:45:22.212 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.918 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:14

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.919 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:15

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.920 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:16

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.921 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:17

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.922 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:18

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.923 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:19

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.924 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:20

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.925 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:21

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.926 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:22

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.928 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:0:24

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.932 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:1:4

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.947 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:1:26

    Aug 17 09:34:45 USMGHAPPS075 vmkernel: 0:00:00:41.949 cpu2)WARNING: LinSCSI: 389: SCSI MODE SENSE command failed with status = I/O error for vmhba2:1:27

    Aug 17 09:55:17 USMGHAPPS075 vmkernel: 0:00:21:25.494 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:17 USMGHAPPS075 vmkernel: 0:00:21:25.877 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:17 USMGHAPPS075 vmkernel: 0:00:21:25.950 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.333 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.426 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.528 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.642 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.728 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    Aug 17 09:55:18 USMGHAPPS075 vmkernel: 0:00:21:26.820 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    DB:2.68:Warnings In Mui Logs z9


    http://www.vmware.com/community/thread.jspa?threadID=37863tstart=0

  • RELEVANCY SCORE 2.68

    DB:2.68:Error While Generating Libraries And Bsp's In Edk 1j



    hieee everyone,

    I am using edk and using spartan 3e board and edk 11.1 ..but while i am generating libraries and bsp's , i am getting the error

    "ERROR:EDK:1860 - Must specify -inp file

    ERROR:EDK:1802

    ERROR:EDK:756 - Cannot read XML file E:/EDK Lab/lab2//__xps/system.xml

    ERROR:EDK:2630 - Unable to read the hardware specification file: E:/EDK

    make: *** [microblaze_0/lib/libxil.a] Error 2

    I am sure that path do not contain any spaces. but i am getting this error...

    plz help..thanx

    DB:2.68:Error While Generating Libraries And Bsp's In Edk 1j


    hieee everyone,

    I am using edk and using spartan 3e board and edk 11.1 ..but while i am generating libraries and bsp's , i am getting the error

    "ERROR:EDK:1860 - Must specify -inp file

    ERROR:EDK:1802

    ERROR:EDK:756 - Cannot read XML file E:/EDK Lab/lab2//__xps/system.xml

    ERROR:EDK:2630 - Unable to read the hardware specification file: E:/EDK

    make: *** [microblaze_0/lib/libxil.a] Error 2

    I am sure that path do not contain any spaces. but i am getting this error...

    plz help..thanx

  • RELEVANCY SCORE 2.67

    DB:2.67:Opensparct1 On Virtex-7 dd



    Hi, I am trying to implement OpenSPARCT1 on Xilinx Virtex-7(VC707 XC7VX485T-2FFG1761CES Evaluation Board), single core and multi core. I first tried the EDK project on Virtex-5 and now I want to check feasibility of implementation of the same on Virtex-7. But I am facing a few problems as below: 1. Generating NGC netlist for Virtex-7 - For rxil command, the OpenSPARCT1 package does not contain the .xst file for my Virtex-7 device. How can I create one or modify the others for my FPGA? Also I tried creating a project on ISE 13.4 and added a copy of all the files mentioned in /design/sys/iop/sparc/xst/sparc.flist but the synthesis is not running due to many missing files and unrecognized modules. 2. I earlier implemented the EDK project on Xilinx EDK 10.1. How can I make it run using Xilinx EDK 13.4? Previously it showed the error - ERROR:EDK:3548 - Revup to 13.4 failed ERROR:EDK:3413 - Error(s) were encountered while updating your project. Any inputs for solutions to the above problems would be highly appreciated. Thanks

    DB:2.67:Opensparct1 On Virtex-7 dd


    Hi, I am trying to implement OpenSPARCT1 on Xilinx Virtex-7(VC707 XC7VX485T-2FFG1761CES Evaluation Board), single core and multi core. I first tried the EDK project on Virtex-5 and now I want to check feasibility of implementation of the same on Virtex-7. But I am facing a few problems as below: 1. Generating NGC netlist for Virtex-7 - For rxil command, the OpenSPARCT1 package does not contain the .xst file for my Virtex-7 device. How can I create one or modify the others for my FPGA? Also I tried creating a project on ISE 13.4 and added a copy of all the files mentioned in /design/sys/iop/sparc/xst/sparc.flist but the synthesis is not running due to many missing files and unrecognized modules. 2. I earlier implemented the EDK project on Xilinx EDK 10.1. How can I make it run using Xilinx EDK 13.4? Previously it showed the error - ERROR:EDK:3548 - Revup to 13.4 failed ERROR:EDK:3413 - Error(s) were encountered while updating your project. Any inputs for solutions to the above problems would be highly appreciated. Thanks

  • RELEVANCY SCORE 2.67

    DB:2.67:Vitex4 Ml403 xf


    Hello,

    I have downloaded virtex ml403 reference design from xilinx
    website..but it is for EDK 8.1 ..so this project is not opening in
    prpoer way in EDK 11.1..when i opened it in EDK 9.2i ,it opens..but
    further it genarates an error msg like....

    ERROR:MDT - Invalid target speed '-10'ERROR:MDT - platgen failed with errors!make: *** [implementation/proc_sys_reset_0_wrapper.ngc] Error 2

    I want to use audio signal as input and want to dispaly the sample value....

    any idea regarding this......

    regards

    DB:2.67:Vitex4 Ml403 xf

    Hi!I was in a same situation. The best solution is usenative for reference design XPS version. Because between 8.1 and further versions were made serious modifications.max

  • RELEVANCY SCORE 2.67

    DB:2.67:Can't Generate Netlist After Upgrading Edk From 10.1 Sp2 To 10.1 Sp3 kj


    Please help me with this one:After I have applied SP3 to my 10.1 EDK installation, I get the following error when I try to create Netlist:ERROR:MDT - issued from TCL procedure "::hw_clock_generator_v2_01_a::gen_clock_circuit" line 20 C_CLK_GEN (clock_generator) - Failed to generate clock circuit, please refer to the log file for details.ERROR:MDT - IPNAME:clock_generator INSTANCE:clock_generator_0 - C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\clock_generator_v2_01_a\dat a\clock_generator_v2_1_0.mpd line 34 - error computing override value for C_CLK_GEN using tclERROR:MDT - platgen failed with errors!make: *** [implementation/system.bmm] Error 2 I could generate netlist when I had 10.1 SP2 without problems, and I haven’t changed anything since then, except the Core updates performed by the wizard when I opened my project the first time after I installed SP3.

    I'm using Spartan 3AN andWindos Vista Ultimate.
    TheClock part of my MHS file is shown below:

    BEGIN clock_generatorPARAMETER INSTANCE = clock_generator_0PARAMETER HW_VER = 2.01.aPARAMETER C_EXT_RESET_HIGH = 1PARAMETER C_CLKIN_FREQ = 50000000PARAMETER C_CLKOUT0_FREQ = 66666667PARAMETER C_CLKOUT0_BUF = TRUEPARAMETER C_CLKOUT0_PHASE = 0PARAMETER C_CLKOUT0_GROUP = NONEPARAMETER C_CLKOUT1_FREQ = 133333334PARAMETER C_CLKOUT1_BUF = TRUEPARAMETER C_CLKOUT1_PHASE = 0PARAMETER C_CLKOUT1_GROUP = DCM0PARAMETER C_CLKOUT2_FREQ = 133333334PARAMETER C_CLKOUT2_BUF = TRUEPARAMETER C_CLKOUT2_PHASE = 90PARAMETER C_CLKOUT2_GROUP = DCM0PARAMETER C_CLKIN_BUF = FALSEPARAMETER C_CLKOUT3_FREQ = 22222222PARAMETER C_CLKOUT3_PHASE = 0PARAMETER C_CLKOUT3_GROUP = NONEPARAMETER C_CLKOUT3_BUF = TRUEPARAMETER C_CLKOUT4_FREQ = 1709401PARAMETER C_CLKOUT4_PHASE = 0PARAMETER C_CLKOUT4_GROUP = NONEPARAMETER C_CLKOUT4_BUF = TRUEPORT CLKOUT0 = sys_clk_sPORT CLKOUT1 = DDR2_SDRAM_mpmc_clk_sPORT CLKOUT2 = DDR2_SDRAM_mpmc_clk_90_sPORT CLKIN = dcm_clk_sPORT LOCKED = Dcm_all_lockedPORT RST = net_gndPORT CLKOUT3 = clk_cicPORT CLKOUT4 = clk_micEND
    Thanks in advance!






    Solved!
    Go to Solution.

    DB:2.67:Can't Generate Netlist After Upgrading Edk From 10.1 Sp2 To 10.1 Sp3 kj


    See what I've posted at the bottom of this thread:

    http://forums.xilinx.com/xlnx/board/message?board.id=EDKmessage.id=9229jump=true

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk Problem In Xup Lab With Virtex-Ii Pro x9


    Hello, I experiment the Lab with Virtex-II Pro in Xilinx University Program, and I'm using EDK8.2i.But I found some errors in XUP Lab1 - Simple Hardware Design (Targeting XUP Virtex-II Pro PPC).
    I followed the steps of this lab, Creating (or Opening) the Project, then Generating the Hardware Netlists. There was all
    right and No error found.Then "Update Bitstream", some errors came out.
    I want to show some errors as follows:"...

    2 [main] powerpc-eabi-gcc 6060 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid
    5724, Win32 error 87
    powerpc-eabi-gcc: fork: Resource temporarily unavailablemake[1]: *** [libs] Error 1
    22821660 [main] powerpc-eabi-gcc 4344 fork_copy: linked dll data/bss pass 0 failed, 0x3CD000..0x3CD020, done 0, windows pid
    4236, Win32 error 87

    ...

    Compiling opbarb
    powerpc-eabi-gcc: Internal error: Segmentation fault (program as)
    make[1]: *** [libs] Error 1
    2 [main] powerpc-eabi-gcc 2444 fork_copy: linked dll data/bss pass 0 failed, 0x88D000..0x88D020, done 0, windows pid
    1432, Win32 error 87
    powerpc-eabi-gcc: Internal error: Segmentation fault (program as)
    make[1]: *** [libs] Error 1

    ...

    Installing Cygwin from EDK installation area...Added registry entries for E:\EDK\cygwin
    2 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 5156,
    Win32 error 871012257 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 3144,
    Win32 error 873023449 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 5872,
    Win32 error 87/cygdrive/e/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/3.4.1/../../../../powerpc-eabi/bin/ld: cannot find boot.ocollect2: ld returned 1 exit statusmake: *** [TestApp_Peripheral/executable.elf] Error 1

    ..."

    And my laptop is HP 2210b with CPU T7100 and my operation system is VISTA Ultimate. And the software is ISE8.2i and EDK8.2i.I am now puzzled. How can I solve this problem?

    Thanks

    -Stefaniee

    P.S. the Attachment is the output when I did the procedure of "Update Bitstream".










    Attachments:







    Update_Bitstream2.txt ‏39 KB

    DB:2.66:Edk Problem In Xup Lab With Virtex-Ii Pro x9

    Hello, I experiment the Lab with Virtex-II Pro in Xilinx University Program, and I'm using EDK8.2i.But I found some errors in XUP Lab1 - Simple Hardware Design (Targeting XUP Virtex-II Pro PPC).
    I followed the steps of this lab, Creating (or Opening) the Project, then Generating the Hardware Netlists. There was all
    right and No error found.Then "Update Bitstream", some errors came out.
    I want to show some errors as follows:"...

    2 [main] powerpc-eabi-gcc 6060 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid
    5724, Win32 error 87
    powerpc-eabi-gcc: fork: Resource temporarily unavailablemake[1]: *** [libs] Error 1
    22821660 [main] powerpc-eabi-gcc 4344 fork_copy: linked dll data/bss pass 0 failed, 0x3CD000..0x3CD020, done 0, windows pid
    4236, Win32 error 87

    ...

    Compiling opbarb
    powerpc-eabi-gcc: Internal error: Segmentation fault (program as)
    make[1]: *** [libs] Error 1
    2 [main] powerpc-eabi-gcc 2444 fork_copy: linked dll data/bss pass 0 failed, 0x88D000..0x88D020, done 0, windows pid
    1432, Win32 error 87
    powerpc-eabi-gcc: Internal error: Segmentation fault (program as)
    make[1]: *** [libs] Error 1

    ...

    Installing Cygwin from EDK installation area...Added registry entries for E:\EDK\cygwin
    2 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 5156,
    Win32 error 871012257 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 3144,
    Win32 error 873023449 [main] collect2 4288 fork_copy: linked dll data/bss pass 0 failed, 0x8DD000..0x8DD020, done 0, windows pid 5872,
    Win32 error 87/cygdrive/e/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/3.4.1/../../../../powerpc-eabi/bin/ld: cannot find boot.ocollect2: ld returned 1 exit statusmake: *** [TestApp_Peripheral/executable.elf] Error 1

    ..."

    And my laptop is HP 2210b with CPU T7100 and my operation system is VISTA Ultimate. And the software is ISE8.2i and EDK8.2i.I am now puzzled. How can I solve this problem?

    Thanks

    -Stefaniee

    P.S. the Attachment is the output when I did the procedure of "Update Bitstream".










    Attachments:







    Update_Bitstream2.txt ‏39 KB

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk 11.1 Error Failed To Launch Sdk ck



    hi all,

    we are using edk 11.1 with our custom board. earlier we were able work with both EDK and SDK successfully.Recently SDK stopped working

    suddenly.SDK not launching in either ways (from EDK or by clicking the SDK icon on the desktop). It is giving an eclipse error " an error has

    occured,see the log file 'C:\xilinx\11.1\EDK\Eclipse\bin\nt\configuration\1254915256564.log" . i have attached the error dialog box with this

    messagem, please find the attachment of picture.

    can you please help to solve this problem.

    regards,

    Varun.G










    Attachments:




    DB:2.66:Edk 11.1 Error Failed To Launch Sdk ck


    the content of the log file like this

    "!SESSION 2010-03-29 17:35:40.811 -----------------------------------------------eclipse.buildId=M20060118-1600java.version=1.6.0_18java.vendor=Sun Microsystems Inc.BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=hu_HUCommand-line arguments: -os win32 -ws win32 -arch x86!ENTRY org.eclipse.osgi 2010-03-29 17:35:41.244!MESSAGE Unexpected exception occurred loading manifest for bundle at the location: update@plugins/com.xilinx.mdt.edk.cheatsheets_11.1.0/.!STACK 0org.osgi.framework.BundleException: Error converting plugin at c:\Xilinx\11.1\EDK\eclipse\bin\nt\plugins\com.xilinx.mdt.edk.cheatsheets_11.1.0. at org.eclipse.core.runtime.adaptor.EclipseBundleData.generateManifest(EclipseBundleData.java:302) at org.eclipse.core.runtime.adaptor.EclipseBundleData.loadManifest(EclipseBundleData.java:257) at org.eclipse.core.runtime.internal.adaptor.CachedManifest.getManifest(CachedManifest.java:38) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.createStateManager(EclipseAdaptor.java:257) at org.eclipse.osgi.framework.adaptor.core.AbstractFrameworkAdaptor.frameworkStart(AbstractFrameworkAdaptor.java:330) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.frameworkStart(EclipseAdaptor.java:332) at org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start(SystemBundleActivator.java:55) at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:994) at java.security.AccessController.doPrivileged(Native Method) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.startActivator(BundleContextImpl.java:988) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.start(BundleContextImpl.java:969) at org.eclipse.osgi.framework.internal.core.StartLevelManager.resumeBundles(StartLevelManager.java:550) at org.eclipse.osgi.framework.internal.core.StartLevelManager.incFWSL(StartLevelManager.java:485) at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:275) at org.eclipse.osgi.framework.internal.core.StartLevelManager.launch(StartLevelManager.java:245) at org.eclipse.osgi.framework.internal.core.SystemBundle.resume(SystemBundle.java:155) at org.eclipse.osgi.framework.internal.core.Framework.launch(Framework.java:503) at org.eclipse.osgi.framework.internal.core.OSGi.launch(OSGi.java:51) at org.eclipse.core.runtime.adaptor.EclipseStarter.startup(EclipseStarter.java:275) at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:159) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)Caused by: org.eclipse.osgi.service.pluginconversion.PluginConversionException: Could not find a plugin.xml or a fragment.xml in c:\Xilinx\11.1\EDK\eclipse\bin\nt\plugins\com.xilinx.mdt.edk.cheatsheets_11.1.0. at org.eclipse.core.runtime.internal.adaptor.PluginConverterImpl.fillPluginInfo(PluginConverterImpl.java:93) at org.eclipse.core.runtime.internal.adaptor.PluginConverterImpl.convertManifest(PluginConverterImpl.java:689) at org.eclipse.core.runtime.adaptor.EclipseBundleData.generateManifest(EclipseBundleData.java:299) ... 27 moreRoot exception:org.eclipse.osgi.service.pluginconversion.PluginConversionException: Could not find a plugin.xml or a fragment.xml in c:\Xilinx\11.1\EDK\eclipse\bin\nt\plugins\com.xilinx.mdt.edk.cheatsheets_11.1.0. at org.eclipse.core.runtime.internal.adaptor.PluginConverterImpl.fillPluginInfo(PluginConverterImpl.java:93) at org.eclipse.core.runtime.internal.adaptor.PluginConverterImpl.convertManifest(PluginConverterImpl.java:689) at org.eclipse.core.runtime.adaptor.EclipseBundleData.generateManifest(EclipseBundleData.java:299) at org.eclipse.core.runtime.adaptor.EclipseBundleData.loadManifest(EclipseBundleData.java:257) at org.eclipse.core.runtime.internal.adaptor.CachedManifest.getManifest(CachedManifest.java:38) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.createStateManager(EclipseAdaptor.java:257) at org.eclipse.osgi.framework.adaptor.core.AbstractFrameworkAdaptor.frameworkStart(AbstractFrameworkAdaptor.java:330) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.frameworkStart(EclipseAdaptor.java:332) at org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start(SystemBundleActivator.java:55) at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:994) at java.security.AccessController.doPrivileged(Native Method) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.startActivator(BundleContextImpl.java:988) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.start(BundleContextImpl.java:969) at org.eclipse.osgi.framework.internal.core.StartLevelManager.resumeBundles(StartLevelManager.java:550) at org.eclipse.osgi.framework.internal.core.StartLevelManager.incFWSL(StartLevelManager.java:485) at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:275) at org.eclipse.osgi.framework.internal.core.StartLevelManager.launch(StartLevelManager.java:245) at org.eclipse.osgi.framework.internal.core.SystemBundle.resume(SystemBundle.java:155) at org.eclipse.osgi.framework.internal.core.Framework.launch(Framework.java:503) at org.eclipse.osgi.framework.internal.core.OSGi.launch(OSGi.java:51) at org.eclipse.core.runtime.adaptor.EclipseStarter.startup(EclipseStarter.java:275) at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:159) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)!ENTRY System Bundle 0 0 2010-03-29 17:35:41.255!MESSAGE FrameworkEvent.ERROR!STACK 0org.osgi.framework.BundleException: Exception in org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start() of bundle system.bundle. at org.eclipse.osgi.framework.internal.core.BundleContextImpl.startActivator(BundleContextImpl.java:1013) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.start(BundleContextImpl.java:969) at org.eclipse.osgi.framework.internal.core.StartLevelManager.resumeBundles(StartLevelManager.java:550) at org.eclipse.osgi.framework.internal.core.StartLevelManager.incFWSL(StartLevelManager.java:485) at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:275) at org.eclipse.osgi.framework.internal.core.StartLevelManager.launch(StartLevelManager.java:245) at org.eclipse.osgi.framework.internal.core.SystemBundle.resume(SystemBundle.java:155) at org.eclipse.osgi.framework.internal.core.Framework.launch(Framework.java:503) at org.eclipse.osgi.framework.internal.core.OSGi.launch(OSGi.java:51) at org.eclipse.core.runtime.adaptor.EclipseStarter.startup(EclipseStarter.java:275) at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:159) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)Caused by: java.lang.NullPointerException at org.eclipse.osgi.internal.resolver.StateBuilder.createBundleDescription(StateBuilder.java:31) at org.eclipse.osgi.internal.resolver.StateObjectFactoryImpl.createBundleDescription(StateObjectFactoryImpl.java:27) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.createStateManager(EclipseAdaptor.java:258) at org.eclipse.osgi.framework.adaptor.core.AbstractFrameworkAdaptor.frameworkStart(AbstractFrameworkAdaptor.java:330) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.frameworkStart(EclipseAdaptor.java:332) at org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start(SystemBundleActivator.java:55) at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:994) at java.security.AccessController.doPrivileged(Native Method) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.startActivator(BundleContextImpl.java:988) ... 18 moreRoot exception:java.lang.NullPointerException at org.eclipse.osgi.internal.resolver.StateBuilder.createBundleDescription(StateBuilder.java:31) at org.eclipse.osgi.internal.resolver.StateObjectFactoryImpl.createBundleDescription(StateObjectFactoryImpl.java:27) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.createStateManager(EclipseAdaptor.java:258) at org.eclipse.osgi.framework.adaptor.core.AbstractFrameworkAdaptor.frameworkStart(AbstractFrameworkAdaptor.java:330) at org.eclipse.core.runtime.adaptor.EclipseAdaptor.frameworkStart(EclipseAdaptor.java:332) at org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start(SystemBundleActivator.java:55) at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:994) at java.security.AccessController.doPrivileged(Native Method) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.startActivator(BundleContextImpl.java:988) at org.eclipse.osgi.framework.internal.core.BundleContextImpl.start(BundleContextImpl.java:969) at org.eclipse.osgi.framework.internal.core.StartLevelManager.resumeBundles(StartLevelManager.java:550) at org.eclipse.osgi.framework.internal.core.StartLevelManager.incFWSL(StartLevelManager.java:485) at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:275) at org.eclipse.osgi.framework.internal.core.StartLevelManager.launch(StartLevelManager.java:245) at org.eclipse.osgi.framework.internal.core.SystemBundle.resume(SystemBundle.java:155) at org.eclipse.osgi.framework.internal.core.Framework.launch(Framework.java:503) at org.eclipse.osgi.framework.internal.core.OSGi.launch(OSGi.java:51) at org.eclipse.core.runtime.adaptor.EclipseStarter.startup(EclipseStarter.java:275) at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:159) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)!ENTRY org.eclipse.osgi 2010-03-29 17:35:41.259!MESSAGE Startup error!STACK 1java.lang.RuntimeException: Exception in org.eclipse.osgi.framework.internal.core.SystemBundleActivator.start() of bundle system.bundle. at org.eclipse.osgi.framework.internal.core.StartLevelManager.resumeBundles(StartLevelManager.java:558) at org.eclipse.osgi.framework.internal.core.StartLevelManager.incFWSL(StartLevelManager.java:485) at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:275) at org.eclipse.osgi.framework.internal.core.StartLevelManager.launch(StartLevelManager.java:245) at org.eclipse.osgi.framework.internal.core.SystemBundle.resume(SystemBundle.java:155) at org.eclipse.osgi.framework.internal.core.Framework.launch(Framework.java:503) at org.eclipse.osgi.framework.internal.core.OSGi.launch(OSGi.java:51) at org.eclipse.core.runtime.adaptor.EclipseStarter.startup(EclipseStarter.java:275) at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:159) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)!SESSION Mon Mar 29 17:35:41 CEST 2010 -----------------------------------------!ENTRY org.eclipse.core.launcher 4 0 2010-03-29 17:35:41.265!MESSAGE Exception launching the Eclipse Platform:!STACKjava.lang.NullPointerException at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:172) at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) at java.lang.reflect.Method.invoke(Unknown Source) at org.eclipse.core.launcher.Main.invokeFramework(Main.java:334) at org.eclipse.core.launcher.Main.basicRun(Main.java:278) at org.eclipse.core.launcher.Main.run(Main.java:973) at org.eclipse.core.launcher.Main.main(Main.java:948)"

    It seems a Java RE problem. Any other suggest for solving this problem are greatly acknowledged.

    regards

    Zsolt

    ps. the installed JAVA RE is the lastest version 1.6.0._18

  • RELEVANCY SCORE 2.65

    DB:2.65:[Standalone Program] Simple I/O Using Hyperterminal cm


    Hi,
    I am trying to create simple standalone program to get some values from keyboard via hyperterminal and let Opensparc on FPGA do the processing and then display the result back in hyperterminal. I have sunStudio compiler. However, it seems scanf is not recognized by the compiler?

    ***********************************************************************************
    /home/ssoekamt/sparct1/design/sys/edk/examples/src/simple_add
    /opt/sunstudio12.1/bin/cc -xarch=v9 -I../include -errwarn=%all -xO2 -c simple_add.c
    cc: Warning: -xarch=v9 is deprecated, use -m64 to create 64-bit programs
    /usr/ccs/bin/ld -64 -e start -dn -M ../mapfile -o simpleadd -z allextract -L ../libos -los simple_add.o -L ../libc -lc
    Undefinedfirst referenced
    symbol in file
    scanf simple_add.o
    ld: fatal: Symbol referencing errors. No output written to simple_add
    *** Error code 1
    make: Fatal error: Command failed for target `simple_add'
    Current working directory /home/ssoekamt/sparct1/design/sys/edk/examples/src/simple_add
    *** Error code 1
    The following command caused the error:
    cd simple_add pwd make install
    make: Fatal error: Command failed for target `simple_add'
    *********************************************************************************

    When I commented out all scanf statements in the codes, everything is working.
    any thought?
    Thank you.

    DB:2.65:[Standalone Program] Simple I/O Using Hyperterminal cm

    Hi,
    I am trying to create simple standalone program to get some values from keyboard via hyperterminal and let Opensparc on FPGA do the processing and then display the result back in hyperterminal. I have sunStudio compiler. However, it seems scanf is not recognized by the compiler?

    ***********************************************************************************
    /home/ssoekamt/sparct1/design/sys/edk/examples/src/simple_add
    /opt/sunstudio12.1/bin/cc -xarch=v9 -I../include -errwarn=%all -xO2 -c simple_add.c
    cc: Warning: -xarch=v9 is deprecated, use -m64 to create 64-bit programs
    /usr/ccs/bin/ld -64 -e start -dn -M ../mapfile -o simpleadd -z allextract -L ../libos -los simple_add.o -L ../libc -lc
    Undefinedfirst referenced
    symbol in file
    scanf simple_add.o
    ld: fatal: Symbol referencing errors. No output written to simple_add
    *** Error code 1
    make: Fatal error: Command failed for target `simple_add'
    Current working directory /home/ssoekamt/sparct1/design/sys/edk/examples/src/simple_add
    *** Error code 1
    The following command caused the error:
    cd simple_add pwd make install
    make: Fatal error: Command failed for target `simple_add'
    *********************************************************************************

    When I commented out all scanf statements in the codes, everything is working.
    any thought?
    Thank you.

  • RELEVANCY SCORE 2.65

    DB:2.65:Error:Import Edk p1



    Hi:

    When I importing EDK into system generator, one error occured.

    Error executing sg_xps_import.tcl (when Configuring user EDK project).

    Anyone knows?

    thanks!

    regards

    DB:2.65:Error:Import Edk p1


    Hi:

    When I importing EDK into system generator, one error occured.

    Error executing sg_xps_import.tcl (when Configuring user EDK project).

    Anyone knows?

    thanks!

    regards

  • RELEVANCY SCORE 2.65

    DB:2.65:Problem About Fx200t Edk V11.1 Ll_Temac mf



    when i regenerate the ngc, a error will occur:

    Failed to run core generator for xps_ll_temac_0_wrapper_fifo_generator_v4_3_1macr​o.

    i am confused by this problem.

    DB:2.65:Problem About Fx200t Edk V11.1 Ll_Temac mf


    when i regenerate the ngc, a error will occur:

    Failed to run core generator for xps_ll_temac_0_wrapper_fifo_generator_v4_3_1macr​o.

    i am confused by this problem.

  • RELEVANCY SCORE 2.64

    DB:2.64:Opb_Plbv46_Bridge Or Plb2opb_Bridge ?Help Needed da


    Hello folks:
    I am using EDK9.2 issue which support plb bus only.But I want to add some OPB devices into my design which means an OPB bus should be added too.So I turn to the bridges.There are opb_plbv46_bridge,plbv46_opb_bridge,opb2plb_bridge and plb2opb_bridge in the directory of "EDK\hw\XilinxProcessorIPLib\pcores".Which one should I choose?
    However I have tried all of them.I imported them with CIP Wizard.But problem occurs. The CIP Wizard would let me select the bus interfaces.I think one side of the bridge should connect to PLB and the other side to OPB,Then I do so.But when I importing the plbbv46_opb_bridge,opb2plb_bridgeor plb2opb_bridge,the CIP Wizard would let me select the ports of the bridge manually.That is terrible.What should I do with this?
    Fortunately,the opb_plbv46_bridge could select the ports automatically,but I don't know whether I should choose this kind of bridge.However when I generate the bitstream of the hardware,another problem occurs saying "opb_v20 INSTANCE:must have atleast 1 master assigned"I give all of the report on the error below.

    In a word,I ask for help that which bridge should I choose and if the opb_plbv46_bridge is right,how could I resolve the problem below?If any other bridge is right how can I select the ports of the bridge correctly?

    Sincerely hoping for the help!

    The EDK report when I generate the bitstream of hardware(using opb_plbv46_bridge)
    /********************************************************************************/
    At Local date and time: Fri Apr 18 15:57:34 2008xbash -q -c "cd /cygdrive/f/EDKWORK/opbnet/; /usr/bin/make -f system.make bits; exit;" started...****************************************************Creating system netlist for hardware specification..****************************************************platgen -p xc3s500efg320-4 -lang vhdl system.mhs
    Release Xilinx EDK 9.2.02 - platgen EDK_Jm_SP2.3Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
    Command Line: platgen -p xc3s500efg320-4 -lang vhdl system.mhs
    Parse system.mhs ...
    Read MPD definitions ...
    Overriding IP level properties ...INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 164 - tcl is overriding PARAMETER C_ADDR_TAG_BITS value to 0INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 172 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG value to 0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 135 - tcl is overriding PARAMETER C_MEM_PART_DATA_DEPTH value to 32INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 136 - tcl is overriding PARAMETER C_MEM_PART_DATA_WIDTH value to 16INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 139 - tcl is overriding PARAMETER C_MEM_PART_NUM_COL_BITS value to 10INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 140 - tcl is overriding PARAMETER C_MEM_PART_TRAS value to 42000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 141 - tcl is overriding PARAMETER C_MEM_PART_TRASMAX value to 70000000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 142 - tcl is overriding PARAMETER C_MEM_PART_TRC value to 60000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 143 - tcl is overriding PARAMETER C_MEM_PART_TRCD value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 145 - tcl is overriding PARAMETER C_MEM_PART_TWR value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 146 - tcl is overriding PARAMETER C_MEM_PART_TRP value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 147 - tcl is overriding PARAMETER C_MEM_PART_TMRD value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 148 - tcl is overriding PARAMETER C_MEM_PART_TRRD value to 12000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 149 - tcl is overriding PARAMETER C_MEM_PART_TRFC value to 72000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 150 - tcl is overriding PARAMETER C_MEM_PART_TREFI value to 7800000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 155 - tcl is overriding PARAMETER C_MEM_PART_CAS_A_FMAX value to 133INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 156 - tcl is overriding PARAMETER C_MEM_PART_CAS_A value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 157 - tcl is overriding PARAMETER C_MEM_PART_CAS_B_FMAX value to 166INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 158 - tcl is overriding PARAMETER C_MEM_PART_CAS_B value to 2.5
    Performing IP level DRCs on properties...
    Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...Address Map for Processor microblaze_0 (0000000000-0x00003fff) dlmb_cntlrdlmb (0000000000-0x00003fff) ilmb_cntlrilmb (0x81400000-0x8140ffff) LEDs_8Bitmb_plb (0x81420000-0x8142ffff) DIP_Switches_4Bitmb_plb (0x81800000-0x8180ffff) xps_intc_0mb_plb (0x84000000-0x8400ffff) RS232_DCEmb_plb (0x84400000-0x8440ffff) debug_modulemb_plb (0x89000000-0x89ffffff) FLASHmb_plb (0x8c000000-0x8fffffff) DDR_SDRAMmb_plb
    Check platform address map ...INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 203 - tool is overriding PARAMETER C_SPLB0_P2P value to 0
    Overriding system level properties ...INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 125 - tcl is overriding PARAMETER C_D_PLB value to 1INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 126 - tcl is overriding PARAMETER C_D_OPB value to 0INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 128 - tcl is overriding PARAMETER C_I_PLB value to 1INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - d:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_b\data\microblaze_v2_1_0.mpd line 129 - tcl is overriding PARAMETER C_I_OPB value to 0INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - d:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 35 - tool is overriding PARAMETER C_PLBV46_NUM_MASTERS value to 3INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - d:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 36 - tool is overriding PARAMETER C_PLBV46_NUM_SLAVES value to 7INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - d:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 39 - tool is overriding PARAMETER C_PLBV46_DWIDTH value to 32INFO:MDT - IPNAME:ilmb INSTANCE:lmb_v10 - d:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1INFO:MDT - IPNAME:dlmb INSTANCE:lmb_v10 - d:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1INFO:MDT - IPNAME:dlmb_cntlr INSTANCE:lmb_bram_if_cntlr - d:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK value to 0x80000000INFO:MDT - IPNAME:ilmb_cntlr INSTANCE:lmb_bram_if_cntlr - d:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK value to 0x80000000INFO:MDT - IPNAME:lmb_bram INSTANCE:bram_block - d:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 36 - tool is overriding PARAMETER C_MEMSIZE value to 0x4000INFO:MDT - IPNAME:RS232_DCE INSTANCE:xps_uartlite - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\data\xps_uartlite_v2_1_0.mpd line 44 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:RS232_DCE INSTANCE:xps_uartlite - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\data\xps_uartlite_v2_1_0.mpd line 45 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:LEDs_8Bit INSTANCE:xps_gpio - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.mpd line 40 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:LEDs_8Bit INSTANCE:xps_gpio - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.mpd line 41 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:DIP_Switches_4Bit INSTANCE:xps_gpio - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.mpd line 40 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:DIP_Switches_4Bit INSTANCE:xps_gpio - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.mpd line 41 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:FLASH INSTANCE:xps_mch_emc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v1_00_a\data\xps_mch_emc_v2_1_0.mpd line 46 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:FLASH INSTANCE:xps_mch_emc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v1_00_a\data\xps_mch_emc_v2_1_0.mpd line 47 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 199 - tool is overriding PARAMETER C_SPLB0_DWIDTH value to 32INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 201 - tool is overriding PARAMETER C_SPLB0_NUM_MASTERS value to 3INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 202 - tool is overriding PARAMETER C_SPLB0_MID_WIDTH value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 163 - tcl is overriding PARAMETER C_MEM_CAS_LATENCY0 value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 195 - tcl is overriding PARAMETER C_PIM0_SUBTYPE value to PLBINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 516 - tcl is overriding PARAMETER C_CTRL_DP_RDFIFO_WHICHPORT_DELAY value to 0xbINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 519 - tcl is overriding PARAMETER C_CTRL_PHYIF_DUMMYREADSTART_DELAY value to 0x5INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 526 - tcl is overriding PARAMETER C_CTRL_Q6_DELAY value to 0x4INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 527 - tcl is overriding PARAMETER C_CTRL_Q7_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 528 - tcl is overriding PARAMETER C_CTRL_Q8_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 529 - tcl is overriding PARAMETER C_CTRL_Q9_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 531 - tcl is overriding PARAMETER C_CTRL_Q11_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 532 - tcl is overriding PARAMETER C_CTRL_Q12_DELAY value to 0x1INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 533 - tcl is overriding PARAMETER C_CTRL_Q13_DELAY value to 0x1INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 537 - tcl is overriding PARAMETER C_CTRL_Q17_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 538 - tcl is overriding PARAMETER C_CTRL_Q18_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 539 - tcl is overriding PARAMETER C_CTRL_Q19_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 540 - tcl is overriding PARAMETER C_CTRL_Q20_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 541 - tcl is overriding PARAMETER C_CTRL_Q21_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 542 - tcl is overriding PARAMETER C_CTRL_Q22_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 543 - tcl is overriding PARAMETER C_CTRL_Q23_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 544 - tcl is overriding PARAMETER C_CTRL_Q24_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 545 - tcl is overriding PARAMETER C_CTRL_Q25_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 546 - tcl is overriding PARAMETER C_CTRL_Q26_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 547 - tcl is overriding PARAMETER C_CTRL_Q27_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 548 - tcl is overriding PARAMETER C_CTRL_Q28_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 549 - tcl is overriding PARAMETER C_CTRL_Q29_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 550 - tcl is overriding PARAMETER C_CTRL_Q30_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 551 - tcl is overriding PARAMETER C_CTRL_Q31_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 552 - tcl is overriding PARAMETER C_CTRL_Q32_DELAY value to 0x1INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 553 - tcl is overriding PARAMETER C_CTRL_Q33_DELAY value to 0x1INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 554 - tcl is overriding PARAMETER C_CTRL_Q34_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 555 - tcl is overriding PARAMETER C_CTRL_Q35_DELAY value to 0x0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 556 - tcl is overriding PARAMETER C_SKIP_1_VALUE value to 0x001INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 557 - tcl is overriding PARAMETER C_SKIP_2_VALUE value to 0x001INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 558 - tcl is overriding PARAMETER C_SKIP_3_VALUE value to 0x001INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 559 - tcl is overriding PARAMETER C_SKIP_4_VALUE value to 0x001INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 560 - tcl is overriding PARAMETER C_SKIP_5_VALUE value to 0x001INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 561 - tcl is overriding PARAMETER C_B32_REPEAT_CNT value to 6INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 562 - tcl is overriding PARAMETER C_B64_REPEAT_CNT value to 14INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 564 - tcl is overriding PARAMETER C_HIGHADDR_CTRL0 value to 0x008INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 565 - tcl is overriding PARAMETER C_BASEADDR_CTRL1 value to 0x009INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 566 - tcl is overriding PARAMETER C_HIGHADDR_CTRL1 value to 0x00fINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 567 - tcl is overriding PARAMETER C_BASEADDR_CTRL2 value to 0x010INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 568 - tcl is overriding PARAMETER C_HIGHADDR_CTRL2 value to 0x019INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 569 - tcl is overriding PARAMETER C_BASEADDR_CTRL3 value to 0x01aINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 570 - tcl is overriding PARAMETER C_HIGHADDR_CTRL3 value to 0x020INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 571 - tcl is overriding PARAMETER C_BASEADDR_CTRL4 value to 0x021INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 572 - tcl is overriding PARAMETER C_HIGHADDR_CTRL4 value to 0x02cINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 573 - tcl is overriding PARAMETER C_BASEADDR_CTRL5 value to 0x02dINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 574 - tcl is overriding PARAMETER C_HIGHADDR_CTRL5 value to 0x034INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 575 - tcl is overriding PARAMETER C_BASEADDR_CTRL6 value to 0x035INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 576 - tcl is overriding PARAMETER C_HIGHADDR_CTRL6 value to 0x044INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 577 - tcl is overriding PARAMETER C_BASEADDR_CTRL7 value to 0x045INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 578 - tcl is overriding PARAMETER C_HIGHADDR_CTRL7 value to 0x050INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 579 - tcl is overriding PARAMETER C_BASEADDR_CTRL8 value to 0x051INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 580 - tcl is overriding PARAMETER C_HIGHADDR_CTRL8 value to 0x068INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 581 - tcl is overriding PARAMETER C_BASEADDR_CTRL9 value to 0x069INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 582 - tcl is overriding PARAMETER C_HIGHADDR_CTRL9 value to 0x07cINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 583 - tcl is overriding PARAMETER C_BASEADDR_CTRL10 value to 0x07dINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 584 - tcl is overriding PARAMETER C_HIGHADDR_CTRL10 value to 0x08cINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 585 - tcl is overriding PARAMETER C_BASEADDR_CTRL11 value to 0x08dINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 586 - tcl is overriding PARAMETER C_HIGHADDR_CTRL11 value to 0x098INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 587 - tcl is overriding PARAMETER C_BASEADDR_CTRL12 value to 0x099INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 588 - tcl is overriding PARAMETER C_HIGHADDR_CTRL12 value to 0x0a8INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 589 - tcl is overriding PARAMETER C_BASEADDR_CTRL13 value to 0x0a9INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 590 - tcl is overriding PARAMETER C_HIGHADDR_CTRL13 value to 0x0b4INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 591 - tcl is overriding PARAMETER C_BASEADDR_CTRL14 value to 0x0b5INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 592 - tcl is overriding PARAMETER C_HIGHADDR_CTRL14 value to 0x0beINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 593 - tcl is overriding PARAMETER C_BASEADDR_CTRL15 value to 0x0bfINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 594 - tcl is overriding PARAMETER C_HIGHADDR_CTRL15 value to 0x0c0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 633 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_19 value to 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FCINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 634 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_18 value to 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC0000003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 635 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_17 value to 0x0000003C0000003C0000003C0000003C0000003C0000003C0000003D0000003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 636 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_16 value to 0x000000300000003C000040280000003C000040280000043C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 637 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_15 value to 0x000004350000243C000004340000243C000004340000903C000080380001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 638 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_14 value to 0x0001003C000140280001003C0001003C0001003D0001013C000101240001213CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 639 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_13 value to 0x000101240001213C000101240001213C000101240001903C000180380000003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 640 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_12 value to 0x000040280000043C000004340000243C000004350000243C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 641 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_11 value to 0x000004340000903C000080380001003C0001003C000140280001003C0001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 642 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_10 value to 0x0001003D0001013C000101240001213C000101240001213C000101240001213CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 643 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0F value to 0x000101240001903C000180380000003C000040280000043C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 644 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0E value to 0x000004350000243C000004340000243C000004340000243C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 645 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0D value to 0x000004340000243C000004340000243C000004340000903C000080380001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 646 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0C value to 0x0001003C000140280001003C0001003C0001003D0001013C000101240001213CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 647 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0B value to 0x000101240001213C000101240001213C000101240001213C000101240001213CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 648 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0A value to 0x000101240001213C000101240001213C000101240001903C000180380000003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 649 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_09 value to 0x000040280000043C000004340000243C000004350000243C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 650 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_08 value to 0x000004340000903C000080380001003C0001003C000140280001003C0001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 651 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_07 value to 0x0001003D0001013C000101240001213C000101240001213C000101240001213CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 652 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_06 value to 0x000101240001903C000180380000003C000040280000043C000004340000243CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 653 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_05 value to 0x000004350000903C000080380001003C0001003C000140280001003C0001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 654 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_04 value to 0x0001003D0001013C000101240001213C000101240001903C000180380000003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 655 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_03 value to 0x000040280000003C0000043C000004340000903D000080380001003C0001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 656 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_02 value to 0x000140280001003C0001003C0001003D0001013C000101240001903C00018038INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 657 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_01 value to 0x0000003C000040280000003C0000003C000004340000903D000080380001003CINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 658 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_00 value to 0x0001003C000140280001003C0001003C0001013D000101240001903C00018038INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 664 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_03 value to 0x0000000000000000000000000000000000000000000000000000000000000000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 665 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_02 value to 0x0000000000000000000200000000111000020000000000020000000011100002INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 666 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_01 value to 0x0000000000000000000000000000111000000000000000000000000000000000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - d:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_b\data\mpmc_v2_1_0.mpd line 667 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_00 value to 0x1110000000000000000000001110000000000000000111000000000000001110INFO:MDT - IPNAME:debug_module INSTANCE:mdm - d:\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 55 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:debug_module INSTANCE:mdm - d:\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 56 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 44 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 3INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 45 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 2INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 48 - tcl is overriding PARAMETER C_NUM_INTR_INPUTS value to 1INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 49 - tcl is overriding PARAMETER C_KIND_OF_INTR value to 0b00000000000000000000000000000000INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 50 - tcl is overriding PARAMETER C_KIND_OF_EDGE value to 0b00000000000000000000000000000000INFO:MDT - IPNAME:xps_intc_0 INSTANCE:xps_intc - d:\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v1_00_a\data\xps_intc_v2_1_0.mpd line 51 - tcl is overriding PARAMETER C_KIND_OF_LVL value to 0b00000000000000000000000000000001INFO:MDT - IPNAME:opb_v20_0 INSTANCE:opb_v20 - d:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd line 38 - tool is overriding PARAMETER C_NUM_MASTERS value to 0INFO:MDT - IPNAME:opb_v20_0 INSTANCE:opb_v20 - d:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd line 39 - tool is overriding PARAMETER C_NUM_SLAVES value to 1
    Running system level Update ...
    Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
    Performing System level DRCs on properties...
    Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
    Check platform configuration ...IPNAME:plb_v46 INSTANCE:mb_plb - F:\EDKWORK\opbnet\system.mhs line 62 - 3master(s) : 7 slave(s)IPNAME:lmb_v10 INSTANCE:ilmb - F:\EDKWORK\opbnet\system.mhs line 69 - 1master(s) : 1 slave(s)IPNAME:lmb_v10 INSTANCE:dlmb - F:\EDKWORK\opbnet\system.mhs line 76 - 1master(s) : 1 slave(s)IPNAME:opb_v20 INSTANCE:opb_v20_0 - F:\EDKWORK\opbnet\system.mhs line 288 - 0master(s) : 1 slave(s)ERROR:MDT - IPNAME:opb_v20 INSTANCE:opb_v20_0 - F:\EDKWORK\opbnet\system.mhs line 288 - must have atleast 1 master assigned!
    Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...INFO: The DDR_SDRAM core has constraints automatically generated by XPS inimplementation/ddr_sdram_wrapper/ddr_sdram_wrapper.ucf.It can be overridden by constraints placed in the system.ucf file.
    ERROR:MDT - platgen failed with errors!make: *** [implementation/system.bmm] Error 2Done!

    DB:2.64:Opb_Plbv46_Bridge Or Plb2opb_Bridge ?Help Needed da

    Thank you very much.Things seems to work now.
    Thank you!! :-)

  • RELEVANCY SCORE 2.64

    DB:2.64:About Edk Update km



    Hi,

    I update my EDK from 10.1 to 11.1. I met problem with the previous project to use in the new EDK version.

    My project was based on VirtexII pro and it is not support in 11.1 anymore. Lots of error report for not compatible when EDK start.

    I try to change the device in the project option(Now I use Spartan3-E), but it generate serious error and it said to contact Xilinx support.

    Can anyone tell me how to change to new device and make the design work?

    DB:2.64:About Edk Update km

    I tried it. The design already update to 11.1 version and it can not run in 10.1 anymore....Message Edited by squaremeng on 03-08-2010 07:57 AM

  • RELEVANCY SCORE 2.64

    DB:2.64:Manual Ip Version Update In Edk 8.2i 98


    Hi all, I downloaded a reference design from Xilinx, (http://www.xilinx.com/bvdocs/appnotes/xapp441_des​ignfiles.zip). When I open the design in EDK version 8.2.02i, I receive the following error message,“Reving up design to EDK 8.2.02...ERROR:MDT - Unrecoverable error(s) were encountered while updating your project”I tried to open the project the second time, it did without error. When I try to generate bitstream, I receive the following error,“ERROR:MDT - Ip plb_bram_if_cntlr 1.00.a is marked OBSOLETEERROR:MDT - Ip plb_bram_if_cntlr 1.00.a is marked OBSOLETEERROR:MDT - Ip opb_sdram 1.00.c is marked OBSOLETERunning UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...ERROR:MDT - platgen failed with errors!”I suspect that when I open the project the first time, EDK did not update the IP’s due to the error. How do you manually update the IP versions?Thanks in advance.Scott

    DB:2.64:Manual Ip Version Update In Edk 8.2i 98

    Scott,I am having the same problem with a reference design for a Spartan 3 Starter Brd.The design was generated within EDK 8.2 and I am using 9.1.When I initially opened the design, EDK took me through an update Wizard which updated some, but not all, of the design.It left me with a log file, Version_Changes.log, which contained the following:The following files will be modified: system.mhs system.mss--------------------------------------The following changes will be made:Core opb_gpio 3.01.a will be replaced by 3.01.bCore opb_v20 1.10.b will be replaced by 1.10.cDriver cpu 1.00.a will be replaced by 1.01.aDriver uartlite 1.00.b will be replaced by 1.02.a--------------------------------------The following changes need to be made manually by the user:Core microblaze 2.10.a needs to be replaced by 6.00.bCore lmb_bram_if_cntlr 1.00.b needs to be replaced by 2.00.aCore opb_emc 1.10.b needs to be replaced by 2.00.aCore fsl_v20 1.00.b needs to be replaced by 2.10.aDriver emc 1.00.a needs to be replaced by 1.01.aAfter much trial and error, mostly error, I edited the mhs and mss files to conform to the manuall changes indicated in the last section above.The core instances were in the mhs file, and the driver instance was in the mss file.While this got me further along, there is more to this equation and I am not yet done.Good luck.Mark Abraira

  • RELEVANCY SCORE 2.64

    DB:2.64:Edk 92 Vsim Unisims_Ver And Verilog Fails To Simulate cs



    Hi,

    I would like to simulate a design made with EDK 92i (SP2) of ml405 based basic design

    Unfortunately, the simulation fails du to the verilog module of the MPMC

    I make a configuration of the top level that includes the design and here is the message I have

    # vsim -L unisims_ver -L simprims_ver work.bench_cfg # ** Note: (vsim-3812) Design is being optimized...# ** Error: /rech-fmr/mancini/EDK92/lib/ise92/unisims_ver/unisims_ver_source.v(60928): Failed to find 'glbl' in hierarchical name.# Optimization failed

    What's the trouble ?

    Does it mean that unisms_ver_source.v is different from the VHDL code ????

    What should I do to simulate this design ?

    Thanks

    DB:2.64:Edk 92 Vsim Unisims_Ver And Verilog Fails To Simulate cs


    Hello,

    To resolve this issue, make sure the globals source file is compiled. This source file is located at:

    %XILINX%/verilog/src/glbl.v

    Edit your simulation script to the source code above is compiled. It should resolve the error.

    Hope this helps.




    Eddie

  • RELEVANCY SCORE 2.63

    DB:2.63:Error While Running "Make" For Microblze 3z



    hello,

    while generating libraries for project on edk, following error occurs.what is the cause for it? and how can i solve it?

    -------------

    mb-ar: ../../../lib/libxil.a: No space left on devicemake[1]: *** [libs] Error 1ERROR:MDT - make failed for target "libs" ERROR:MDT - Error while running "make" for processor microblaze_0...mb-ar: ../../../lib/libxil.a: No space left on devicemake[1]: *** [libs] Error 1Done!

    --------------

    nasim

    DB:2.63:Error While Running "Make" For Microblze 3z


    Hi,

    I guess you are running out of space on the project directory location.

    Try to run the project on another location.

    Thanks.




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.63

    DB:2.63:Edk 9.1 Error 39



    Hello all:

    When I try to either update bitstream, or generate bitstream in EDK 9.1 on Linux, I get this error:

    Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...Sourcing tcl file/opt/applics/9.1i/EDK-9.1i/hw/XilinxProcessorIPLib​/pcores/ddr2_v1_03_b/data/ddr2_v2_1_0.tcl ...Sourcing tcl file/opt/applics/9.1i/EDK-9.1i/hw/XilinxProcessorIPLib​/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cntlr_v2_1_0.tcl ...Sourcing tcl file/opt/applics/9.1i/EDK-9.1i/hw/XilinxProcessorIPLib​/pcores/bram_if_cntlr_v1_00_b/data/bram_if_cntlr_v2_1_0.tcl ...ERROR:MDT - opb_epc_0 (opb_epc) - Invalid opb_epc_0 parameter: C_PRH0_WRN_WIDTH must be less than C_PRH0_WR_CYCLE while executing "error "Invalid $instname parameter:\n$wrn_width_param must be less than $wr_cycle_param" "" "libgen_error"" (procedure "check_wrn_width" line 15) invoked from within "check_wrn_width $mhsinst" (procedure "::hw_opb_epc_v1_00_a::check_iplevel_settings" line 6) invoked from within "::hw_opb_epc_v1_00_a::check_iplevel_settings 151396184" Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...ERROR:MDT - platgen failed with errors!

    Please help. cus I am totally stuck.

    Kind Regards

    DB:2.63:Edk 9.1 Error 39


    The error just says

    The parameter C_PRH0_WRN_WIDTH must be less than C_PRH0_WR_CYCLE in your epc peripheral.

    Check these two parameters in your MHS file and read the datasheet of this core.

    You can open a webcase if you can't find the problem.

  • RELEVANCY SCORE 2.63

    DB:2.63:Edk 9.2i Sp2 Libgen Fails To Compile Libraries For Xc4vfx20ff672 Part zj


    I recently upgraded from EDK 9.1 to EDK 9.2, I installed the latest service packs for both EDK 9.2i and ISE 9.2i. Now I get the following message when I create a design in the EDK:libgen -mhs system.mhs -p xc4vfx20ff672-10 system.msslibgenXilinx EDK 9.2.02 Build EDK_Jm_SP2.3Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.ERROR:MDT - Invalid target device 'xc4vfx20'make: *** [ppc405_0/lib/libxil.a] Error 2Done!I've found a work around by using the following at an EDK shell:libgen -mhs system.mhs -p virtex4 system.mssThis allows me to generate the libraries for the PPC. But when I open the SDK and try to build my apps, it fails with something similar:make all libgen -mhs C:/projects/xilinx/test/system.mhs -xmpdir C:/projects/xilinx/test \-p xc4vfx20ff672-10 -pe ppc405_0 -od C:/projects/xilinx/test/SDK_projects/ppc405_0_sw_platform \-log C:/projects/xilinx/test/SDK_projects/ppc405_0_sw_platform/libgen.log C:/projects/xilinx/test/SDK_projects/ppc405_0_sw_platform/system.msslibgenXilinx EDK 9.2.02 Build EDK_Jm_SP2.3Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.ERROR:MDT - Invalid target device 'xc4vfx20'make: *** [C:/projects/xilinx/test/SDK_projects/ppc405_0_sw_platform/ppc405_0/lib/libxil.a] Error 2Build complete for project testHas anyone else seen this? Is there a work around? I can't seem to find any posts that refer to this problem.

    DB:2.63:Edk 9.2i Sp2 Libgen Fails To Compile Libraries For Xc4vfx20ff672 Part zj

    Yes, I just realized the ISE Webpack doesn't include support for this part. Thanks for the response.

  • RELEVANCY SCORE 2.62

    DB:2.62:Edk Elfcheck Failed! xk


    Hi everybody!I have downloaded the new ISE and EDK 11 and updated them to 11.3.I have noticed some changes in the way software projects are managed in SDK.My problem is the following: I have built my hardware platform succesfully (its a very simple one with just a couple of peripherals). The I export my hardware design to SDK.Once in SDK I create a software platform and after that a managed make c application project. I add my code and create the linker script. I get this error message one time after the other************** Validating ELF File **************Validating ELF Section Addresses with Hardware Address Map...elfcheck -noheader -hw /home/jcgcecilia/Xilinx/projects/EDK/multiplier_test/SDK/SDK_Export/hw/system.xml -pe microblaze_0 mult.elfERROR:EDK:3165 - elfcheck failed!The following sections did not fit into Processor memory: Section .vectors.hw_exception (0x20 - 0x27) Section .vectors.interrupt (0x10 - 0x17) Section .vectors.sw_exception (0x8 - 0xF) Section .vectors.reset (0x0 - 0x7)

    Try using the linker script generation tools to generate an ELF that mapscorrectly to your hardware design.make: *** [mult.elf] Error 2The thing is I can build and download to the FPGA he same project if a create the project i Software Projects inside XPS.I have tried several things without succes. I have googled it and nothing.Any suggestion??Thnaks in advanced

    JC

    DB:2.62:Edk Elfcheck Failed! xk


    In my case, I've increased the size of dlmb_cntrl and ilmb_ctrl from 16K to 64K and the error was resolved.

    -Maaz

  • RELEVANCY SCORE 2.62

    DB:2.62:Edk 10.1 Gui Error j7



    I find a method to recover from edk 10.1 gui error______remove __xps\system.gui.







    Solved!
    Go to Solution.

    DB:2.62:Edk 10.1 Gui Error j7


    I use this method many times whengui erroroccurs as openningan project just run well a moment ago.

    I don't know why gui errors occur, this makes me can't open my project. but after remove the file. I can open my project again,and it work well.

    in system.gui, I think it's some gui parameters.

  • RELEVANCY SCORE 2.62

    DB:2.62:Problem On Working With Edk ap



    hi,

    i have xilinx ISE 9.2i and EDK 9.1i software. i installed both in my system in different location i.e for ISE(C:\program files\Xilinx ISE9.2i) and for EDK(C:\program files\EDK). i successfully installed both. I can create the "system.xmp" file using ISE. then the EDK console will be opened. but whenever i am trying to work with EDK . It shows the following error. The error msg is
    "ERROR:PersonalityModule:7- Unable to open xilinx data file for vendor/device Module "qrvirtex2". Please make sure that it has been correctly installed before continuing."
    and automatically closed the EDK console.

    i cant solve this problem and alsocant use the EDK softyware. if anyone know the solution for this pls help me..

    ​ thankyou.
    with regards,
    albin viju.

    DB:2.62:Problem On Working With Edk ap

    I've been told by a few sources that we're not supposed to mix ISE and EDK revisions.

  • RELEVANCY SCORE 2.61

    DB:2.61:Error Building For The Ml507 With Edk 10.1 k8


    i’m using edk 10.1.02(nt) – edk_k_sp2.5+0 version and i’m trying to go through the online tutorial (http://www.xilinx.com/products/boards/ml507/files/ml507_bsb_design_ppc440.zip) and i keep getting the following error when trying to “generate libraries and bsps”:At Local date and time: Fri Aug 15 12:19:29 2008 make -f ml507_bsb_system.make libs started...*********************************************Creating software libraries...*********************************************libgen -mhs ml507_bsb_system.mhs -p xc5vfx70tff1136-1 ml507_bsb_system.mss libgen Xilinx EDK 10.1.02 Build EDK_K_SP2.5 Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.ERROR: MDT - Invalid target speed '-1'make: *** [ppc440_0/lib/libxil.a] Error 2 Done!any ideas what could be wrong?

    DB:2.61:Error Building For The Ml507 With Edk 10.1 k8

    I'm having the same error after a reinstall. I am using EDK 10.1 SP3 and ISE Foundation 10.1 SP3

  • RELEVANCY SCORE 2.61

    DB:2.61:Error :When I Download Bit Stream In Xps 1j



    Hello

    I have spartan 3a 3400 and everything go o.k. but when I wanted to download bit stream from device configuration

    this error appeared:

    Error:

    cable connection faild

    cable autodetection failed

    make: *** [download] Error 1

    I used EDK 12.1

    windows 7

    and I connect serial cable (RS232) because I want to see the result in hyperterminal

    Please,

    Tell me , what should I do to overcom this problem.

    Thanks in advance

    Regards

    Adam

    DB:2.61:Error :When I Download Bit Stream In Xps 1j

    This error generally occurs when the it doesnot find the JTAG chain.Please check the following :1. Power supply .2. Jumper settings of the board in JTAG mode.3. Cable connectivity.

  • RELEVANCY SCORE 2.61

    DB:2.61:Sp605 Hardware Tutorial Error jx



    Good afternoon,

    I recently purchased a sp605 embedded kit and I am trying to follow the hardware tutorial (UG669) however I get the errors above when I try to generate the Programming File as described on page 21 (figure 12).

    What am I doing wrong?

    Thank you!

    Platgen Messages - Errors, Warnings, and Infos

    New

    ERROR
    EDK:3900 - issued from TCL procedure "check_rdy_tout" line 54 axi_epc_0 (axi_epc) - Invalid axi_epc_0 parameter: C_PRH0_RDY_TOUT must be greater than 0. The C_PRH0_RDY_TOUT is either set to 0 or it is not specified in the MHS file

    ERROR
    EDK:4125 - IPNAME: axi_epc, INSTANCE: axi_epc_0, PARAMETER: C_PRH0_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

    ERROR
    EDK:4125 - IPNAME: axi_epc, INSTANCE: axi_epc_0, PARAMETER: C_PRH0_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

    ERROR
    EDK:4125 - IPNAME: axi_epc, INSTANCE: axi_epc_0, PARAMETER: C_PRH0_RDY_TOUT - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

    ERROR
    EDK:4125 - IPNAME: axi_epc, INSTANCE: axi_epc_0, PARAMETER: C_PRH0_RDY_WIDTH - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS.

    ERROR
    EDK:440 - platgen failed with errors!

    WARNING
    EDK:4123 - IPNAME: axi_s6_ddrx, INSTANCE: DDR3_SDRAM, PARAMETER: C_S2_AXI_DATA_WIDTH - ASSIGNMENT=CONSTANT is defined in the MPD. Its value should not be overwritten in the MHS.

    WARNING
    EDK:2137 - Peripheral axi_epc_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.

    INFO
    EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ICACHE_USE_FSL value to 0 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_20_b\data\microblaze_v2_1_0.mpd line 334

    INFO
    EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_DCACHE_USE_FSL value to 0 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_20_b\data\microblaze_v2_1_0.mpd line 364

    INFO
    EDK:4130 - IPNAME: axi_s6_ddrx, INSTANCE:DDR3_SDRAM - tcl is overriding PARAMETER C_SYS_RST_PRESENT value to 1 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_05_a\data\axi_s6_ddrx_v2_1_0.mpd line 237

    INFO
    EDK:4130 - IPNAME: axi_interconnect, INSTANCE:AXI_MM - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_05_a\data\axi_interconnect_v2_1_0.mpd line 78

    INFO
    EDK:4130 - IPNAME: axi_interconnect, INSTANCE:AXI_DMA_SG - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_05_a\data\axi_interconnect_v2_1_0.mpd line 78

    INFO
    EDK:4130 - IPNAME: axi_interconnect, INSTANCE:AXI_DMA_MM - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_05_a\data\axi_interconnect_v2_1_0.mpd line 78

    INFO
    EDK:4130 - IPNAME: axi_interconnect, INSTANCE:AXI_Lite - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_05_a\data\axi_interconnect_v2_1_0.mpd line 78

    INFO
    EDK:4130 - IPNAME: axi_intc, INSTANCE:Interrupt_Cntlr - tcl is overriding PARAMETER C_NUM_INTR_INPUTS value to 8 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 80

    INFO
    EDK:740 - Cannot determine the input clock associated with port : LocalMemory_Cntlr_I:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it.

    INFO
    EDK:740 - Cannot determine the input clock associated with port : LocalMemory_Cntlr_D:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it.

    INFO
    EDK:1039 - Did not update the value for parameter: axi_epc_0:C_PRH_CLK_PERIOD_PS. Top-level frequency could not be propagated to this IP. Please make sure that you have specified the frequency of the top-level clock port, and that the clocks are properly connected.

    INFO
    EDK:4130 - IPNAME: lmb_v10, INSTANCE:ilmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data\lmb_v10_v2_1_0.mpd line 80

    INFO
    EDK:4130 - IPNAME: lmb_v10, INSTANCE:dlmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data\lmb_v10_v2_1_0.mpd line 80

    INFO
    EDK:4130 - IPNAME: bram_block, INSTANCE:lmb_bram - tool is overriding PARAMETER C_MEMSIZE value to 0x10000 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 76

    INFO
    EDK:4130 - IPNAME: bram_block, INSTANCE:axi_bram_0 - tool is overriding PARAMETER C_MEMSIZE value to 0x10000 - D:\Xilinx\13.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 76

    DB:2.61:Sp605 Hardware Tutorial Error jx


    Hi,

    Refer tohttp://www.xilinx.com/support/documentation/ip_documentation/axi_epc/v1_00_a/ds809_axi_epc.pdf

    Reference design to configure EPC,http://www.xilinx.com/support/documentation/application_notes/xapp925.pdf

    --Hem




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.60

    DB:2.60:Opensparct1 On Virtex-7 zm


    Hi,

    I am trying to implement OpenSPARCT1 on Xilinx Virtex-7(VC707 XC7VX485T-2FFG1761CES Evaluation Board), single core and multi core. I first tried the EDK project on Virtex-5 and now I want to check feasibility of implementation of the same on Virtex-7. But I am facing a few problems as below:

    1. Generating NGC netlist for Virtex-7 - For rxil command, the OpenSPARCT1 package does not contain the .xst file for my Virtex-7 device. How can I create one or modify the others for my FPGA? Also I tried creating a project on ISE 13.4 and added a copy of all the files mentioned in /design/sys/iop/sparc/xst/sparc.flist but the synthesis is not running due to many missing files and unrecognized modules.
    2. I earlier implemented the EDK project on Xilinx EDK 10.1. How can I make it run using Xilinx EDK 13.4? Previously it showed the error - ERROR:EDK:3548 - Revup to 13.4 failed
    ERROR:EDK:3413 - Error(s) were encountered while updating your project.

    Any inputs for solutions to the above problems would be highly appreciated.

    Thanks
    pk21

    DB:2.60:Opensparct1 On Virtex-7 zm

    Hi,

    I found a solution to my problem. I created a .xst file for virtex-7 device by copying device parameters given in a random ISE and I was able to generate the bit file for single-core 4-thread. It uses hardly 18 LUT resources.

    But still the EDK problem persists, if anyone has a solution, please contribute.

    Also has anybody tried to implement a dual-core on single FPGA? I am trying to generate bit-file for dual core but I am not able to find options to do so. Please help!!

    Thanks in advance

  • RELEVANCY SCORE 2.60

    DB:2.60:Error:Edk:1278 Failed To Create Directory When Executing Libgen From Command Prompt 7f



    Version: Xilinx ISE Design Suite 13.2

    OS: Windows 7

    I was be able to build the board support package using SDK tool, but when I executed the same command on the Xilinx ISE Command Prompt (either 32-bit or 64-bit version), I received the following errors.

    Is there a workaround to fix this? I'm trying to automate our build process using script.

    make -k alllibgen -hw ../my_up_hw_platform/system.xml\ \ -pe microblaze_0 \ -log libgen.log \ system.msslibgenXilinx EDK 13.2 Build EDK_O.61xdCopyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../my_up_hw_platform/system.xml -pe microblaze_0 -loglibgen.log system.mss

    Staging source files.ERROR:EDK:1278 - Failed to create directory C:\Users\cjs142.DS\My Documents\my_project\workspace\standalone_bsp_1\microblaze_0\libsrc\standalone_v3_01_a\src\.

    ERROR:EDK:1278 - Failed to create directory C:\Users\cjs142.DS\My Documents\my_project\workspace\standalone_bsp_1\microblaze_0\libsrc\common_v1_00_a\src\.

    ERROR:EDK:3419 - Error(s) while staging sources.make: *** [microblaze_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.

    -------------------------------

    Output from SDK's console:

    make -k all libgen -hw ../my_up_hw_platform/system.xml\ \ -pe microblaze_0 \ -log libgen.log \ system.msslibgenXilinx EDK 13.2 Build EDK_O.61xdCopyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../my_up_hw_platform/system.xml -pe microblaze_0 -loglibgen.log system.mss

    Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'."Compiling common""Compiling standalone";"Compiling spi""Compiling hwicap""Compiling uartlite""Compiling bram""Compiling cpu"Running execs_generate.'Finished building libraries'







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.59

    DB:2.59:Error:Ngdbuild:989 - Failed To Process Bmm Information Edkbmmfile.Bmm xz



    Hello, i m working on the latest version of ISE/EDK 10.1.02.

    I ve a problem to make a hybrid design. I explain:

    1- I ve created a custom circuit (1)using ISE,data came to (1) form an external circuit, circuit (1) performs DSP computing and store result in a dual port RAM, please note that DSP cores and the dual port ram are all on the same circuit (1).

    2- Using EDK i ve created an embedded system with a CPU Microblaze and with double LMB controllerone is connected to a RAM andi made externalpins with the second one in order to make a pin to pin connection with the dual_port_ram in circuit (1).

    I ve imported the embedded system *.xmp file to ISE to connect circuit(1) to the *.xmp file

    The syntesize processworks with no probelm, but when it comes to translate

    i have this error,

    ERROR:NgdBuild:989 - Failed to process BMM information edkBmmFile.bmm

    I searched a lot for this error, but i hv'nt found any answer.

    I appreciate every replythank you

    DB:2.59:Error:Ngdbuild:989 - Failed To Process Bmm Information Edkbmmfile.Bmm xz


    Hello,

    Actually, time went by and I found another way to solve the problem:

    - Failed to process BMM information edkBmmFile.bmm

    I don't need anymore to import the NGC file only as I mentionned on my last posting.

    Here is what happens and what you could do when you get this error:

    -You have your ISE project that instanciates a XMP system,

    -you import your .XMP file in ISE

    -Normally the Synthesize step should work fine but the Translate process must fail with "Failed to process BMM information edkBmmFile.bmm"

    -Go to your project directory and check that a file named "edkBmmFile.bmm" has been created

    -Then in your ISE project you have to remove the XMP project, click right - Remove

    -Now you add the file named "edkBmmFile.bmm" in your ISE project: click right - Add source

    -This file is just enough to add your XMP system in ISE, you don't need to reimportthe .XMP file anymore. This file actually is linked to your project and describes too the hierarchy to follow to initiate the BRAM. It is this hierarchy description that makes your design fails. Indeed,

    XMP creates this edkBmmFile.bmm assuming that the XMP system is at top level. You can open theBMM filein ISE and you are going to see the hierarchy as "microblaze_i/bram_0".

    -You have to change the "edkBmmFile.bmm" contents in order to match your design hierarchy: for example I had a top level above the microblaze subsystem and I had to write:

    "uut/microblaze_i/bram_0".

    -Then you relaunch the Translate process and it should work this time.

    Please tell me it helped you.

    ydohi,every time you change something in XPS, you have to click on Generate netlist = it creates the NGC files in XPS project. Then you come back to ISE and you follow

    all the steps again:

    -importing .xmp in ISE

    -launch translate tocreate .edkBmmFile.bmm file

    -remove the .xmp project and add the .bmm file

    -and so on...

    Pierre

  • RELEVANCY SCORE 2.59

    DB:2.59:Sdk Linker Fails jx



    Hi, I am using EDK 12.2 with SDK. I have a problem with the linker. I get the following error message:

    /cygdrive/c/Xilinx/12.2/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: read in flex scanner failed

    collect2: ld returned 1 exit status

    make: *** [costello_probe_fw_project.elf] Error 1

    The command that generates this error is the following:

    mb-gcc -Wl,-T -Wl,/cygdrive/z/projects/codesign/costello/0928_st​b_fproc/src/probes/edk_probe_core/SDK/SDK_Workspac​e_35/costello_probe_fw_project/src/firmware_costel​lo -L../../costello_probe_fw_project_bsp_0/uBlaze1/li​b -mxl-barrel-shift -mcpu=v7.30.b -mno-xl-soft-mul -o"costello_probe_fw_project.elf" ./src/fw_freeze_black/video_detection_window.o ./src/fw_freeze_black/video_process.o ./src/fw_freeze_black/video_window_control.o ./src/firmware_costello/costello_input.o ./src/firmware_costello/costello_main.o ./src/firmware_costello/costello_output.o

    If anyone knows how to solve that problem, I would be gratefull.

    Thank you,

    Simon Martineau







    Solved!
    Go to Solution.

    DB:2.59:Sdk Linker Fails jx


    Look at the build settings for your project, then under the Tool Settings tab, then linker item, then Linker Script.

    I found that to be wrong and by fixing it to point to ../src/lscript.ld everything compiles.

    Paul

  • RELEVANCY SCORE 2.59

    DB:2.59:Help On Edk Simulation fp



    Hi,

    I'm tyring simulation with modelsim in an edk design, belowing is my error message:

    ----- Creating Lib ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vlib workmake[1]: 离开目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”----- Running VLOG ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vlog -timescale "1 ns / 1 ps" -incr \ -work work +define+SIM ../../behavioral/sbox.v ../../bench/glbl.v ../../bench/test_sbox.vModel Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009-- Compiling module sbox-- Compiling module glbl-- Compiling module test_sbox

    Top level modules: glbl test_sboxmake[1]: 离开目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”

    ----- Running VSIM ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vsim -c -L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L secureip -L microblaze_v7_30_b -L edk -voptargs=+acc -do sim.do test_sbox glbl -wlf test_sbox.wlfReading D:/modeltech_6.5/tcl/vsim/pref.tcl

    # 6.5

    # vsim -L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L secureip -L microblaze_v7_30_b -L edk -do sim.do -c -voptargs=+acc -wlf test_sbox.wlf test_sbox glbl# ** Note: (vsim-3812) Design is being optimized...# ** Error: ../../behavioral/sbox.v(525): Module 'microblaze_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(626): Module 'mb_plb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(649): Module 'ilmb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(672): Module 'dlmb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(693): Module 'dlmb_cntlr_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(714): Module 'ilmb_cntlr_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(732): Module 'lmb_bram_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(785): Module 'xps_bram_if_cntlr_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(803): Module 'xps_bram_if_cntlr_1_bram_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(852): Module 'rs232_uart_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(905): Module 'gpio_tp_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(980): Module 'ndma_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1042): Module 'alg_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1095): Module 'xps_timer_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1124): Module 'clock_generator_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1277): Module 'mdm_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1301): Module 'proc_sys_reset_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1349): Module 'xps_intc_0_wrapper' is not defined.# Optimization failed# Error loading design

    Can anybody help me out?

    thanks,

    Zhiyong

    DB:2.59:Help On Edk Simulation fp


    Hi,

    I'm tyring simulation with modelsim in an edk design, belowing is my error message:

    ----- Creating Lib ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vlib workmake[1]: 离开目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”----- Running VLOG ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vlog -timescale "1 ns / 1 ps" -incr \ -work work +define+SIM ../../behavioral/sbox.v ../../bench/glbl.v ../../bench/test_sbox.vModel Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009-- Compiling module sbox-- Compiling module glbl-- Compiling module test_sbox

    Top level modules: glbl test_sboxmake[1]: 离开目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”

    ----- Running VSIM ... ----------make[1]: 进入目录“/cygdrive/e/work/mywork/mdv/repo/SBOX/fpga3/s​imulation/script/test_sbox”vsim -c -L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L secureip -L microblaze_v7_30_b -L edk -voptargs=+acc -do sim.do test_sbox glbl -wlf test_sbox.wlfReading D:/modeltech_6.5/tcl/vsim/pref.tcl

    # 6.5

    # vsim -L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L secureip -L microblaze_v7_30_b -L edk -do sim.do -c -voptargs=+acc -wlf test_sbox.wlf test_sbox glbl# ** Note: (vsim-3812) Design is being optimized...# ** Error: ../../behavioral/sbox.v(525): Module 'microblaze_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(626): Module 'mb_plb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(649): Module 'ilmb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(672): Module 'dlmb_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(693): Module 'dlmb_cntlr_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(714): Module 'ilmb_cntlr_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(732): Module 'lmb_bram_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(785): Module 'xps_bram_if_cntlr_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(803): Module 'xps_bram_if_cntlr_1_bram_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(852): Module 'rs232_uart_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(905): Module 'gpio_tp_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(980): Module 'ndma_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1042): Module 'alg_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1095): Module 'xps_timer_1_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1124): Module 'clock_generator_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1277): Module 'mdm_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1301): Module 'proc_sys_reset_0_wrapper' is not defined.# ** Error: ../../behavioral/sbox.v(1349): Module 'xps_intc_0_wrapper' is not defined.# Optimization failed# Error loading design

    Can anybody help me out?

    thanks,

    Zhiyong

  • RELEVANCY SCORE 2.59

    DB:2.59:Virtex-6 With Microblaze cx



    Hi.

    I designed PCB for Virtex-6(XC6VLX240T), and i'd like to use microblaze on that.

    We pass until downloading bit file with impact, however EDK shows me errors like an attachment.

    Error:ERROR:EDK:1304 - Failed to load XMD option file: etc/xmd_microblaze_0.opt

    Error:ERROR:EDK:2970 -

    ML605 doesn't make that error but the board which I designed.

    What was my misstake? Could someone help me please..

    Thanks










    Attachments:




    DB:2.59:Virtex-6 With Microblaze cx


    That error happens if the Microblaze does not receive a clock. Things to check:

    * Is your oscillator outputting a proper signal ?

    * Is the signal from the oscillator reaching the FPGA ?

    This can be tested by writing some test RTL to take the clock signal and use it to toggle another pin that can be externally observed (LED driving pin etc)

    Stephen EcobSilicon On InspirationSydney Australiawww.sioi.com.auSpartan 6 LX75 with 2GB DDR3 DIMM for $375:http://www.sioi.com.au/shop/product_info.php/cPath​/24/products_id/56

  • RELEVANCY SCORE 2.59

    DB:2.59:Minor Version Mismatch Vmnix Errors Started fk



    I started to get this error yesterday. Couldn't find anything in the forums. We didn't make any changes on this blade.

    Apr 3 09:06:43 blade14 vmkernel: 42:19:10:41.862 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:52:50 blade14 vmkernel: 43:17:56:48.884 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:52:50 blade14 vmkernel: 43:17:56:48.884 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:52:50 blade14 vmkernel: 43:17:56:48.994 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:52:50 blade14 vmkernel: 43:17:56:48.995 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:56:00 blade14 vmkernel: 43:17:59:58.478 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:56:00 blade14 vmkernel: 43:17:59:58.478 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:56:00 blade14 vmkernel: 43:17:59:58.480 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    Apr 4 07:56:00 blade14 vmkernel: 43:17:59:58.480 cpu0)VMNIX: WARNING: Mod: 369: Minor version mismatch vmnix (0x1c0001), vmware-ccagent (0x1c0000)

    DB:2.59:Minor Version Mismatch Vmnix Errors Started fk


    One more thing, I wanted to add the error:

    WARNING: Mod: 376: Minor version mismatch vmnix (0x1c0001), vpxa (0x1c0000)

    As you see, this error doesn't point to the agent, but rather vmnix...

  • RELEVANCY SCORE 2.59

    DB:2.59:Unable To Launch Software Debugger In Edk12.2 z8



    Hi,

    I need to debugmy software project running on Microblaze processor in EDK. I tried to launch software debugger in EDK 12.2 but it failed to open. I managed to capture the debugger error message before termination which is attached along with this message. The message says that EDK can'tfind the GUI Tcl library in the following directory....

    It would be grateful if anyone could help. Thank you.










    Attachments:




    DB:2.59:Unable To Launch Software Debugger In Edk12.2 z8


    Hi,

    I need to debugmy software project running on Microblaze processor in EDK. I tried to launch software debugger in EDK 12.2 but it failed to open. I managed to capture the debugger error message before termination which is attached along with this message. The message says that EDK can'tfind the GUI Tcl library in the following directory....

    It would be grateful if anyone could help. Thank you.










    Attachments:




  • RELEVANCY SCORE 2.59

    DB:2.59:Help Regarding Compact Flash Of Virtex2 c1



    hi...

    i am currently working on virtex2 pro development board.
    and i want to use my compact flash drive as a data storage device. i
    first initialize the device using XSysAce_Initialize() then i tried the
    XSysAce_SelfTest() which failed and also the RED error led is on..what
    do i have to do to make it work for storing data of files ?

    i m working on EDK 10.1

    DB:2.59:Help Regarding Compact Flash Of Virtex2 c1


    hi...

    i am currently working on virtex2 pro development board.
    and i want to use my compact flash drive as a data storage device. i
    first initialize the device using XSysAce_Initialize() then i tried the
    XSysAce_SelfTest() which failed and also the RED error led is on..what
    do i have to do to make it work for storing data of files ?

    i m working on EDK 10.1

  • RELEVANCY SCORE 2.57

    DB:2.57:Ise/Edk Node Locked License Failed To Built Bitstream d8



    I have purchased a Node Locaked License for ISE/EDK and installed sucessfully(saw C:\.Xilinx\Xilinx.lic).

    But EDK generated following error message when I tried to built bitstream.

    It seems the license didn't work because EDK thought it is WebPack or tried to get floating license.

    How to fix this issue?

    Thanks.

    JY

    #----------------------------------------------## Starting program map# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf #----------------------------------------------#Release 14.6 - Map P.68d (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.PMSPEC -- Overriding Xilinx fileC:/Xilinx/14.6/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local fileC:/Xilinx/14.6/ISE_DS/ISE/data/Xdh_PrimTypeLib.xdaUsing target part "6vlx240tff1156-1".vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvINFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.INFO:Security:60 - The XILINXD_LICENSE_FILE environment variable is set to'C:\.Xilinx\Xilinx.lic'.INFO:Security:62 - The LM_LICENSE_FILE environment variable is set to'C:\.Xilinx\Xilinx.lic'.INFO:Security:68 - For more information or for assistance in obtaining a license, please run the Xilinx License Configuration Manager (xlcm or "Manage Xilinx Licenses".)INFO:Security:68a - user is user, on host name.WARNING:Security:9b - No 'ISE' feature version 2013.06 was available for part'xc6vlx240t'.ERROR:Security:12 - No 'xc6vlx240t' feature version 2013.06 was available (-15), so 'WebPack' may not be used.----------------------------------------------------------------------Cannot connect to license server system. The license server manager (lmgrd) has not been started yet, the wrong port@host or license file is being used, or the port or hostname in the license file has been changed.Feature: ISEServer name: localhostLicense path: C:\.Xilinx\Xilinx.lic;C:\Xilinx\14.6\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.6\ISE_DS\EDK/data/core_licenses\Xilinx.lic;@localhost;FLEXnet Licensing error:-15,570For further information, refer to the FLEXnet Licensing documentation,available at "www.flexerasoftware.com".Cannot connect to license server system. The license server manager (lmgrd) has not been started yet, the wrong port@host or license file is being used, or the port or hostname in the license file has been changed.Feature: xc6vlx240tServer name: localhostLicense path: C:\.Xilinx\Xilinx.lic;C:\Xilinx\14.6\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.6\ISE_DS\EDK/data/core_licenses\Xilinx.lic;@localhost;FLEXnet Licensing error:-15,570For further information, refer to the FLEXnet Licensing documentation,available at "www.flexerasoftware.com".^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ERROR:Map:258 - A problem was encountered attempting to get the license for this architecture.

    Design Summary--------------Number of errors : 1Number of warnings : 0ERROR:Xflow - Program map returned error code 2. Aborting flow execution...make: *** [__xps/system_routed] Error 1Done!

    DB:2.57:Ise/Edk Node Locked License Failed To Built Bitstream d8

    Hi,Yes, you have to get ISE license for running MAP and PAR process.And why do you want to remove the attachments??Thanks,Vinay



    --------------------------------------------------------------------------------------------Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

  • RELEVANCY SCORE 2.57

    DB:2.57:Zedboard Sdk Tutorial - Wont Build. kp



    Trying to bulid the attached tutorial for the Zeboard. Using version 14.4 tools. The SDK can't seem to find th libraries.

    I've tried versions 14.2, 14.4 and 14.6.

    Is this a license issue? I should have all full licenses.

    make -k all libgen -hw ../system_hw_platform/system.xml\ \ -pe ps7_cortexa9_0 \ -log libgen.log \ system.msslibgenXilinx EDK 14.4 Build EDK_P.49dCopyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../system_hw_platform/system.xml -pe ps7_cortexa9_0-log libgen.log system.mss

    Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling xadc"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling standalone"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -march=armv7-a -mfloat-abi=soft -mfpu=neon -I./. -I../../../include _exit.c _open.c _sbrk.c abort.c close.c errno.c fcntl.c fstat.c getpid.c inbyte.c isatty.c kill.c lseek.c open.c outbyte.c print.c putnum.c read.c sbrk.c sleep.c smc.c uart.c unlink.c usleep.c vectors.c write.c xil_assert.c xil_cache.c xil_exception.c xil_io.c xil_mmu.c xil_printf.c xil_testcache.c xil_testio.c xil_testmem.c xl2cc_counter.c xpm_counter.c xtime_l.c asm_vectors.S boot.S cpu_init.S translation_table.s xil-crt0.S, ...) failed."Compiling devcfg"make (e=2): The system cannot find the file specified."Compiling dmaps"

    make[1]: *** [standalone_libs] Error 2make[1]: Target `libs' not remade because of errors.process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scugic"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scutimer"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scuwdt"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling uartps"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.










    Attachments:







    Lab02 -Hello_World_14_2_2.pdf ‏1856 KB

    DB:2.57:Zedboard Sdk Tutorial - Wont Build. kp


    Trying to bulid the attached tutorial for the Zeboard. Using version 14.4 tools. The SDK can't seem to find th libraries.

    I've tried versions 14.2, 14.4 and 14.6.

    Is this a license issue? I should have all full licenses.

    make -k all libgen -hw ../system_hw_platform/system.xml\ \ -pe ps7_cortexa9_0 \ -log libgen.log \ system.msslibgenXilinx EDK 14.4 Build EDK_P.49dCopyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../system_hw_platform/system.xml -pe ps7_cortexa9_0-log libgen.log system.mss

    Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling xadc"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling standalone"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -march=armv7-a -mfloat-abi=soft -mfpu=neon -I./. -I../../../include _exit.c _open.c _sbrk.c abort.c close.c errno.c fcntl.c fstat.c getpid.c inbyte.c isatty.c kill.c lseek.c open.c outbyte.c print.c putnum.c read.c sbrk.c sleep.c smc.c uart.c unlink.c usleep.c vectors.c write.c xil_assert.c xil_cache.c xil_exception.c xil_io.c xil_mmu.c xil_printf.c xil_testcache.c xil_testio.c xil_testmem.c xl2cc_counter.c xpm_counter.c xtime_l.c asm_vectors.S boot.S cpu_init.S translation_table.s xil-crt0.S, ...) failed."Compiling devcfg"make (e=2): The system cannot find the file specified."Compiling dmaps"

    make[1]: *** [standalone_libs] Error 2make[1]: Target `libs' not remade because of errors.process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scugic"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scutimer"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling scuwdt"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling uartps"process_begin: CreateProcess(NULL, arm-xilinx-eabi-gcc -O2 -c -g -I./. -I../../../include *.c, ...) failed.make (e=2): The system cannot find the file specified.

    make[1]: *** [libs] Error 2"Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.










    Attachments:







    Lab02 -Hello_World_14_2_2.pdf ‏1856 KB

  • RELEVANCY SCORE 2.57

    DB:2.57:Problem When Migrating From Edk10.1 To Edk 11.3 x3


    I have an ML506 Board and I created
    the following design using EDK 10.1

    In this example,I developed project
    using the Base System Builder for custom board (I used custom board option in
    the Base System Builder)which includes three peripherals: the RS232 UART
    and two GPIOs. One GPIO will be used for the DIP switches and the other for
    the LEDs.
    Iworte the C program to read the data from the
    switches and map it to the LEDs.
    The result is that the LEDs should glow when the
    DIP switch is pressed. the design worked aswas expected.ButI encountered
    anerror whenI tried to implement the same project in EDK
    11.3.

    ERROR shown in the EDK
    console:
    Constructing platform-level connectivity ...ERROR:EDK:1526 -
    INST:LEDS PORT:GPIO_IO_O
    CONNECTOR:fpga_0_LEDS_GPIO_IO_O_pin_vslice_0_31_co​ncat -
    E:\EDK_projects\EDK_trial_test\system.mhs line 85 - 32 bit-width connector
    assigned to 8 bit-width portERROR:EDK:1526 - INST:DIP_Switches
    PORT:GPIO_IO_I
    CONNECTOR:fpga_0_DIP_Switches_GPIO_IO_I_pin_vslice​_0_31_concat -
    E:\EDK_projects\EDK_trial_test\system.mhs line 98 - 32 bit-width connector
    assigned to 8 bit-width portCompletion time: 0.00 secondsERROR:EDK:440 -
    platgen failed with errors!make: *** [implementation/system.bmm] Error
    2Done!

    please help us to get over the
    above issue as soon as possible.

    DB:2.57:Problem When Migrating From Edk10.1 To Edk 11.3 x3

    If some has the same problem this might be interessting: http://www.xilinx.com/support/answers/29915.htm

  • RELEVANCY SCORE 2.57

    DB:2.57:Edk Error c3



    Hi All,

    I've copied the iomodule edk peripheral from ISE 14.6 into ISE 13.2. I've imported the iomodule as a custom peripheral.

    When I generate netlist I get this errors:

    ERROR:EDK - xget_value name : a null handle was providedERROR:EDK - C_MASK (IPNAME:lmb_bram_if_cntlr, INSTANCE:dlmb_cntlr) - expected integer but got "" ERROR:EDK:4114 - IPNAME: lmb_bram_if_cntlr, INSTANCE: dlmb_cntlr - error computing override value for C_MASK using tcl - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\lmb_bram_if_cntlr_v3 _00_b\data\lmb_bram_if_cntlr_v2_1_0.mpd line 87 ERROR:EDK - xget_value name : a null handle was providedERROR:EDK - C_MASK (IPNAME:lmb_bram_if_cntlr, INSTANCE:ilmb_cntlr) - expected integer but got "" ERROR:EDK:4114 - IPNAME: lmb_bram_if_cntlr, INSTANCE: ilmb_cntlr - error computing override value for C_MASK using tcl - C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\lmb_bram_if_cntlr_v3 _00_b\data\lmb_bram_if_cntlr_v2_1_0.mpd line 87 ERROR:EDK:440 - platgen failed with errors!make: *** [implementation/microblaze_0_wrapper.ngc] Error 2ERROR:HDLParsers:3384 - "C:/Projects/sia2_v1_3/sia2_v1_2/EDK/system/hdl/io​module_0_wrapper.vhd" Line 241. Size mismatch. String literal "0" is of size 1 but is expected to be of size 32.ERROR:HDLParsers:3384 - "C:/Projects/sia2_v1_3/sia2_v1_2/EDK/system/hdl/io​module_0_wrapper.vhd" Line 244. Size mismatch. String literal "0" is of size 1 but is expected to be of size 32.ERROR:EDK:546 - Aborting XST flow execution!ERROR:EDK:440 - platgen failed with errors!

    The iomodule_0_wrapper.vhd is created incorrectly:

    the iomodule component has the following generic parameter: C_MASK : std_logic_vector(0 to 31);

    but the instance in the generic map has: C_MASK = "0".

    I've tried the default self computing of C_MASK when the iomodule is configured and also put in the C_MASK by hand and it does change the problem.

    I was wondering how to debug this further?

    thanks, serge

    DB:2.57:Edk Error c3


    Hi Serge,

    The iomodule is only available from 14.1 version of ISE/EDK.Using 14.6 core version in 13.2 will leave you with many error as the IP's involved with the iomodule may not have the upadates or interface that are in 14.6 when compared with 13.2.So , i would recommend migrate to 14.x for using iomodule by updating the other IP's in you project.

    Regards,Achutha




    ---------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.56

    DB:2.56:Hdl Parser Errors In User_Logic File ps



    I am trying to create IP named scheduler. I modified user_logic.vhdl file to make it top level module and to interface it with bus.I added sub modules like infer_bram.vhdl and parallel.vhdl in .pao file.And it look like this

    ib proc_common_v1_00_b ld_arith_reg vhdllib proc_common_v1_00_b ld_arith_reg2 vhdllib proc_common_v1_00_b down_counter vhdllib proc_common_v1_00_b inferred_lut4 vhdllib proc_common_v1_00_b or_muxcy vhdllib proc_common_v1_00_b or_gate v

    .

    .

    .

    .

    .

    lib opb_ipif_v2_00_h master_attachment vhdllib opb_ipif_v2_00_h opb_ipif vhdllib scheduler_v1_00_a parallel vhdllib scheduler_v1_00_a infer_bram vhdllib scheduler_v1_00_a user_logic vhdllib scheduler_v1_00_a scheduler vhdl

    ----------------

    So while importing this IP as existing peripheral ,this report comes

    -------------------

    Parsing PAO project file successfully ...Analyzing HDL source files ...Analyzing HDL source files successfully ...HDL language for the peripheral (top level) design unit scheduler is vhdl ...WARNING:MDT - Project file C:\demo2\pcores/scheduler.prj already exists, will be overwrite and removed afterward ...INFO:MDT - Create temparary xst project file: C:\demo2\pcores/scheduler.prjCompiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v1_00_b.Entity or_muxcy compiled.Entity or_muxcy (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v1_00_b.Package proc_common_pkg compiled.WARNING:HDLParsers:3534 - "D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hd l/vhdl/proc_common_pkg.vhd" Line 364. In the function Get_RLOC_Name, not all control paths contain a return statement.WARNING:HDLParsers:3534 - "D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hd l/vhdl/proc_common_pkg.vhd" Line 379. In the function Get_Reg_File_Area, not all control paths contain a return statement.Package body proc_common_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/direct_path_cntr.vhd" in Library proc_common_v1_00_b.Entity direct_path_cntr compiled.Entity direct_path_cntr (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo.vhd" in Library proc_common_v1_00_b.Entity SRL_FIFO compiled.Entity SRL_FIFO (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v1_00_b.Entity srl_fifo2 compiled.Entity srl_fifo2 (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v1_00_b.Entity srl_fifo_rbu compiled.Entity srl_fifo_rbu (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" in Library proc_common_v1_00_b.Entity pselect compiled.Entity pselect (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v1_00_b.Entity ld_arith_reg compiled.Entity ld_arith_reg (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg2.vhd" in Library proc_common_v1_00_b.Entity ld_arith_reg2 compiled.Entity ld_arith_reg2 (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/down_counter.vhd" in Library proc_common_v1_00_b.Entity down_counter compiled.Entity down_counter (Architecture simulation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd" in Library proc_common_v1_00_b.Entity or_gate compiled.Entity or_gate (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/family.vhd" in Library proc_common_v1_00_b.Package family compiled.Package body family compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v1_00_b.Entity inferred_lut4 compiled.Entity inferred_lut4 (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_bit.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter_bit compiled.Entity pf_counter_bit (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder_bit.vhd" in Library opb_ipif_v2_00_h.Entity pf_adder_bit compiled.Entity pf_adder_bit (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter compiled.Entity pf_counter (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter.vhd" in Library opb_ipif_v2_00_h.Entity pf_occ_counter compiled.Entity pf_occ_counter (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ipif_pkg.vhd" in Library ipif_common_v1_00_d.Package ipif_pkg compiled.Package body ipif_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter_top.vhd" in Library opb_ipif_v2_00_h.Entity pf_occ_counter_top compiled.Entity pf_occ_counter_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_top.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter_top compiled.Entity pf_counter_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder.vhd" in Library opb_ipif_v2_00_h.Entity pf_adder compiled.Entity pf_adder (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_dly1_mux.vhd" in Library opb_ipif_v2_00_h.Entity pf_dly1_mux compiled.Entity pf_dly1_mux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg.vhd" in Library ipif_common_v1_00_d.Entity dma_sg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ctrl_reg.vhd" in Library ipif_common_v1_00_d.Entity ctrl_reg compiled.Entity ctrl_reg (Architecture sim) compiled.Entity ctrl_reg_0_to_6 compiled.Entity ctrl_reg_0_to_6 (Architecture sim) compiled.Entity ctrl_reg_0_to_0 compiled.Entity ctrl_reg_0_to_0 (Architecture sim) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/burst_size_calc.vhd" in Library ipif_common_v1_00_d.Entity burst_size_calc compiled.Entity burst_size_calc (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_cmp.vhd" in Library ipif_common_v1_00_d.Package dma_sg_cmp compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_pkg.vhd" in Library ipif_common_v1_00_d.Package dma_sg_pkg compiled.Package body dma_sg_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_wr.vhd" in Library opb_ipif_v2_00_h.Entity ipif_control_wr compiled.Entity ipif_control_wr (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_dp_cntl.vhd" in Library opb_ipif_v2_00_h.Entity wrpfifo_dp_cntl compiled.Entity wrpfifo_dp_cntl (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_dpram_select.vhd" in Library opb_ipif_v2_00_h.Entity pf_dpram_select compiled.Entity pf_dpram_select (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/srl16_fifo.vhd" in Library opb_ipif_v2_00_h.Entity srl16_fifo compiled.Entity srl16_fifo (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_rd.vhd" in Library opb_ipif_v2_00_h.Entity ipif_control_rd compiled.Entity ipif_control_rd (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_dp_cntl.vhd" in Library opb_ipif_v2_00_h.Entity rdpfifo_dp_cntl compiled.Entity rdpfifo_dp_cntl (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_reset.vhd" in Library opb_ipif_v2_00_h.Entity ipif_reset compiled.Entity ipif_reset (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/interrupt_control.vhd" in Library ipif_common_v1_00_d.Entity interrupt_control compiled.Entity interrupt_control (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ipif_steer.vhd" in Library ipif_common_v1_00_d.Entity IPIF_Steer compiled.Entity IPIF_Steer (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_sim.vhd" in Library ipif_common_v1_00_d.Entity dma_sg (Architecture sim) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_dmux.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_dmux compiled.Entity ip2bus_dmux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_srmux compiled.Entity ip2bus_srmux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/addr_load_and_incr.vhd" in Library opb_ipif_v2_00_h.Entity addr_load_and_incr compiled.Entity addr_load_and_incr (Architecture implementation) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/parall​el.vhd" inLibrary scheduler_v1_00_a.Entity parallel compiled.Entity parallel (Architecture imp) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/infer_​bram.vhd"in Library scheduler_v1_00_a.Entity infer_bram compiled.Entity infer_bram (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/master_attachment.vhd" in Library opb_ipif_v2_00_h.Entity master_attachment compiled.Entity master_attachment (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/address_decoder.vhd" in Library opb_ipif_v2_00_h.Entity address_decoder compiled.Entity address_decoder (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux_blk.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_srmux_blk compiled.Entity ip2bus_srmux_blk (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/bus2ip_amux.vhd" in Library opb_ipif_v2_00_h.Entity bus2ip_amux compiled.Entity bus2ip_amux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_dmux_blk.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_dmux_blk compiled.Entity ip2bus_dmux_blk (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/slave_attachment.vhd" in Library opb_ipif_v2_00_h.Entity slave_attachment compiled.Entity slave_attachment (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/reset_control.vhd" in Library opb_ipif_v2_00_h.Entity reset_control compiled.Entity reset_control (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_top.vhd" in Library opb_ipif_v2_00_h.Entity rdpfifo_top compiled.Entity rdpfifo_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_top.vhd" in Library opb_ipif_v2_00_h.Entity wrpfifo_top compiled.Entity wrpfifo_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/opb_ipif.vhd" in Library opb_ipif_v2_00_h.Entity opb_ipif compiled.Entity opb_ipif (Architecture implementation) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd"in Library scheduler_v1_00_a.Entity user_logic compiled.ERROR:HDLParsers:164 - "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd" Line 431. parse error, unexpected FUNCTIONERROR:HDLParsers:164 - "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd" Line 431. parse error, unexpected CLOSEPAR, expecting OPENPAR or TICK or LSQBRACKERROR:MDT - Parse Errors encountered in HDL source WARNING:MDT - Unable to delete temparary project file C:\demo2\pcores\scheduler.prj : 13

    ------------

    where the 431 line in my user_logic file starts from here "function"

    -------------

    function is_encoder_bit_zero(pri_index: integer; e_entry: std_logic_vector(0 to INPUT_BITS-1)) return boolean isbegin if (e_entry(pri_index) = '0') then return true; else return false; end if;end function is_encoder_bit_zero;

    --------------

    what's wrong with it????? can anybody tell me a solution to this problem???

    nasim







    Solved!
    Go to Solution.

    DB:2.56:Hdl Parser Errors In User_Logic File ps

    thanx it worked.I was actually using semiclon instead of comma in port map.

  • RELEVANCY SCORE 2.56

    DB:2.56:Edk Error : 1 Constraint Not Met. p7



    Hi all,

    I'm trying to use a microblaze for the evaluation plateform xupv5-lx110t.

    When creating a new project with EDK 13.4this board doesn't exist.So i select the evaluation board 5ML506 then i generate the bitstream, intil now every thing works but when i change the target toXC5VLX110T i have this error :

    ERROR: 1 constraint not met.

    make: *** [implementation system.bit] erreur 1

    How can i correct this error?

    Best regards.

    DB:2.56:Edk Error : 1 Constraint Not Met. p7


    Hi all,

    I'm trying to use a microblaze for the evaluation plateform xupv5-lx110t.

    When creating a new project with EDK 13.4this board doesn't exist.So i select the evaluation board 5ML506 then i generate the bitstream, intil now every thing works but when i change the target toXC5VLX110T i have this error :

    ERROR: 1 constraint not met.

    make: *** [implementation system.bit] erreur 1

    How can i correct this error?

    Best regards.

  • RELEVANCY SCORE 2.56

    DB:2.56:Edk 13.1 s1



    hello all,

    what can be the solution of the following problem..

    Device ID Code IR Length Part Name1 02610093 6 XC3S50AN2 64288093 10 XC6VSX475TConnection to MDM UART Target Failed. ERROR: Could not detect MDM peripheral onhardware. Please check:1. If FPGA is configured correctly2. MDM Core is instantiated in the design







    Solved!
    Go to Solution.

    DB:2.56:Edk 13.1 s1

    Thanks Stephen, It loooks like EDK does not automatically configures the XMD terminal, and so manual setting is necessary.

  • RELEVANCY SCORE 2.56

    DB:2.56:Error: File "User_Logic.C" Not Found 8k



    Hi,

    I am using the 'Create/Import Peripheral' Wizard in EDK 10.1 to modify slightly a user logic peripheral that I have used successfully in the past; I have modified the .mpd, .prj, and .pao files appropriately to account for my new port definitions, but whenever I try to generate the hardware bitstream, I receive the following error:

    Generating synthesis project file ...ERROR:MDT - File not found in any repository 'dwdmrx_v2_00_a/vpmodel/c/user_logic.c'ERROR:MDT - platgen failed with errors!make: *** [implementation/ppc405_0_wrapper.ngc] Error 2Done!

    My stub logic "user_logic" for my peripheral 'dwdmrx.hdl' is in Verilog; it is not clear to me why EDK looking for a "user_logic.c" driver file in the first place, let alone within a directory 'vpmodel' that does not exist. Has anyone seen this sort of behavior?

    Thanks.

    Matt

    DB:2.56:Error: File "User_Logic.C" Not Found 8k


    Unfortunately I spend the whole morning figuring out what was wrong, and this is the only "same problem"I could find.

    It turns out the problem was in adding the files to the PAO file, I copied the filenames and edited these. Then I get this same error response on these file names.

    It turns out I forgot to change the file extension VHD into the proper type definition VHDL in the PAO file. Apparently VHD is interpreted as VPMODEL... awakward maybe but changing VHD into VHDL solved the problem.

  • RELEVANCY SCORE 2.56

    DB:2.56:Problem In Edk 1c



    Hi All,

    I am new to EDK tool , and I'm facing a problem while generating Libraries and BSP, The console window displays following error.

    "Running include - 'make -s include "COMPILER=powerpc-eabi-gcc""ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440 -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.cp: cannot stat `*.h': No such file or directorymake[1]: *** [include] Error 1cp: cannot stat `*.h': No such file or directorymake[1]: *** [standalone_includes] Error 1cp: cannot stat `*.h': No such file or directorymake[1]: *** [include] Error 1ERROR:EDK:368 - make failed for target "include" ERROR:EDK:1189 - Error(s) while running "make" for processor ppc440_0.cp: cannot stat `*.h': No such file or directorymake[1]: *** [include] Error 1make: *** [ppc440_0/lib/libxil.a] Error 2"

    Can anyone please tell me what could be wrong.

    Regards

    Pooja

    DB:2.56:Problem In Edk 1c


    No, i am just generating libraries and BSP.

  • RELEVANCY SCORE 2.56

    DB:2.56:Edk Error fz


    /cygdrive/d/edk/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: cannot find boot.o
    collect2: ld returned 1 exit status

    make: *** [TestApp_Memory/executable.elf] Error 1

    This error came out when the operating system is converted into linux2.6. I don't know how to solve this problem, thank you for your help.

    DB:2.56:Edk Error fz


    Thank you for your reply. I have seen the solution 17462.htm. But I don't understand "only LibGen should be run to generate the VxWorks BSP" and still don't know the concrete solution. Hoping for your reply.

  • RELEVANCY SCORE 2.56

    DB:2.56:Problems Compiling Simulation Libraries In Xps m8



    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

    DB:2.56:Problems Compiling Simulation Libraries In Xps m8


    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

  • RELEVANCY SCORE 2.56

    DB:2.56:Problem With Edk And Bluecat mj


    Hi,

    I get following error while trying to generate libraries and
    BSPs in EDK

    #--------------------------------------
    ERROR:MDT - linux_bc54 () - Error: Target directory does not
    exist.

    while executing

    "error
    "Error: Target directory does not exist.""

    (procedure
    "::sw_linux_bc54_v1_00_a::linux_drc" line 30)

    invoked from
    within

    "::sw_linux_bc54_v1_00_a::linux_drc 66343224"

    ERROR:MDT - Error while running DRC for processor
    microblaze_0...

    make: *** [microblaze_0/lib/libxil.a] Error 2

    #--------------------------------------

    Is there something I forget when I configured the environment?

    I am using EDK 10.1.03 in windows and BlueCat ME 5.4.3.

    Thanks

    DB:2.56:Problem With Edk And Bluecat mj


    Hi,

    1. the directory path may be incorrect. should be this slash / not \

    or

    2. you need to change the default linux path to linux.ml405 or linux.ml507 in the tcl under the bsp directory

    Regards

    TOM

  • RELEVANCY SCORE 2.56

    DB:2.56:Errors Making Bsp When Following Ug670, Edk 13.1 kz



    Hello,

    I've followed the instructions for the benchmarking demo in "UG670 (v3.0) March 18, 2011: AXI Interface Based ML605/SP605 MicroBlaze Processor Subsystem: Software Tutorial" using EDK 13.1

    But when I make the BSP, I get the following errors:

    make -k all libgen -hw ../hw_platform/system.xml\ -lp C:/sp605_13/Tutorial_Sanbox/SW/benchmark_demo\ -pe microblaze_0 \ -log libgen.log \ system.msslibgenXilinx EDK 13.1 Build EDK_O.40dCopyright (c) 1995-2010 Xilinx, Inc. All rights reserved.Command Line: libgen -hw ../hw_platform/system.xml -lpC:/sp605_13/Tutorial_Sanbox/SW/benchmark_demo -pe microblaze_0 -log libgen.logsystem.mss Staging source files.Running DRCs.Runnning DRC for lwIP library... lwIP can be used with the following EMAC peripherals found in your system:Soft_Ethernet_MACMFS DRC ...Running generate.Little Endian systemMFS generate ...Running post_generate.Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.10.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g -DXILKERNEL_MB_MPU_DISABLE"'.cp -r lwip-1.3.0/src/include/ipv4/lwip ../../../includecp -r lwip-1.3.0/src/include/lwip ../../../includecp -r lwip-1.3.0/src/include/netif ../../../includecp -r contrib/ports/xilinx/include/netif ../../../includecp -r contrib/ports/xilinx/include/arch ../../../includecp -r contrib/ports/xilinx/include/lwipopts.h ../../../includeRunning libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mlittle-endian -mno-xl-soft-mul -mxl-barrel-shift-mxl-pattern-compare -mcpu=v8.10.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g -DXILKERNEL_MB_MPU_DISABLE"'.Compiling standaloneCompiling commonCompiling llfifo/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [arch-libs] Error 258make[2]: Target `libs' not remade because of errors.make[1]: *** [dir_syscall] Error 2/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_arch] Error 258/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_sys] Error 258/usr/bin/sh: -c: line 3: syntax error: unexpected end of filemake[2]: *** [dir_ipc] Error 258make[2]: Target `all' not remade because of errors.make[1]: *** [dir_src] Error 2c:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin\mb-ar.exe: creating ./libsyscall.ac:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin\mb-ar.exe: ./syscall/arch/microblaze/*.o: Invalid argumentmake[1]: *** [rellibs] Error 1make[1]: Target `libs' not remade because of errors.Compiling lwIP with mb-gccCompiling lwip-1.3.0/src/core/init.cCompiling lwip-1.3.0/src/core/mem.cCompiling lwip-1.3.0/src/core/memp.cCompiling lwip-1.3.0/src/core/netif.cCompiling lwip-1.3.0/src/core/pbuf.cCompiling lwip-1.3.0/src/core/raw.cCompiling lwip-1.3.0/src/core/stats.cCompiling lwip-1.3.0/src/core/sys.cCompiling lwip-1.3.0/src/netif/etharp.cCompiling lwip-1.3.0/src/core/ipv4/ip_addr.cCompiling lwip-1.3.0/src/core/ipv4/icmp.cCompiling lwip-1.3.0/src/core/ipv4/inet.cCompiling lwip-1.3.0/src/core/ipv4/inet_chksum.cCompiling lwip-1.3.0/src/core/ipv4/ip.cCompiling lwip-1.3.0/src/core/ipv4/ip_frag.cCompiling lwip-1.3.0/src/core/tcp.cCompiling lwip-1.3.0/src/core/tcp_in.cCompiling lwip-1.3.0/src/core/tcp_out.cCompiling lwip-1.3.0/src/core/udp.cCompiling lwip-1.3.0/src/core/dhcp.cCompiling lwip-1.3.0/src/api/api_lib.cCompiling lwip-1.3.0/src/api/api_msg.cCompiling lwip-1.3.0/src/api/err.cCompiling lwip-1.3.0/src/api/netbuf.cCompiling lwip-1.3.0/src/api/sockets.cCompiling lwip-1.3.0/src/api/tcpip.cCompiling lwIP adapter for Xilinx MAC:Compiling contrib/ports/xilinx/sys_arch_raw.cCompiling contrib/ports/xilinx/netif/xpqueue.cCompiling contrib/ports/xilinx/netif/xadapter.cCompiling contrib/ports/xilinx/netif/xtopology_g.cCompiling contrib/ports/xilinx/sys_arch.cCompiling contrib/ports/xilinx/netif/xaxiemacif_hw.cCompiling contrib/ports/xilinx/netif/xaxiemacif_physpeed.cCompiling contrib/ports/xilinx/netif/xaxiemacif.cCompiling contrib/ports/xilinx/netif/xaxiemacif_dma.cCreating archive liblwip4.aCompiling axicdmaCompiling axidma v3.00aCompiling gpioCompiling uartliteCompiling tmrctrCompiling iicCompiling bramCompiling intcCompiling perf_axiCompiling uartns550Compiling spiCompiling axiethernetCompiling cpuERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [microblaze_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.

    Has anyone else resolved this issue yet? Any tips on debugging this would be greatly appreciated.

    I'm using Windows 7 - 64bit.

    Thank you,

    Kurt







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.55

    DB:2.55:I Can't Add To My Sw Platform The Interrupt Controller? fs



    Hello

    On the Software Platform Settings, when I add an Interrupt Controller (intc), why do I get this errors?

    It seems that when I add the interrupt controller, the software platform will add to the library the file:

    "timer_intr_handler.c" which at the begginning has the following line:

    #include "xintc.h"

    The problem is that this xintc.h wasn't add to the software library XilKernel....

    I'm stuck on this problem, and therefore I can't use the interrupts.

    Anyone has any ideia about this error?

    The Errors:

    make -k clean all rm -rf microblaze_0/code/rm -rf microblaze_0/include/rm -rf microblaze_0/lib/rm -rf microblaze_0/libsrc/rm -f libgen.loglibgen \ -hw C:/VSS/ICC-251/SW-XILINX/hw/ublaze.xml \ -pe microblaze_0 \ -od . \ -lp C:/VSS/ICC-251/SW-XILINX \ -log libgen.log SW_Platform_XILKERNEL.mss libgenXilinx EDK 11.1 Build EDK_L.29.1Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.Command Line: libgen -hw C:/VSS/ICC-251/SW-XILINX/hw/ublaze.xml -pe microblaze_0-od . -lp C:/VSS/ICC-251/SW-XILINX -log libgen.log SW_Platform_XILKERNEL.mss WARNING:EDK:411 - spi - C:\VSS\ICC-251\SW-XILINX\SW_Platform_XILKERNEL\SW_​Platform_XILKERNEL.mss line 64 - deprecated driver!INFO:EDK:1740 - List of peripherals connected to processor instance microblaze_0: - DDR - dlmb_cntlr - iccBridge - ilmb_cntlr - intc - mdm_0 - spi - uartStaging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mno-xl-soft-mul -mxl-pattern-compare -mcpu=v7.20.d -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar""COMPILER_FLAGS=-mno-xl-soft-mul -mxl-pattern-compare -mcpu=v7.20.d -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Compiling standaloneCompiling commonCompiling lldmatimer_intr_handler.c:31:19: error: xintc.h: No such file or directorytimer_intr_handler.c:32: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'sys_intc'make[3]: *** [timer_intr_handler.o] Error 1mb-hw.c:43:19: error: xintc.h: No such file or directorymb-hw.c:54: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'sys_intc'mb-hw.c:84: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'XIntc_ConfigTable'mb-hw.c: In function 'int_system_init':mb-hw.c:143: error: 'sys_intc' undeclared (first use in this function)mb-hw.c:143: error: (Each undeclared identifier is reported only oncemb-hw.c:143: error: for each function it appears in.)mb-hw.c:143: error: 'XPAR_INTC_DEVICE_ID' undeclared (first use in this function)mb-hw.c:150: error: 'XPAR_INTC_BASEADDR' undeclared (first use in this function)mb-hw.c:150: error: 'XIN_SVC_ALL_ISRS_OPTION' undeclared (first use in this function)mb-hw.c:167: error: 'XIN_REAL_MODE' undeclared (first use in this function)make[3]: *** [mb-hw.o] Error 1make[3]: Target `all' not remade because of errors.make[2]: *** [dir_arch] Error 2intr.c:35:19: error: xintc.h: No such file or directoryintr.c:42: error: expected specifier-qualifier-list before 'XInterruptHandler'intr.c:57: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'sys_intc'intr.c: In function 'sys_register_int_handler':intr.c:116: error: 'sys_intc' undeclared (first use in this function)intr.c:116: error: (Each undeclared identifier is reported only onceintr.c:116: error: for each function it appears in.)intr.c:116: error: 'XInterruptHandler' undeclared (first use in this function)intr.c:116: error: expected ')' before 'handler'intr.c: In function 'sys_unregister_int_handler':intr.c:138: error: 'sys_intc' undeclared (first use in this function)intr.c: In function 'sys_enable_interrupt':intr.c:159: error: 'sys_intc' undeclared (first use in this function)intr.c: In function 'sys_disable_interrupt':intr.c:180: error: 'sys_intc' undeclared (first use in this function)intr.c: In function 'sys_acknowledge_interrupt':intr.c:202: error: 'sys_intc' undeclared (first use in this function)make[3]: *** [intr.o] Error 1make[3]: Target `all' not remade because of errors.make[2]: *** [dir_sys] Error 2make[2]: Target `all' not remade because of errors.make[1]: *** [dir_src] Error 2mb-ar: creating ./libsyscall.amb-ar: creating ./libxilkernel.amake[1]: Target `libs' not remade because of errors.Compiling mpmcCompiling uartliteCompiling spiCompiling cpuERROR:EDK:369 - make failed for target "libs" ERROR:EDK:1189 - Error(s) while running "make" for processor microblaze_0.make: *** [microblaze_0/lib/libxil.a] Error 2make: Target `all' not remade because of errors.

    Thanks in advance







    Solved!
    Go to Solution.

    DB:2.55:I Can't Add To My Sw Platform The Interrupt Controller? fs


    THANKS VSIVA!!!! :-D!!!

    That's it!!!!!!!!!!!!!

    Instead of xps_intc_0, as you said, i wrote "intc"....

    And finally XilKernel compiles!!!

    My MSS file has:

    BEGIN DRIVER
    PARAMETER DRIVER_NAME = intc
    PARAMETER DRIVER_VER = 1.11.a
    PARAMETER HW_INSTANCE = intc
    END

    Thank you!!! :-)

    Kudos for you my friend!

  • RELEVANCY SCORE 2.55

    DB:2.55:Error: [Edk 24-166] (Generate_Target): Failed To Execute Xps Script m3



    Hi

    I've done a design in PlanAhead 14.7 and I'm trying to generate the Bitstream. Each time I do I get an error box saying xst.exe has stopped working. If I ignore this I get an Edk 24-166 error message.

    Looking at the tcl command window I can see the following:

    ERROR:EDK:546 - Aborting XST flow execution!

    INFO:EDK:2246 - Refer to

    C:\Xilinx\tutorial\Imageon_step1_2\Imageon_step1_2​.srcs\sources_1\edk\Imageon

    _1_sub_design\synthesis\Imageon_1_sub_design_v_tc_​0_wrapper_xst.srp for

    details

    Running NGCBUILD ...

    INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

    If any constraint needs to be overridden, this should be done by modifying

    the data/Imageon_1_sub_design.ucf file.

    Rebuilding cache ...

    ERROR:EDK:440 - platgen failed with errors!

    make: *** [implementation/Imageon_1_sub_design_v_vid_in_axi4​s_0_wrapper.ngc] Error 2

    ERROR:EDK -

    Error while running "make -f Imageon_1_sub_design.make netlist".

    ERROR: [Edk 24-166] (generate_target): Failed to execute XPS script. Please check for any errors reported by the XPS application in the console: [C:/Xilinx/tutorial/Imageon_step1_2/Imageon_step1_​2.srcs/sources_1/edk/Imageon_1_sub_design/__xps/pa​/_Imageon_1_sub_design_synth.tcl]

    Any idea what causing this?

    DB:2.55:Error: [Edk 24-166] (Generate_Target): Failed To Execute Xps Script m3

    I'm guessing that this just isn't clear enough for people to make a response?

  • RELEVANCY SCORE 2.55

    DB:2.55:Error Computing Override Value For C_Mem_Cas_Latency0 p8


    I've tried to follow the tutorial at http://www.xilinx.com/support/techsup/tutorials/92_MB_Tutorial.pdf for the Spartan 3E Starter kit. The steps of generating the processor were the same aside from the platform and peripherals chosen. I'm unsure why an error is given for a variable that appears to be undefined. Was there a step I missed or was I expected to define this in some way? I know the file it says that it cannot open does exist and contains the parameter mentioned.Below I've pasted the output generated from the XPS tool.============================================Started : "XPS Process: Synthesize XPS Source".Xilinx Platform StudioXilinx EDK 9.2 Build EDK_Jm.16Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.XPS% Evaluating fileZ:\docs\docs\Fall2007\HDL\mbtest\project_navigator\system.setprop.tclArchitecture: spartan3eDevice: xc3s500ePackage: fg320SpeedGrade: -4Hierarchy: ToplevelHierarchy setting in XPS (top) does not match Hierarchy setting in ISE (sub)No changes to be saved in MSS fileNo changes to be saved in XMP fileStarted : "Updating XPS project device settings".Xilinx Platform StudioXilinx EDK 9.2 Build EDK_Jm.16Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.XPS% Evaluating fileZ:\docs\docs\Fall2007\HDL\mbtest\project_navigator\system.setprop.tclCopied E:/EDK/data/xflow/bitgen_spartan3e.ut to etc directoryArchitecture: spartan3eDevice: xc3s500ePackage: fg320SpeedGrade: -4Hierarchy: Sub ModuleSetting ProjNav as implementation tool flow.No changes to be saved in MSS fileSaved project XMP fileNo changes to be saved in MSS fileNo changes to be saved in XMP fileProcess "Updating XPS project device settings" completed successfullyXilinx Platform StudioXilinx EDK 9.2 Build EDK_Jm.16Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.XPS% Evaluating fileZ:\docs\docs\Fall2007\HDL\mbtest\project_navigator\system.synth.tcl****************************************************Creating system netlist for hardware specification..****************************************************platgen -p xc3s500efg320-4 -lang vhdl -toplevel no -ti system_i system.mhsRelease Xilinx EDK 9.2 - platgen EDK_Jm.16Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.Command Line: platgen -p xc3s500efg320-4 -lang vhdl -toplevel no -ti system_isystem.mhs WARNING:MDT - You are using an evaluation version of Xilinx Software. In 55 days, hardware generation in this program will not operate. Software applications can still be generated. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!Parse system.mhs ...Read MPD definitions ...Overriding IP level properties ...INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 164 - tcl is overriding PARAMETER C_ADDR_TAG_BITS value to 0INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 172 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG value to 0INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 135 - tcl is overriding PARAMETER C_MEM_PART_DATA_DEPTH value to 32INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 136 - tcl is overriding PARAMETER C_MEM_PART_DATA_WIDTH value to 16INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 139 - tcl is overriding PARAMETER C_MEM_PART_NUM_COL_BITS value to 10INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 140 - tcl is overriding PARAMETER C_MEM_PART_TRAS value to 42000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 141 - tcl is overriding PARAMETER C_MEM_PART_TRASMAX value to 70000000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 142 - tcl is overriding PARAMETER C_MEM_PART_TRC value to 60000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 143 - tcl is overriding PARAMETER C_MEM_PART_TRCD value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 145 - tcl is overriding PARAMETER C_MEM_PART_TWR value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 146 - tcl is overriding PARAMETER C_MEM_PART_TRP value to 15000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 147 - tcl is overriding PARAMETER C_MEM_PART_TMRD value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 148 - tcl is overriding PARAMETER C_MEM_PART_TRRD value to 12000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 149 - tcl is overriding PARAMETER C_MEM_PART_TRFC value to 72000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 150 - tcl is overriding PARAMETER C_MEM_PART_TREFI value to 7800000INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 155 - tcl is overriding PARAMETER C_MEM_PART_CAS_A_FMAX value to 133INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 156 - tcl is overriding PARAMETER C_MEM_PART_CAS_A value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 157 - tcl is overriding PARAMETER C_MEM_PART_CAS_B_FMAX value to 166INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 158 - tcl is overriding PARAMETER C_MEM_PART_CAS_B value to 2.5Performing IP level DRCs on properties...Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...Address Map for Processor microblaze_0 (0000000000-0x00001fff) dlmb_cntlr dlmb (0000000000-0x00001fff) ilmb_cntlr ilmb (0x81400000-0x8140ffff) LEDs_8Bit mb_plb (0x81420000-0x8142ffff) DIP_Switches_4Bit mb_plb (0x81440000-0x8144ffff) Buttons_4Bit mb_plb (0x84000000-0x8400ffff) RS232_DTE mb_plb (0x84020000-0x8402ffff) RS232_DCE mb_plb (0x84400000-0x8440ffff) debug_module mb_plb (0x89000000-0x89ffffff) FLASH mb_plb (0x8c000000-0x8fffffff) DDR_SDRAM mb_plbCheck platform address map ...INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 203 - tool is overriding PARAMETER C_SPLB0_P2P value to 0Overriding system level properties ...INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 125 - tcl is overriding PARAMETER C_D_PLB value to 1INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 126 - tcl is overriding PARAMETER C_D_OPB value to 0INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 128 - tcl is overriding PARAMETER C_I_PLB value to 1INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze - E:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_00_a\data\microblaze_v2_1 _0.mpd line 129 - tcl is overriding PARAMETER C_I_OPB value to 0INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - E:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 35 - tool is overriding PARAMETER C_PLBV46_NUM_MASTERS value to 2INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - E:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_PLBV46_MID_WIDTH value to 1INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 - E:\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_00_a\data\plb_v46_v2_1_0.mpd line 39 - tool is overriding PARAMETER C_PLBV46_DWIDTH value to 32INFO:MDT - IPNAME:ilmb INSTANCE:lmb_v10 - E:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1INFO:MDT - IPNAME:dlmb INSTANCE:lmb_v10 - E:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1INFO:MDT - IPNAME:dlmb_cntlr INSTANCE:lmb_bram_if_cntlr - E:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\data\lmb_bram _if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK value to 0x80000000INFO:MDT - IPNAME:ilmb_cntlr INSTANCE:lmb_bram_if_cntlr - E:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\data\lmb_bram _if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK value to 0x80000000INFO:MDT - IPNAME:lmb_bram INSTANCE:bram_block - E:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1 _0.mpd line 36 - tool is overriding PARAMETER C_MEMSIZE value to 0x2000INFO:MDT - IPNAME:RS232_DTE INSTANCE:xps_uartlite - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\data\xps_uartlite_ v2_1_0.mpd line 45 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:RS232_DCE INSTANCE:xps_uartlite - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\data\xps_uartlite_ v2_1_0.mpd line 45 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:LEDs_8Bit INSTANCE:xps_gpio - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.m pd line 41 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:DIP_Switches_4Bit INSTANCE:xps_gpio - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.m pd line 41 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:Buttons_4Bit INSTANCE:xps_gpio - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v1_00_a\data\xps_gpio_v2_1_0.m pd line 41 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:FLASH INSTANCE:xps_mch_emc - E:\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v1_00_a\data\xps_mch_emc_v2 _1_0.mpd line 47 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 199 - tool is overriding PARAMETER C_SPLB0_DWIDTH value to 32INFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 201 - tool is overriding PARAMETER C_SPLB0_NUM_MASTERS value to 2ERROR:MDT - issued from TCL procedure "init_control" line 48 C_MEM_CAS_LATENCY0 (mpmc) - File Z:/docs/docs/Fall2007/HDL/mbtest/__xps/DDR_SDRAM_mpmc_ctrl_path_params.v is not found or unable to open for reading.ERROR:MDT - IPNAME:mpmc INSTANCE:DDR_SDRAM - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 163 - error computing override value for C_MEM_CAS_LATENCY0 using tclINFO:MDT - IPNAME:DDR_SDRAM INSTANCE:mpmc - E:\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v3_00_a\data\mpmc_v2_1_0.mpd line 195 - tcl is overriding PARAMETER C_PIM0_SUBTYPE value to PLBINFO:MDT - IPNAME:debug_module INSTANCE:mdm - E:\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 55 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 1INFO:MDT - IPNAME:debug_module INSTANCE:mdm - E:\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_a\data\mdm_v2_1_0.mpd line 56 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2Running system level Update ...Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...INFO: The DDR_SDRAM core has constraints automatically generated by XPS in implementation/ddr_sdram_wrapper/ddr_sdram_wrapper.ucf.It can be overridden by constraints placed in the system.ucf file.ERROR:MDT - platgen failed with errors!make: *** [implementation/microblaze_0_wrapper.ngc] Error 2ERROR:MDT - Error while running "make -f system.make netlist"No changes to be saved in MSS fileNo changes to be saved in XMP fileProcess "XPS Process: Synthesize XPS Source" completed successfullyReading design: system_stub.prj=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "Z:/docs/docs/Fall2007/HDL/mbtest/project_navigator/../hdl/system.vhd" in Library work.ERROR:HDLParsers:3264 - Can't read file "Z:/docs/docs/Fall2007/HDL/mbtest/project_navigator/../hdl/system.vhd": No such file or directory-- Total memory usage is 113164 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)Process "Synthesize" failedMessage Edited by echabot on 03-19-2008 07:00 PM

    DB:2.55:Error Computing Override Value For C_Mem_Cas_Latency0 p8

    I've run into similar problems using EDK 10.1 that was solved by making sure there were no spaces in any of my paths. It is a problem with lazy Java coding by developers.