• RELEVANCY SCORE 3.75

    DB:3.75:Bmd Simulation 1a





    Hi everyone,

    I'm trying to integrate my design with the BMD example design of XAPP1052, but in dma_performance_demo.zip I cannot find any ad hoc simultion testbench. Do I have to use the simulation files of the PIO design? Do they also support dma transfers? Any hint is really appreciated.

    Thanks in advance.

    DB:3.75:Bmd Simulation 1a


    Hi everyone,

    I'm trying to integrate my design with the BMD example design of XAPP1052, but in dma_performance_demo.zip I cannot find any ad hoc simultion testbench. Do I have to use the simulation files of the PIO design? Do they also support dma transfers? Any hint is really appreciated.

    Thanks in advance.

  • RELEVANCY SCORE 3.63

    DB:3.63:Does The Bmd Project Could Simulate? Is There Any Differences Between The Bmd And Dma? sc





    I‘ve found some body discussing thequestion in this post "

    PCI Express DMA Completion streaming problem"

    they say the DMA and the BMD is different . and then i confused, I have thought they are the same transfer way.

    and they say "There is simulation env for DMA design . no simulation for BMD(1052) design." Is this true? if the BMD couldn't be simulated ,how can i test the function ?

  • RELEVANCY SCORE 3.59

    DB:3.59:Ml507 Bmd Reference Design - How To Raise Interrupt? 7k





    Hello all,

    I am using the ML507 development board with a Virtex 5 FX70T FPGA.

    I have modified the BMD reference design to send data as long as mwr_start is set. When ever Package Count (set in the associated register) packages have been written to the PC memory, an interrupt shall be assigned - notifying that the data is ready to be read from the PC host application.

    In simulation with ModelSim, cfg_interrupt_n and cfg_interrupt_assert_n are deasserted when mwr_done is signaled in BMD_EP_TX module until cfg_interrupt_ready_n becomes low. So the cfg interrupt lines seem to act as they have to.

    I am working on a Linux system, using the driver enclosed by the reference design.

    I have tried using MSI by adding pci_enable_msi(gDev) to the init of the driver also as using legacy interrupts by leaving this line of code. Neither of them raised any interrupt to the system when I write 1 to the MWR Start register. I can see this because interrupts should print the configuration registers of the FPGA PCIe device into dmesg (I have left the given irq function from Xillinx in its original state). But there is no interrupt at all. The write data to memory is transfered properly.

    I even tried to set LEGACYCLR to 1 (I found this hind somewhere else in this forum), but without effect.

    Does anybody have any idea what I have to do to get interrupts running?

    I have appended the source of the linux driver, maybe this helps someone to spot the problem.

    Regards,

    Michael










    Attachments:







    xbmd.c ‏29 KB

    DB:3.59:Ml507 Bmd Reference Design - How To Raise Interrupt? 7k

    Can you upload the stable PCIe driver for ML507 board?

  • RELEVANCY SCORE 3.30

    DB:3.30:Simulation Cloth Prob ?? fx



    Hi everyone

    i really have a problem with simulation cuz when i did it for a table cloth and saved the project and opned it again i found the table sheet "cloth"

    unsimulated or like aplane without the simulation processe ..????

    i dont know what i did wrong ??? or what shall i do to save the simulation action ????

    could anyone help me in that ???

    DB:3.30:Simulation Cloth Prob ?? fx


    Hi everyone

    i really have a problem with simulation cuz when i did it for a table cloth and saved the project and opned it again i found the table sheet "cloth"

    unsimulated or like aplane without the simulation processe ..????

    i dont know what i did wrong ??? or what shall i do to save the simulation action ????

    could anyone help me in that ???

  • RELEVANCY SCORE 3.19

    DB:3.19:Simulation pk



    Hi,

    I have a problem with the simulation of charging and discharging of the supercapacitor in the program Hyperlynx Analog, Mentor Graphics. I have the project, which is apparently correct, but when I will give some equivalent circuit of RC supercapacitor, the results of simulation give not the correct characteristics of current and volatage. It is possible that the problem lies in the switchs, because I do not know how to put their parameters. I have a standard library version 7.9.

    following is my project, maybe could someone look at this and help

    Regards

    DB:3.19:Simulation pk


    I do not know how to define the parameters of switchs like

    RON On resistance W 1.0

    ROFF Off resistance W 1.0/GMIN

    VT Threshold voltage (SW only) V 0.0

    VH Hysteresis voltage (SW only) V 0.0

    IT Threshold current (CSW only) A 0.0

    IH Hysteresis current (CSW only) A 0.0

  • RELEVANCY SCORE 3.14

    DB:3.14:Error Occurred During "Simulation Initialization". 8p


    please help to solve this problem, I get this message when i try to run any simulink simulation that uses SYTEM GENERATOR block:

    ISE Simulator Simulation could not be started. It is possible that the system memory available for this process has been exhausted.Error occurred during "Simulation Initialization".

    thanks







    Solved!
    Go to Solution.

    DB:3.14:Error Occurred During "Simulation Initialization". 8p


    problem solved by reseting windows and reinstall everything :smileysad:

  • RELEVANCY SCORE 3.07

    DB:3.07:Urgent Help Need mk



    Adobe Premiere Pro cc not captured Audio but through BMD Card out to external Monitor

    Windows 7 Ultimate and Blackmajic Studio 2 card Adobe Premier Pro cc 7.2 my Video capture (Analog) through card but Audio not captured but also external out video and audio perfectly Through Blackmajic Decklink studeo card with desktop video 9.8 software.pl.assist me. Thanks.

    DB:3.07:Urgent Help Need mk


    Adobe Premiere Pro cc not captured Audio but through BMD Card out to external Monitor

    Windows 7 Ultimate and Blackmajic Studio 2 card Adobe Premier Pro cc 7.2 my Video capture (Analog) through card but Audio not captured but also external out video and audio perfectly Through Blackmajic Decklink studeo card with desktop video 9.8 software.pl.assist me. Thanks.

  • RELEVANCY SCORE 3.07

    DB:3.07:Routing Simulation Problem 17


    Hello,

    I've got to code a simulation of a routing algorithm in a wireless network. Can anyone help?

    Thanx

    DB:3.07:Routing Simulation Problem 17

    Read this thread: http://forum.java.sun.com/thread.jspa?threadID=592557,
    it's all similar to your homework.

    kind regards,

    Jos

  • RELEVANCY SCORE 3.07

    DB:3.07:Premiere Pro Cc14, Blackmagic Intensity Pro dd



    Im in the process of changing from FCP ver7 using a BMD Intensity Pro card (lowest priced BMD device) to Ppr cc14. Would love to hear if anyone is using that card with Premiere Pro CC 14 and either running

    Mavericks or Mountain Lion??

    any issues?

    DB:3.07:Premiere Pro Cc14, Blackmagic Intensity Pro dd


    wouldn't Premiere Pro limit your color bit depth to 8 and your BMD be capable of a larger bit depth?

    that is my thoughts, just limiting your capabilities is my guess

  • RELEVANCY SCORE 3.05

    DB:3.05:Mgii To Sgmii Simulation Problem With "Sgmii_Clk" xm



    Hi

    I have a problem regarding MGII to SGMII simulation. In fact the Xilinx IP core seems to loose clock synchrony.

    I have mentioned my problem details in the following post, but I got no help.

    http://forums.xilinx.com/t5/General-Technical-Disc​ussion/GMII-to-SGMII-Simulation-Problem-sgmii-clk-​...

    Could any one read the post and tell me more about the problem?

    Thanks

    DB:3.05:Mgii To Sgmii Simulation Problem With "Sgmii_Clk" xm


    Thanks yenigal

    This is the example design simulation. I have only fed it with my own data; i.e. it has gmii_txd gmii_tx_en input ports. I fed them with my test data. I considered timing using sgmii_clk when feeding it.

    And ofcourse my design is VHDL based, though it should not make difference for the core or maybe the VHDL version is different in behavior than the Verilog version !!??

  • RELEVANCY SCORE 2.92

    DB:2.92:Post-Route Simulation 98


    We are implementing a microprocessor using VHDL and the target deviceis Spartan-2E XC2s600E. Our problem is on post-route simulation. The behavioral simulation told us that our rtl is working as it should but not whenwe do post-route simulation. The main control for the microprocessor is our problem. Is there a coding guide or coding style to simulate in post route correctly?Our control contains lots of if and ifelse statements. Is there a problem with that?Sorry I can't post our codes here. Please help us. Thanks...

    DB:2.92:Post-Route Simulation 98

    Hi,

    I am working in a I2C controller in VHDL. Mydesign working fine during the functional RTL-Simulation but notduring a post route simulation.

    I simulate my desing using a simple testbench. What can I do?

    Regards, Carlos

  • RELEVANCY SCORE 2.91

    DB:2.91:Control Design And Simulation Palette Doesn't Appear ck



    I'm using LabVIEW 2009 in Professional License. I've installed Control Design and Simulation Module with its all other required Toolkits. The problem is thatControl Design and Simulation palettedoesn't appear in the Functions Palette in any VI. Please help me with that.

    Adeel Amin

    NEDUniversityof Engineering Technology







    Solved!
    Go to Solution.

    DB:2.91:Control Design And Simulation Palette Doesn't Appear ck


    If you run NI License Manager, Expand LabVIEW2009ModulesControl Design and Simulation.Can you verify that you have that directory and what is the color of the cube right next to it?




    Andy ChangNational InstrumentsLabVIEW Control Design and Simulation

  • RELEVANCY SCORE 2.90

    DB:2.90:Hardware Co-Simulation , Non-Memory Mapped Ports j1


    hi,

    there is a question about non-memory mapped ports.

    I do a Hardware co-simulation compilation type with my hardware platform,and creat a A/D non-memory mapped ports. But when I generate code,and hardware simulation, I can't get the correct data from external signal.

    So is there anyone help me with this problem? thanks.

    DB:2.90:Hardware Co-Simulation , Non-Memory Mapped Ports j1


    Hi

    I am expecting you are using Jtag based custom boardHardware Co Simulation,

    "Not getting correct data " means ?

    Are you comparing simulink simulation against HW CO SIM results , if so wthat is clocking type ?

    It depends onsingle stepped or free running.

    Free running results may not match as Hardware runs asynchronoulsy with software simulation.

    Snapshots may be useful for better understanding.




    ---------------------------------------------------------------------------------------------Please do google search before posting, you may find relavant information.Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

  • RELEVANCY SCORE 2.88

    DB:2.88:Error 77080 - Labview Softmotion 8m



    hi all,

    I am working with labview softmotion and solidworks.

    I am posting this question since a new problem happened to me. Everything was working well, and suddenly it became impossible to start the solidworks simulation through the labview project explorer. When I click "start simulation", as i was doing before, the error 77080 pops up, saying "an error occurred while starting the solidworks simulation" and "an error occurred while reading deployed data".

    It would be really nice if someone can provide me some help about this problem.

    Thank you in advance.

    DB:2.88:Error 77080 - Labview Softmotion 8m


    Hi,

    It took me a while to figure out how to tackle this problem, therefore, I'd like to share the solution with the community:

    Save any design with your Solidworks version: The files shipped with SoftMotion are created with an old version of Solidworks (prior to Solidworks 2013 for sure). So first step is to save any model using your current version.

    Make sure you close your LabVIEW project and Solidworks after enabling Motion addins in Solidworks: This is the major and common problem for that error. Reopeneing both thereafter would solve the problem.
    Open your Solidworks model from LabVIEW project, then make sure you "Synchronized it".

    Deploy your solidworks model and axis.

    Then starting simulation would run normally

    Hope it helps.

    .




    Waleed El-Badry MSc.,MCPD, ISTQB Certified TesterAssistant Lecturer Mechatronics DepartmentFaculty of EngineeringMisr University for Science Technology

  • RELEVANCY SCORE 2.84

    DB:2.84:Bmd On Ml605 With X8 Gen2 37



    Hi,

    I'm experimenting with the BMD design (xapp1052) and try to reproduce the mentioned throughput for the x8 Gen2 on the ML605. So I got a design compiled and I can also talk to the BMD and transmit/recive data.

    I'm using "Virtex-6 Integrated Block for PCI Express v1.7" andI noticed that gen2 is not supported for speed grade -1 which is used on the ML605. Does that mean it was supported in an earlier version or it's not recommended, because it was used right?

    I'm unsure about the real data throughput. So I tried to verify theLink Status and theLink Capabilities Register (0x60) is0x82 which is x8 Gen2 if I'm right. But theCurrent Link Status (0x70) is 0x00 which I don't understand. What does that mean?

    Also Documentation says that TLP size of 128byte is maximum for speed grade -1 and that is advertised even if I compile with256byte. Strange is that the programmed payload size is set to256byte. Both is working as far as I can tell. Does that make sense ?

    I would be very thankful if someone could help me understand?

    Kind regards

    Erik

    P.S.: Virtex6 on my board is Version 6 which should be production, I'm using ISE 13.3.

    DB:2.84:Bmd On Ml605 With X8 Gen2 37

    Helloluisb,

    Thank you for answering.

    You said I'm incorrect about MPS. Could you please give me a hint where I'm mistaken and point me in the right direction?

    Thank you very much in advance!

    Kind regards

    Erik

  • RELEVANCY SCORE 2.84

    DB:2.84:Dropped Frames W/ Ae Dynamic Link Comps Using Bmd (On Playback) pa



    Hey guys,

    This problem started exibiting itself a couple weeks ago. Hoping for some feedback regarding possible problems other than just bad performance with my BMD Hardware.

    The following is the system it's occuring on:

    2009 2.93Ghz/16GB 8-Core MacPro

    Adobe CS5 - Latest Updates

    Internal Raid 0 - Footage Files

    Internal 7200RPM - Project Files

    Internal 7200RPM - OS

    (all drives at 50% or more current capacity)

    Stock GT120GFX

    GTX285

    Blackmagic Decklink Extreme 3D to HDLinkPro

    2 Monitors (1 to each GFX card)

    1 Plasma monitor out of the Decklink

    Now that's out of the way, here's the scenario:

    Using Blackmagic Design sequence presets in Premiere and Dyanamic Linking AE comps in the Premiere sequence . Playing back the sequence results in CS5 stopping playback because "Dropped Frames Detected"

    This ONLY occurs in the following situations:

    - with any BMD preset

    - only unrendered (yellow) timeline comps

    Rendering the timeline (sot it's green) results in uninterrupted playback

    The comps have no problems in AE

    Premiere exhibits no playback issues outside of BMD presets

    Premiere exhibits no playback issues with other footage

    All fingers point to something internal when in a BMD preset. But could a drive be failing? Something else?

    Thanks.

    DB:2.84:Dropped Frames W/ Ae Dynamic Link Comps Using Bmd (On Playback) pa


    Yes, of course After Effects will have to do an inital rendering of the frames, but I had assumed that Jay knew this and was concerned with playing/scrubbing through a part of a track for which the After Effects frames had already been rendered and cached.

    My next line of questioning was going to relate to how much memory After Effects was being allowed, because a small amount would mean that it was needing to drop rendered frames out of its cache.

    Todd, I believe the playback resolution setting is ignored on a BMD timeline.

    Ah, I didn't realize that wrinkle. Thanks for the clarification.

  • RELEVANCY SCORE 2.79

    DB:2.79:Problem While Giving Input Values In Simulation Window!! Please Help.. px



    I have written a VHDL program for which I have to give 64bit inputs. The program doesnt have any errors. It also synthesized without errors on spartan6.

    But during simulation it is not accepting inputs.

    When I force input like this 'isim force add 3'

    It will dispaly a message like 'the value 3 given is higher than the indentifier size in the context'

    I have a similar problem with another program also. Please help me as soon as possible.







    Solved!
    Go to Solution.

    DB:2.79:Problem While Giving Input Values In Simulation Window!! Please Help.. px


    Hi,

    yes the language can be described with CSPs.

    CSPs are a method to manage paralleism and VHDL actually supports that.

    FSMs (which can be reduced to a FF in their most simple form) can be seen as a hardware representation of CSPs.

    Still if you are going to synthesize some textual description into hardware you are doing something different than what happens in concurrent programming.

    A (software) program is often developed on the assumption that (in the ideal case) an unlimited ammount of storage space is available. In the early er days of computing the "Out of Memory " error was quite common. Now with GBs of RAM even in a handheld device this became rare.

    If a software engineer is imposed with handling limited memory ressources he's not very pleased becaus now he had to create extra code that deals with things that the computer should care about.

    A hardware description doesn't assume the exsitence of (storage) memory at all. While a FF can be used to store data, this is just a sid effect of interpreting the FFs state as processable information.

    A hardware designer has to deal with all aspects of the hardware architecture directly and is always aware of the limited ressources that can not dynamically grow or change. (Even while dynamic reconfiguration exists, it's a tough business at this time).

    So if a programmer and a HW-designer are given the same task of implementing some algorithm, the approaches and results will be very different.

    What you are doing is subsuming all "text input methods" as programming.

    But then a secretary is a programmer too, because the texts he or she writes into some appointment schedule causes one or more people to act according to that schedule. Is that what's meant by wetware programming? Does this qualify for a payment raise now? ;-)

    Sometimes it's good to distinguish between things that might look similar at first glance.

    Regards

    Eilert

  • RELEVANCY SCORE 2.78

    DB:2.78:Error In Payroll Simulation Rgdir Already Contains An Entry With The Same L c1



    hi all

    please help am having a problem when running a payroll simulation which says rgdir already contains an entry with the same logical key even when i run the correcting report i still encounter the same program

    thnx

    DB:2.78:Error In Payroll Simulation Rgdir Already Contains An Entry With The Same L c1


    Did you try to run SAP program to rebuild payroll directory RPUDIR00, as sometime this gets corrupted ?

  • RELEVANCY SCORE 2.78

    DB:2.78:Coregen Fifo V9.3 Post-Route Simulation Problem In Ise 14.5 3m



    I have created a very basic test design (attached), which instantiates a FIFO and nothing else. The testbench has two processes:the write process writes two sequences of 16 bytes each and the read process tries to read when the empty flag goes zero. This works fine with behavioral model, but fails in post-route. Please see the plots below. The FIFO is asyncronous with different write and read widths. Any help will be highly appreciated. Thanks.







    Solved!
    Go to Solution.

    DB:2.78:Coregen Fifo V9.3 Post-Route Simulation Problem In Ise 14.5 3m


    Please disregard. I have found the problem - setup violations on the control signals generated by the testbench.

  • RELEVANCY SCORE 2.77

    DB:2.77:External Monitoring: Bmd Ultrastudio Sdi - No Audio On Line Out mp



    Hello,

    I wanted to do external monitoring of my Premiere Pro Cs 5.5 sequence on a windows machince. I set up the Blackmagic Design Ultrastudio SDI with the appropriate sequence settings from BMD and got a video output on my SDI monitor. But I want to monitor the audio through the line out and configured Premiere to not pass the audio to the Blackmagic Device. But I cant hear anything on my speakers.

    I would like to have as less adapters as possible involved and thats why I dont like to get the audio from the Ultrastudio.

    Did I miss any important settings for seperate audio output?

    Thanks in advance for your help!

    Horst Kilomi

    DB:2.77:External Monitoring: Bmd Ultrastudio Sdi - No Audio On Line Out mp


    I have a dim memory of reading that this simply may not be possible, you have to pass audio through the BM.

  • RELEVANCY SCORE 2.77

    DB:2.77:Few Doubts On Bmd Parameters a1



    Hi All,

    I am using BMD for pcie integration.. Following are the parameters used

    Max Payload size in core GUI 256 bytes

    max payload size in BMD is 128 bytes.. for 256 bytes it is not writing into Rx.dat file

    32 bit addressing

    3DW header (1st dw payloadis not required) in last DWadding d0dad0da.. I have to avoid that

    Can anyone help for above two point.. I need 256 bytes payload writing to file

    For 128 bit design is working fine..

    DB:2.77:Few Doubts On Bmd Parameters a1


    Hi All,

    I am using BMD for pcie integration.. Following are the parameters used

    Max Payload size in core GUI 256 bytes

    max payload size in BMD is 128 bytes.. for 256 bytes it is not writing into Rx.dat file

    32 bit addressing

    3DW header (1st dw payloadis not required) in last DWadding d0dad0da.. I have to avoid that

    Can anyone help for above two point.. I need 256 bytes payload writing to file

    For 128 bit design is working fine..

  • RELEVANCY SCORE 2.77

    DB:2.77:Fifo Simulation Problem c9



    Hi,

    I am simulating a FIFO in my design with structural model. However, in the simulation, the dout remains XXX even if the empty flag indicates that the data is written into the FIFP. Here is the timing table in the simulation. I think I must made some very stupid mistake since this is the first time I use FIFO. Please help me!

    Thanks!

    Chennan










    Attachments:




    DB:2.77:Fifo Simulation Problem c9

    You need to check the warning generated by tool. It seems all the output data are XXX. this only meant core is not instant properly or your project corrupted any how



    Thanks and RegardsBalkrishan--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 2.77

    DB:2.77:Problem With Simulation 7f


    Please take a look at the readings on the multimeters 2, 3 and 4; for some reason they all show -60V; Notice that we only have 30 V (-15v +15 V) connected to the pots. If we disconnect the LM324 inputs from the pots, the voltmeters read OK. This is frustrating. Need some help.
    thanks and regards,
    Narendra Utukuri
    DeVry, Houston, TX









    Attachments:







    Circuit1.ms8 ‏58 KB

    DB:2.77:Problem With Simulation 7f

    Try hooking up U1A, U2B, and U3C to power. These are unconnected. When you placed these apparently you didn't place them as one continuous IC otherwise they would have been labeled U1A, U1B, U1C, U1D. Unless this is what you wanted to do.

    You can either hook them up to power or try to re-place them to get them all in one IC. I am not sure about whether Version 8 supports virtual wiring to IC's the way Version 10 does, but with Version 10 if you have all these in one IC then you only have to hook up one of them to apply power to all of them.

    This seemed to take care of the voltage problem.




    Kittmaster's Component Database http://ni.kittmaster.comHave a Nice Day

  • RELEVANCY SCORE 2.76

    DB:2.76:Problem With Simulation Of Bmd(Xapp1052) 3a



    Hi !

    I have a sp605 Spartan 6 board , and now i am trying to understand how BMD (xapp1052) works . i did it step by step like this ( i use modelSim 6.4b)

    1. I generated the Spartan6 integrated block for pci express v1.2 (verilog)

    2. after that i put folder from xapp1052.zip in my PCIe folder ( just like an example in xapp1052 )

    3. for Simulation i used all source files in folder dsport ( rootport) and for unit under test i used all bmd files instead of Pio files

    4. i have changed TSK_BAR_PROGRAM in rootport in order to set bus master enable for endpoint

    5. in the beginning of the test i use every tasks like in pio_writeReadBack_test0

    6. then i start to write the length , amount , address and finally start the Memory read Request test.Result

    1. after starting the memory Read request ( mrd_start was set ) , BMD sent out all the mermory read request that i expected ( i monitored all of signal in wave of model sim)

    2. actually i expect that memory Read in my Rootport with memory read expect -task and then i write completion(with data) back and the wait for interrupt from endpoint here are the problems!! : instead of completion with data ,i recieved

    completions without data like this 00a000000, 00002008 , last DW . in the second DW i can see clearly that

    completion status was 010 that refers to unsupported Request .

    can anybody please tell me what happened and what should i do ?

    - do i need to change some configuration in rootport or endpoint?

    - i guess that in my case , the memory read address that i wrote to the register of BMD in the beginning was wrong but how we know which address of rootport should i write ( with endpoint we can assign and address with task in rootport but for address of rootport itself i really have no idea ??)

    thank you very much in advance :manhappy:







    Solved!
    Go to Solution.

    DB:2.76:Problem With Simulation Of Bmd(Xapp1052) 3a


    I follow your steps and solve my problem. Thank u very much.

  • RELEVANCY SCORE 2.76

    DB:2.76:Does Anyone Know About A Program Call Bmd - Premise m1



    I am having issue with BMD and it show floor plans. The company insist it is not the Premise software but more or less the NI LABView that is requiring admin rights to run it... Has anyone heard of this?

    Help

    DB:2.76:Does Anyone Know About A Program Call Bmd - Premise m1


    Please stick to your original post.

    You are asking about something which is unlikely to have been used by anyone here. Please have some patience. If you need immediate assistance, then you should pick up the phone and call NI tech support.

  • RELEVANCY SCORE 2.76

    DB:2.76:Timing Simulation With Modelsim Launch From Planahead 14.6 f9



    Hello,

    For my design I use a SPARTAN 6 XC6SLX75.

    I work with Planahead 14.6 and modelsim 10.2b, and I have a problem with the timing simulation with modelsim launch from Planahead. (nota: the behavioral simulation runs correctly)

    The error message is :

    launch_modelsim -install_path C:/modeltech64_10.2b/win64 -simset sim_1 -mode timingERROR: [Common 17-69] Command failed: Invalid simulation type '' specified. Please see 'launch_modelsim -help' for more details.

    I read the help but I didn't see which kind of information could resolve my problem.

    Currently, the only solution is to work with Modelsim in standalone mode after to have generate the VHDL(or Verilog) and SDF netlist. It's a pity!...

    Someone or a XILINX expert does have a solution to launch "run timing simulation" for modelsim from planahead ?

    Best Regards

    DB:2.76:Timing Simulation With Modelsim Launch From Planahead 14.6 f9


    Hi,

    The correct command is

    launch_modelsim -install_path C:/modeltech64_10.2b/win64 -simset sim_1 -mode post-implementation -type timing

    or

    launch_modelsim -install_path C:/modeltech64_10.2b/win64 -simset sim_1 -mode post-synthesis -type timing

    based on whether you want to run post synthesis or post implementation simulation.

    The -mode switch is used to specify the simulation mode and it has three values

    behavioral

    post-synthesis

    post-implementation

    Thanks,

    Deepika.




    --------------------------------------------------------------------------------------------Google your question before posting.If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

  • RELEVANCY SCORE 2.75

    DB:2.75:Simulation With Codewarrior 1x


    DB:2.75:Simulation With Codewarrior 1x

    hello,I would like simulate a square input signal on a input capture timer , with a processor expert component, and an output on a simulated oscilloscope . All this just in simulation mode, without physical target , but i dont know how to do that, can someone help me, or give me a link on a good tutorial ? Microcontroller can be a 68hc08, qy, QT ...Thanks in advance, Firby

  • RELEVANCY SCORE 2.74

    DB:2.74:Functional Simulation Of Coregen Ip jx


    Hello,

    I've created an AXI stream interconnect crossbar switch using Coregen. Now, for functional simulation for the maximum throughput of the design, I want to simulate it with my testbench, and hence I instantiated it with the "_sim.vhd". ISE is complaining about "compiling the library and using the use clause" at the coregen syntax check level. I have made sure to compile the library and also having the use clause. The problem persists.

    Can you help resolving this issue?

    Thanks

    S







    Solved!
    Go to Solution.

    DB:2.74:Functional Simulation Of Coregen Ip jx

    Hello S,If the last reply was helpful and has helped for your query then do mark it as an Accepted Solution. In case you have solved this issue yourself, kindly post the same for other users.



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.74

    DB:2.74:Problem With Simulation Ise 12.2 With Modelsim 6.6b p3



    ISE version 12.2, for Spartan 3

    1. Simulation of BUFGMUX make unprope direction on Post-Route simulation (I0 instead of I1). But behavioral simulation make prope result.

    2. Simulation of distribution RAM make unprope direction too.

    ISE version 10.1 make good results.

    DB:2.74:Problem With Simulation Ise 12.2 With Modelsim 6.6b p3

    Can you try implementing your netlist ngc generated from 10.1 in 12.1 and see if you see any difference?

    Could you also please open a webcase with our Technical Support at http://www.xilinx.com/support/clearexpress/websupp​ort.htm?

    -PK




    Thanks,-PK

  • RELEVANCY SCORE 2.73

    DB:2.73:Sending Scale Of Image In Byte Array ax



    Hello Friends

    Please guide me how can i send yte array of my bitmapped UIcopmonent with scale size 0.4.

    Actually my size of my UIComponet is 234X390 and i hv to send the byte array to PHP end with size 90X150.

    this is almost 0.4 scale of image so how can i draw an image with smaller size.please guide me.

    when i usedthis code

    var bmd:BitmapData = new BitmapData(cnvParent.width,cnvParent.height,true,0xffffff); var mt:Matrix=new Matrix(); mt.scale(.4,.4); bmd.draw(cnvParent,mt); var jpgencoder:PNGEncoder = new PNGEncoder(); byteArray = jpgencoder.encode(bmd);

    it shows nothing after conversion to byte array.Please help me out from this problem i mtotally confused

    Thanks and Regards

    Vineet osho

    DB:2.73:Sending Scale Of Image In Byte Array ax


    hi,

    the following is a full application that captures the canvas(when you click) then saves it to a file, so you can see the result.

    for this to work correctly(file save) you need to make sure your project compiler settings target flashplayer 10.0.0

    David

    ?xml version="1.0" encoding="utf-8"?

    mx:Application xmlns:mx="http://www.adobe.com/2006/mxml" layout="vertical"

    mx:Script

    ![CDATA[

    import mx.graphics.codec.PNGEncoder;

    protected function canvas1_mouseDownHandler(event:MouseEvent):void

    {

    var pngenc:PNGEncoder = new PNGEncoder();

    var bmd:BitmapData = new BitmapData(cnvs.width,cnvs.height,true,0xffffff);

    var mt:Matrix=new Matrix();

    mt.scale(.4,.4);

    bmd.draw(cnvs,mt);

    var ba:ByteArray = new ByteArray()

    ba = pngenc.encode(bmd);

    var fi:FileReference = new FileReference();

    fi.save(ba,"test.png");

    }

    ]]

    /mx:Script

    mx:Canvas width="200" height="200" id="cnvs" mouseDown="canvas1_mouseDownHandler(event)"

    mx:Button x="10" y="10" label="Button"/

    mx:CheckBox x="44" y="66" label="CheckBox"/

    mx:CheckBox x="44" y="125" label="CheckBox"/

    /mx:Canvas

    /mx:Application

  • RELEVANCY SCORE 2.73

    DB:2.73:Incorrect Simulation Results On Pcie Bmd Xapp1052 App Notes pj



    xapp1052 simulation: EP's trn_tx (MRd packets) data cannot reach RP's trn_rd portHi,I am using the verilog code in the xapp1052 as a reference. However, when I checked the system behavior on simulation in ModelSim, I found something strange with the code running in DMA memory read mode. After setup all the registers and initiated the DMA start, i found that the data (several MRd packets) send through the EP's trn_td port cannot reach the RP's trn_rd port. It just disappeared.Please see the attached file.The RP and EP’s cfg_dstatus= 0x00.The EP’s cfg_command =0x07.But the code can work in my PC on Win XP, under the test program. Thus I guess that there should be some more things to set up.Is there anything more to be set up before the DMA start?--------------------------------------------This is from the Steps to Reproduce Problem--------------------------------------------Run the ModelSim with the xapp1052 code provided. ISE v13.2










    Attachments:




    DB:2.73:Incorrect Simulation Results On Pcie Bmd Xapp1052 App Notes pj

    It can run on my ML605 board on GigaByte or ASUS motherboard. Virtex 6.

  • RELEVANCY SCORE 2.72

    DB:2.72:Problem With Simulation 8x



    i am trying to make a Variable DC voltage supply ranging from 0V to 32V with a fixed 1A of current. i have a schematic googled from a thread but it will give to 30V. unfortunately i can't simulate it with Multisim. Please help design and schematic is attached. i have tried my best but again and again convergence simulation error appears. i didn't know what happen to the circuit? please help ASAP! please made any changing to make it a DC variable voltage supply 0-32v,1A




    m.azeemakhlaq

    DB:2.72:Problem With Simulation 8x


    i will let you know my complete requirement. i'm not getting my desired schematic from google. here i mentioned what i want:

    - A Variable DC Voltage Supply whose output voltages ranges from 0v to 32v and at all voltages the output current must be constant at 1A.

    -Use Potentiometer to change Voltages at constant current 1A.

    - Input source must be a 220v AC source (Vrms) which is to be step down by a transformer and rectified by a Bridge Rectifier..

    -Supply Protection Circuit i.e. a Fuse must be present in the circuit

    -Output Voltages Must be on 7-segment LED display and Constant output current i.e. 1A must also be shown on 7 segment LED display.

    The above desired circuit must be made of simple component which are easily available in the market. Use what ever the model of the components.

    please help as soon as possible i am trying my best for this but continously getting failure..




    m.azeemakhlaq

  • RELEVANCY SCORE 2.72

    DB:2.72:Simulation Issues. k9



    Hello all !

    I am trying to build a project based on MC13213.

    While working with CodeWarrior v10.4, there is a problem in simulation.

    It gives an error saying that

    "Profiling is disabled in Full Chip Simulation Mode" and so I am not able to simulate my project.

    Kindly Help !

    Thanks in advance !

    - Pinakin

    DB:2.72:Simulation Issues. k9


    Hello all !

    I am trying to build a project based on MC13213.

    While working with CodeWarrior v10.4, there is a problem in simulation.

    It gives an error saying that

    "Profiling is disabled in Full Chip Simulation Mode" and so I am not able to simulate my project.

    Kindly Help !

    Thanks in advance !

    - Pinakin

  • RELEVANCY SCORE 2.70

    DB:2.70:Reagarding Simulation Error a7


    hi all...when i'm simulating the circuit...i'm getting o errors and 0 warnings...but i'm getting simulation error...errors are: ------ Checking SPICE netlist for 555timercktthreephasefullwavenew - 2009-10-15 17:16:06 ------ ======= SPICE Netlist check completed, 0 error(s), 0 warning(s) ======= Error Message From Simulation: doAnalyses: Timestep too smallError Message From Simulation: tran simulation(s) abortedi'm changing time step in simulate--interactive simulation settings--maximum time stepi'm changing that max time step....but i'm getting the same error...timestep is small...how to overcome this problem.......please help me

    DB:2.70:Reagarding Simulation Error a7

    hi...i tried the settings link which u have given...but even then my problem is not solved.............can i get any material related to this error....i want to read that....if u can send link then i can download and read...thank u

  • RELEVANCY SCORE 2.69

    DB:2.69:Problem With Bmd Design For Xilinx Endpoint Block Plus Core For Pci Express ds


    I am writing to you for some help on implementing BMD design for xilinx pci express core. I followed the instructions in XAPP1052 demo. When i write data from endpoint to memory, it is normal and cpu can receive an interrupt. But when i read data from memory to endpoit, i found the TLP on RX channel always has a payload of 10h. I have tried many times and changed the payload parameter, but it is still 10h. of course, there is no interrupt when reading.

    DB:2.69:Problem With Bmd Design For Xilinx Endpoint Block Plus Core For Pci Express ds

    I am writing to you for some help on implementing BMD design for xilinx pci express core. I followed the instructions in XAPP1052 demo. When i write data from endpoint to memory, it is normal and cpu can receive an interrupt. But when i read data from memory to endpoit, i found the TLP on RX channel always has a payload of 10h. I have tried many times and changed the payload parameter, but it is still 10h. of course, there is no interrupt when reading.

  • RELEVANCY SCORE 2.69

    DB:2.69:Timing Simulation pa



    hi all im asking for why timitng simulation is not giving same result as functional simulation

    my desing is working with double data rate on vhdl. the functional simulation is fine but the timing isnt giving the result that it should be.

    ive tried many solution as ODDR for spartan 6, making timing constraints, changing code style... but always the problem of wrong result persist

    any help ??

    DB:2.69:Timing Simulation pa


    well idont know exactly how to show my problem but one thing that makes trouble is how to find out the good timing constraints cause its realy makes headaches and still not understanding this constraints

    im working on spartan 6, vhdl, and what i need is puncturing system working on double data rate

    on singla data rate idont have problem but in double data rate it makes troubles

    if you want vhdl code or any other just specify it and iwill post it

    thanks in advance

  • RELEVANCY SCORE 2.69

    DB:2.69:[Help]Problem With Bmd Simulation k9



    I meet a problem when I simulate the DMA free_ware.

    Here is the excerpt of the Modelsim log showing the errors at elaboration time :

    do simulate_mti.do

    # ** Warning: (vlib-34) Library already exists at "work".# Reading D:\modeltech_6.4d\win32/../modelsim.ini# "work" maps to directory work. (Default mapping)# Model Technology ModelSim SE vlog 6.4d Compiler 2009.03 Mar 16 2009# -- Compiling module boardx04# -- Compiling module sys_clk_gen# -- Compiling module sys_clk_gen_ds# -- Compiling module BMD# -- Compiling module BMD_64_RX_ENGINE# -- Compiling module BMD_64_TX_ENGINE# -- Compiling module BMD_EP_MEM_ACCESS# -- Compiling module BMD_EP_MEM# -- Compiling module BMD_EP# -- Compiling module BMD_INTR_CTRL# -- Compiling module BMD_TO_CTRL# -- Compiling module xilinx_pci_exp_4_lane_ep# -- Compiling module endpoint_blk_plus_v1_5# -- Compiling module glbl# -- Compiling module pci_exp_64b_app# -- Compiling module xilinx_pci_exp_4_lane_downstream_port# -- Compiling module xilinx_pci_exp_4_lane_dsport# -- Compiling module dsport_cfg# -- Compiling module pci_exp_usrapp_rx# -- Compiling module pci_exp_usrapp_tx# -- Compiling module pci_exp_usrapp_com# -- Compiling module pci_exp_usrapp_cfg# -- Compiling module pci_exp_4_lane_64b_dsport# -- Scanning library directory 'D:\Xilinx\10.1\ISE/verilog/src/simprims'# -- Scanning library directory 'D:\Xilinx\10.1\ISE/verilog/src/unisims'# -- Compiling module IBUFDS# -- Compiling module IBUF# -- Compiling module VCC# -- Compiling module GND# -- Compiling module INV# -- Compiling module LUT5# -- Compiling module LUT3# -- Compiling module LUT4# -- Compiling module FDR# -- Compiling module LUT2# -- Compiling module LUT6# -- Compiling module FDC# -- Compiling module FDCE# -- Compiling module FDP# -- Compiling module BUFG# -- Compiling module PLL_ADV# -- Compiling module PCIE_INTERNAL_1_1# -- Compiling module RAMB36_EXP# -- Compiling module RAMB36SDP_EXP# -- Compiling module FDRE# -- Compiling module GTP_DUAL# -- Compiling module LDP_1# -- Compiling module FD# -- Compiling module FDE# -- Compiling module SRLC16E# -- Compiling module MUXF7# -- Compiling module FDRS# -- Compiling module LUT1# -- Compiling module FDRSE# -- Compiling module FDS# -- Compiling module FDSE# -- Compiling module MUXCY# -- Compiling module XORCY# -- Compiling module RAM32X1D# -- Compiling module GT11CLK_MGT# -- Compiling module OBUF# -- Compiling module LUT4_L# -- Compiling module LUT1_L# -- Compiling module LUT2_L# -- Compiling module LUT3_L# -- Compiling module MUXF5# -- Compiling module FDPE# -- Compiling module BUF# -- Compiling module DCM_ADV# -- Compiling module dcm_adv_clock_divide_by_2# -- Compiling module dcm_adv_maximum_period_check# -- Compiling module dcm_adv_clock_lost# -- Compiling module BUFGMUX_VIRTEX4# -- Compiling module MUXCY_L# -- Compiling module SRLC16# -- Compiling module SRL16# -- Compiling module GT11# -- Compiling module RAM16X1D# -- Compiling module SRL16E# -- Compiling module RAMB16_S18_S18# -- Compiling module MULT_AND# -- Compiling module MUXF6# -- Compiling module ARAMB36_INTERNAL# -- Compiling module BUFGCTRL# -- Scanning library directory 'D:\Xilinx\10.1\ISE/smartmodel/nt/wrappers/mtiverilog'# -- Compiling module PCIE_INTERNAL_1_1_SWIFT# -- Compiling module GTP_DUAL_FAST# -- Compiling module GTP_DUAL_SWIFT# -- Compiling module GT11_SWIFT# -- Compiling module PCIE_INTERNAL_1_1_SWIFT_BIT# -- Compiling module GTP_DUAL_FAST_BIT# -- Compiling module GTP_DUAL_SWIFT_BIT# -- Compiling module GT11_SWIFT_BIT# # Top level modules:# boardx04# glbl# vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L work work.boardx04 glbl # ** Note: (vsim-3813) Design is being optimized due to module recompilation...# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.# Loading D:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll# Loading work.boardx04(fast)# Loading work.xilinx_pci_exp_4_lane_ep(fast)# Loading work.IBUFDS(fast)# Loading work.IBUF(fast)# Loading work.pci_exp_64b_app(fast)# Loading work.BMD(fast)# Loading work.BMD_EP(fast)# Loading work.BMD_EP_MEM_ACCESS(fast)# Loading work.BMD_EP_MEM(fast)# Loading work.BMD_64_RX_ENGINE(fast)# Loading work.BMD_64_TX_ENGINE(fast)# Loading work.BMD_INTR_CTRL(fast)# Loading work.BMD_TO_CTRL(fast)# Loading work.endpoint_blk_plus_v1_5(fast)# Loading work.VCC(fast)# Loading work.GND(fast)# Loading work.INV(fast)# Loading work.LUT5(fast)# Loading work.LUT3(fast)# Loading work.LUT4(fast)# Loading work.FDR(fast)# Loading work.LUT2(fast)# Loading work.LUT6(fast)# Loading work.LUT2(fast__1)# Loading work.LUT2(fast__2)# Loading work.LUT2(fast__3)# Loading work.LUT2(fast__4)# Loading work.FDC(fast)# Loading work.FDCE(fast)# Loading work.FDP(fast)# Loading work.BUFG(fast)# Loading work.PLL_ADV(fast)# Loading work.PCIE_INTERNAL_1_1(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT_BIT(fast)# Loading work.RAMB36_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast)# Loading work.RAMB36SDP_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast__1)# Loading work.FDRE(fast)# Loading work.GTP_DUAL(fast)# Loading work.GTP_DUAL_FAST(fast)# Loading work.GTP_DUAL_FAST_BIT(fast)# Loading work.GTP_DUAL(fast__1)# Loading work.LDP_1(fast)# Loading work.FD(fast)# Loading work.FD(fast__1)# Loading work.FDE(fast)# Loading work.SRLC16E(fast)# Loading work.MUXF7(fast)# Loading work.RAMB36SDP_EXP(fast__1)# Loading work.ARAMB36_INTERNAL(fast__2)# Loading work.LUT2(fast__5)# Loading work.LUT2(fast__6)# Loading work.FDRS(fast)# Loading work.LUT1(fast)# Loading work.FDRSE(fast)# Loading work.FDS(fast)# Loading work.LUT2(fast__7)# Loading work.FDSE(fast)# Loading work.FDRSE(fast__1)# Loading work.FDE(fast__1)# Loading work.MUXCY(fast)# Loading work.XORCY(fast)# Loading work.FDSE(fast__1)# Loading work.RAM32X1D(fast)# Loading work.xilinx_pci_exp_4_lane_downstream_port(fast)# Loading work.xilinx_pci_exp_4_lane_dsport(fast)# Loading work.GT11CLK_MGT(fast)# Loading work.OBUF(fast)# Loading work.pci_exp_4_lane_64b_dsport(fast)# Loading work.LUT1(fast__1)# Loading work.LUT2(fast__8)# Loading work.LUT4_L(fast)# Loading work.LUT1_L(fast)# Loading work.LUT2_L(fast)# Loading work.LUT2_L(fast__1)# Loading work.LUT2_L(fast__2)# Loading work.LUT3_L(fast)# Loading work.LUT2(fast__9)# Loading work.MUXF5(fast)# Loading work.LUT2_L(fast__3)# Loading work.LUT2_L(fast__4)# Loading work.LUT2_L(fast__5)# Loading work.FDPE(fast)# Loading work.BUF(fast)# Loading work.DCM_ADV(fast)# Loading work.dcm_adv_clock_divide_by_2(fast)# Loading work.dcm_adv_maximum_period_check(fast)# Loading work.dcm_adv_maximum_period_check(fast__1)# Loading work.dcm_adv_clock_lost(fast)# Loading work.BUFGMUX_VIRTEX4(fast)# Loading work.BUFGCTRL(fast)# Loading work.MUXCY_L(fast)# Loading work.LUT2_L(fast__6)# Loading work.SRLC16(fast)# Loading work.SRL16(fast)# Loading work.LUT1_L(fast__1)# Loading work.GT11(fast)# Loading work.GT11_SWIFT(fast)# Loading work.GT11_SWIFT_BIT(fast)# Loading work.GT11(fast__1)# Loading work.GT11(fast__2)# Loading work.LUT2_L(fast__7)# Loading work.RAM16X1D(fast)# Loading work.LUT2_L(fast__8)# Loading work.LUT2_L(fast__9)# Loading work.SRL16E(fast)# Loading work.RAMB16_S18_S18(fast)# Loading work.MULT_AND(fast)# Loading work.MUXF6(fast)# Loading work.dsport_cfg(fast)# Loading work.pci_exp_usrapp_rx(fast)# Loading work.pci_exp_usrapp_tx(fast)# Loading work.pci_exp_usrapp_cfg(fast)# Loading work.pci_exp_usrapp_com(fast)# Loading work.sys_clk_gen_ds(fast)# Loading work.sys_clk_gen(fast)# Loading work.sys_clk_gen_ds(fast__1)# Loading work.sys_clk_gen(fast__1)# Loading work.glbl(fast)# ** Warning: (vsim-PLI-3003) ../board.v(123): [TOFD] - System task or function '$fsdbDumpfile' is not defined.# Region: /boardx04# ** Warning: (vsim-PLI-3003) ../board.v(124): [TOFD] - System task or function '$fsdbDumpvars' is not defined.# Region: /boardx04# ** Warning: (vsim-3015) D:/Xilinx/10.1/ISE/verilog/src/unisims/GTP_DUAL.v(3488): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i /genblk1/gtp_dual_fast_1# ** Warning: (vsim-3015) D:/Xilinx/10.1/ISE/verilog/src/unisims/GTP_DUAL.v(3488): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i /genblk1/gtp_dual_fast_1# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport# Runtime, LMTV v12.4# Copyright (c) 1984-2009 Synopsys Inc. ALL RIGHTS RESERVED# You can use the Browser tool to configure the SmartModel# Library and access information about SmartModels:# $LMC_HOME/bin/sl_browser# # SmartModel product documentation is available here:# $LMC_HOME/doc/smartmodel/manuals/intro.pdf# http://www.synopsys.com/products/lm/doc/smartmodel.html# # (LMTV) (3006)Error: Model named 'PCIE_INTERNAL_1_1_SWIFT' was not installed at $LMC_HOME/models/PCIE_INTERNAL_1_1_SWIFT for this platform - # $lm_model failed to find model. Verify that instance path is correct.# (LMTV) (3006)Error: Model named 'GTP_DUAL_FAST' was not installed at $LMC_HOME/models/GTP_DUAL_FAST for this platform - # $lm_model failed to find model. Verify that instance path is correct.# (LMTV) (3006)Error: Model named 'GTP_DUAL_FAST' was not installed at $LMC_HOME/models/GTP_DUAL_FAST for this platform - # $lm_model failed to find model. Verify that instance path is correct.# Model gt11_swift: Model Vendor: xilinx'.# Running test {sample_smoke_test0}......# [ 0] : System Reset Asserted...# [ 4995000] : System Reset De-asserted...# [ 8522100] : Transaction Reset Is De-asserted...# Break key hit

    I have changed the file modelsim.ini and comipled the library with the following command:

    compxlib -s mti_se -arch all -lib all -l verilog -w

    but'PCIE_INTERNAL_1_1_SWIFT' and 'GTP_DUAL_FAST' arenot appear in the model list, andsome models are lost too. WHY?

    How to correct the errors? Please help!
    Message Edited by hithust on 06-08-2009 08:51 PMMessage Edited by hithust on 06-09-2009 12:34 AMMessage Edited by hithust on 06-09-2009 01:39 AM

    DB:2.69:[Help]Problem With Bmd Simulation k9


    I don't believe that Modelsim supports SmartModels in 6.4.

    When you use secureip, make sure to add the reference to the library in your vsim command:

    vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L secureip -L work work.boardx04 glbl

  • RELEVANCY SCORE 2.68

    DB:2.68:Problem Launching Simulation In Vivado 2013.3 cd



    Hello,

    I'm running Vivado 2013.3 (64 bit) on a Windows 7 machine. Similar to a post from a couple days ago, I repeatedly get an error whenever I try to run a simulation:

    "ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.

    Please see the Tcl Console or the Messages for details.

    ERROR: [Vivado 12-2332] Received fatal error while launching XSIM application!"

    I've tried disabling the antivirus (I've browsed the antivirus quarantine folder as well) and tried other designs including the example designs and I always get this error. Also, there aren't any other messages associated with the error.

    Any help would be appreciated! Thanks!

    DB:2.68:Problem Launching Simulation In Vivado 2013.3 cd

    Hi,Try running dependency walker as I mentioned earlier and source 64-bit xsim.exe from win64.o folder.Thanks



    --------------------------------------------------------------------------------------------Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

  • RELEVANCY SCORE 2.68

    DB:2.68:Bmd Project Support Interrupt ? 39



    Hello:

    I have been doing DMA work of Pcie with XIlinx BMD project Demo. For interrupt, i have duzzle for it. Can anyone help me ?

    1、 Does BMD project Demo suported leagcy interrupt?

    The logic of cfg_interrupt_rdy_n and cfg_interrupt_n in BMD_INTR_CTRL.v of BMD project is conflicting with file describled in UG341.pdf. Can anyone tell me which is correct ?

    Actually, in Hardware test, I can get cfg_interrupt_rdy_n and cfg_interrupt_n signal time-relation with Chipscope. Please see picture(1) !

    But I can not get this leagcy interrupt in my Deiver tool (Windriver), meantime, the PCI STATUS register bit[3] is '0' at all times. So Is this leagcy interrupt really transmitted by FPGA ?

    2、 Does BMD project Demo suported MSI interrupt?

    If supported, so MSI should transmitt interrupt with Memory write request! But in BMD project, MSI MWR logic is not existent. Is this correct?

    THANKS!

    Message Edited by pzczly on 10-28-2009 05:59 PM









    Attachments:




    DB:2.68:Bmd Project Support Interrupt ? 39


    With legacy interrupts enabled, the pcie core has to first send an interrupt with "cfg_interrupt_assert_n" asserted, and then send another interrupt with "cfg_interrupt_assert_n" de-asserted.

    We found that the core wasn't sending a de-assert interrupt, because the driver has to initiate this by setting the LEGACYCLR bit in BMD Register # 18 :

    // 48-4BH : Reg # 18 // INTDI (RW) // INTDO // MMEN // MSIEN 7'b010010: begin if (wr_en_i) begin INTDI[7:0] = wr_d_i[7:0]; LEGACYCLR = wr_d_i[8]; end rd_d_o = {4'h0, cfg_interrupt_msienable, cfg_interrupt_mmenable[2:0], cfg_interrupt_do[7:0], 7'h0, LEGACYCLR, INTDI[7:0]}; end

    The interrupts worked once the driver was modified to do this.

  • RELEVANCY SCORE 2.68

    DB:2.68:Visual Simulation Environment Turn Black 17


    Hi, I face a problem in MRDS  , after i program VPL in MRDS and run simulation using a simulation xml file eg irobot , Lego Nxt ..visual simulation environment will appear to be black without any background..but Visual Simulation example that ready to use in MRDS can be seen. i attached with the error. -------------------------- None: SerializerService:Deserialize. Exception:There is an error in XML document (837, 11). Time: 4/21/2009 11:27:06 PM -------------------------- Error: Could not deserialize document: C:\Documents and Settings\TK\Microsoft Robotics Dev Studio 2008\6025ad31-9c9e-42d2-9c3a-91a909276c35\irobot.create.simulation (irobot.create.simulation.manifest) (irobot.create.simulation.manifest).xml Source: http://yeow:50000/mountpoint Code site: Void GetHandlerb__e(System.Exception)() at line:0, file Time: 4/21/2009 11:27:06 PM can anyone please help me with this problem?? THANKS!!

    DB:2.68:Visual Simulation Environment Turn Black 17

    I have the same problem, I have the previous version in another PC, it runs perfectly. Yesterday, I  downloaded the New version R2 to my another PC. I have the  same problem as above. All manifests have the same problem, some have black screen also, the error message are the same as below:--------------------------Error: Could not deserialize document: C:\Documents and Settings\To\Microsoft Robotics Dev Studio 2008 R2 Express\ca41c116-e7ce-4e7d-b886-750e73372393\irobot.create.simulationenginestate (irobot.create.simulation.manifest).xmlSource: http://to:50000/mountpointCode site: Void GetHandlerb__e(System.Exception)() at line:0, fileTime: 4/7/2009 16:19:43--------------------------I have tried to run the Visual Simulation Environment 2008 R2, almost all the sample are OK, therefore, it's not the problem of the display card?It's the R2 new version problem or my PC? My PC setting as belowCPU: E5200 IntelMB:   Gigabyte G31M-ES2CRam:4 GBSYS: windows XP SP3Display: Onboard DisplayNow I dare not to upgrade my previous Version to R2, Can anyone help?

  • RELEVANCY SCORE 2.67

    DB:2.67:System Generator Fails To Run Simulation With A Filter In Black Box m7



    Hi everyone!

    I started to build a simulation diagram in Simulink, using System Generator's provided blocks. It started out to be a simple design at first, just to try out how System Generator works. Firstly, I designed a lowpass FIR filter with FDATool in Matlab, exported it to a VHDL file. Then I added the black box to the Simulink design, selected the vhd file corresponding to the filter, and set the simulation mode to ISE Simulator. I ran the simulation, but nothing happened (by that I mean that no result has appeared on the scope). So I tried using ModelSim SE 6.2c as an external co-simulator. This time ModelSim has opened, and told me the following:

    # The System Generator simulation has terminated.

    # The System Generator co-simulation interface will now pause (but not terminate)

    # the ModelSim simulation so as to allow inspection of the design state.

    # simstats:

    # Simulation halt requested by foreign interface.

    # Simulation Breakpoint: Simulation halt requested by foreign interface.

    # MACRO ./filter_model_cosim_cw.tcl PAUSED at line 138

    I suspect there is a problem somewhere around System Generator and the Black Box and/or the filter. I have tried to simulate a different vhd file (with only combinatorial logic in it) and it worked without any problems.

    I would really appreciate any help or suggestions.

    Regards,

    Ferenc

    P.S. I am using the 10.1 version of System Generator and Matlab 2007b







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.66

    DB:2.66:Accept Simulation Is Not Working In Demantra 1d


    Hi,
    I am facing a problem with 'Accept simulation' feature in Collaborator workbench.
    After running simulation successfully, the simulation value is generated.
    Now when i accept simulation and rerun the worksheet, the simulation data disappears and my final forecast series is also empty.

    Ideally, it is supposed to empty the simulation data from the simulation series and populate the final forecast series, but 'accept simulation' is behaving like reject simulation feature where i loose the simulation data without getting it populated in final forecast series.

    Does anybody know the reason for this?
    Please help. It is urgent.

    Thanks,
    Ruby

  • RELEVANCY SCORE 2.66

    DB:2.66:Problem In Post-Map Simulation f3



    Hello guys , i know that this is my third message in 2 days , but i'm really new to this

    currently , after implementing my top module , i tried to do simple post-map simulation using ISim , on my core

    I started with a very simple test bench that only uses the rst signal , which is active low

    the problem is ... all output signals gives me x values ,

    I tried to simulate the same testbench on behaveoral model of the top module , and it worked just fine

    so , any hints of where may be the problem , I cannot observe internal signals inside the components in the post-map simulation

    Help please

    DB:2.66:Problem In Post-Map Simulation f3

    Are you still facing this issue? In case you have solved this issue yourself, kindly post the same for other users. If you need help, request you to post your code and testbench for others to check.



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.66

    DB:2.66:Pure Simulation 1x


    I posted this message on General Discussion and repost it
    here so that anybody with related experience could help me soon.

    I read an article and the author talked about guided
    simulation and pure simulation. The guided simulation is actually
    the training simulation in Captivate. The pure simulation,
    according to the article, featured the same controls and
    functionality as the real system. They did not provide any help
    while learners perform tasks. Has anybody created something similar
    as the "pure simulation"? Can we do it in Captivate? Please help.

    DB:2.66:Pure Simulation 1x

    I think that the use of a pure simulation would have limited
    value in training. However, I did create a simulation with no
    feedback and limited captions that only contained the minimum
    information to perform the job. I set up each interaction such that
    on the second miss on any interaction jumped to the end slide which
    stated "Dummy, You fail to complete the simulation with fewer than
    one error."

  • RELEVANCY SCORE 2.66

    DB:2.66:Problem With Modelsim Showing Internal Signals x7



    When doing behavioral simulation with ModelsimSE 6.4and adding internal signals to the wave display, all the internal signals show as 'U' whereas the toplevel signals running to my testbench show the actual values. What is the configuration to allow actual values on internal signals?

    I've checked help files, web searches, etc. but I do not see this issue addressed.

    Thanx.

    DB:2.66:Problem With Modelsim Showing Internal Signals x7


    Found the problem. L's and H's were causing problems. Switched to 0's and 1's and the waveforms are okay now.

  • RELEVANCY SCORE 2.65

    DB:2.65:Pcie Bmd Simulation Problem With Sp605 fj



    Hi,

    I am trying to simulate PCIe BMD for SP605 with ISim 13.2. I got a problem that PIO operation doesn't happen once Bus Master bit set. Here is my tests.vhd:

    elsif (test_selector = String'("bmd_write_test")) then writeNowToScreen(String'("Running bmd_write_test")); PROC_SYSTEM_INITIALIZATION(trn_reset_n, trn_lnk_up_n); PROC_BAR_INIT (tx_rx_read_data_valid, rx_tx_read_data_valid, rx_tx_read_data, trn_td_c, trn_tsof_n, trn_teof_n, trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk); PROC_TX_CLK_EAT(300, trn_clk);

    -- Set the DMA(2) and Interrupt(10) bit in cfg_command write (Lglobal, String'(" Writing cfg_command REG ")); --hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4))); writeline (output, Lglobal); PROC_TX_TYPE0_CONFIGURATION_WRITE ( X"06", x"004", x"00000404", X"F", trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk); PROC_TX_CLK_EAT(5000, trn_clk); -- Assert Initiator Reset write (Lglobal, String'(" Writing DCR1 With 0x01 ")); --hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4))); writeline (output, Lglobal); DATA_STORE(0) := X"01"; DATA_STORE(1) := X"00"; DATA_STORE(2) := X"00"; DATA_STORE(3) := X"00"; PROC_TX_MEMORY_WRITE_32 ( X"07", "000", "0000000001", BAR(0)(31 downto 0), X"0", X"F",'0', trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk); PROC_TX_CLK_EAT(100, trn_clk);

    ......(other BMD register operation)

    -- Write DMA Start write (Lglobal, String'(" Writing DCR2 With 0x01 ")); --hwrite(Lglobal, std_logic_vector(to_unsigned(i, 4))); writeline (output, Lglobal); DATA_STORE(0) := X"01"; DATA_STORE(1) := X"00"; DATA_STORE(2) := X"00"; DATA_STORE(3) := X"00"; addr := std_logic_vector(unsigned(BAR(0)(31 downto 0)) + X"04"); PROC_TX_MEMORY_WRITE_32 ( X"0d", "000", "0000000001", addr, X"0", X"F",'0', trn_td_c, trn_tsof_n, trn_teof_n , trn_trem_n_c, trn_tsrc_rdy_n, trn_terrfwd_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk); PROC_TX_CLK_EAT(100, trn_clk);

    From ISim only first two PIO operations happened. rest of them didn't happen. Once I move cfg_command writing operation down to bottom after BMD config operation, it seems I can see all BMD config operations. but another problem happened that is the second DMA will not happen becuase any PIO operation after first DMA will not happen. What am I missing here?

    Thanks,

    Jeff

    DB:2.65:Pcie Bmd Simulation Problem With Sp605 fj


    thanks for your reply. here is message from ISim Console:

    ISim

    # restart

    ISim

    # run all

    Simulator is doing circuit initialization process.

    at 0 fs: Note: [0 fs] : System Reset Asserted... (/board/).

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_SCMPCE_I_YESLUT6_U_SRL32/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_WLCMPCE_I_YESLUT6_U_SRL32/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_WHCMPCE_I_YESLUT6_U_SRL32/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_CDONE_I_YESLUT6_I_YES_RPM_U_SRL32_B​/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_CDONE_I_YESLUT6_I_YES_RPM_U_SRL32_A​/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_SCRST_I_YESLUT6_I_YES_RPM_U_SRL32_B​/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_SCRST_I_YESLUT6_I_YES_RPM_U_SRL32_A​/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_CMPRESET_I_YESLUT6_I_YES_RPM_U_SRL3​2_B/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_CMPRESET_I_YESLUT6_I_YES_RPM_U_SRL3​2_A/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS1_I_YESLUT6_I_YES_RPM_U_SRL32_D/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS1_I_YESLUT6_I_YES_RPM_U_SRL32_C/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS1_I_YESLUT6_I_YES_RPM_U_SRL32_B/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS1_I_YESLUT6_I_YES_RPM_U_SRL32_A/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS0_I_YESLUT6_I_YES_RPM_U_SRL32_D/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS0_I_YESLUT6_I_YES_RPM_U_SRL32_C/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS0_I_YESLUT6_I_YES_RPM_U_SRL32_B/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_I_SRLT_NE_1_U_NS0_I_YESLUT6_I_YES_RPM_U_SRL32_A/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_SCNT_CMP_I_CS_GAND_U_CS_GAND_SRL_​I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SET​_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLA/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_SCNT_CMP_I_CS_GAND_U_CS_GAND_SRL_​I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SET​_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLB/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_SCNT_CMP_I_CS_GAND_U_CS_GAND_SRL_​I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SET​_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLC/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_HCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLA/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_HCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLB/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_HCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLC/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_LCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLA/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_LCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLB/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    at 0 fs, Instance /board/EP/CS_ila/U0_I_NO_D_U_ILA_U_G2_SQ_U_CAPCTRL​_U_CAP_ADDRGEN_U_WCNT_LCMP_I_CS_GAND_U_CS_GAND_SRL​_I_S6_U_CS_GAND_SRL_S6_I_USE_RPM_NE0_U_GAND_SRL_SE​T_I_PARTIAL_SLICE_U_GAND_SRL_SLICE_U_SRLC/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    [ 0 ns ] : CoreName = s6_pcie_v1_4

    [ 0 ns ] : Running bmd_write_test

    Finished circuit initialization process.

    at 3996 ns(3): Note: [3996000000 fs] : System Reset De-asserted... (/board/).

    [ 40324.246 ns ] : Transaction Reset is De-asserted

    [ 114400.246 ns ] : Transaction Link is Up

    [ 114400.246 ns ] : PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN..

    BAR 0 = 0x10000000 RANGE = 0xFFFFFC00 MEM32 MAPPED

    BAR 1 = 0x00000000 RANGE = 0x00000000 DISABLED

    BAR 2 = 0x00000000 RANGE = 0x00000000 DISABLED

    BAR 3 = 0x00000000 RANGE = 0x00000000 DISABLED

    BAR 4 = 0x00000000 RANGE = 0x00000000 DISABLED

    BAR 5 = 0x00000000 RANGE = 0x00000000 DISABLED

    BAR 6 = 0x00000000 RANGE = 0x00000000 DISABLED

    [ 114400.246 ns ] : Setting Core Configuration Space...

    [ 114412.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 114824.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 115236.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 115648.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 116060.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 116472.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 116884.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 117296.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 117708.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 117788.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 118236.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 118716.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 119132.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 119612.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 120028.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 120476.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 120924.146 ns ] : PROC_PARSE_FRAME on Receive

    [ 121372.146 ns ] : PROC_PARSE_FRAME on Receive

    Writing cfg_command REG

    [ 122920.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing DCR1 With 0x01

    [ 124132.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing DCR1 With 0x00

    [ 124544.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing WDMATLPA With 0x00

    [ 124956.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing WDMATLPS With 0x00

    [ 125368.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing WDMATLPC With 0x00

    [ 125780.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing WDMATLPP With 0xFEEDBEEF

    [ 126192.146 ns ] : PROC_PARSE_FRAME on Transmit

    Writing DCR2 With 0x01

    [ 126604.146 ns ] : PROC_PARSE_FRAME on Transmit

    [ 130460.146 ns ] : PROC_PARSE_FRAME on Receive

    Stopped at time : 171596104 ps : File "v:/hipsBuilds/O_hips_v19.0/rst/hips/gtpa1_dual/GT​PA1_DUAL_all_enc.v" Line 61894

    ISim

    there is no error during simulation. but the DMA did not happen.

  • RELEVANCY SCORE 2.65

    DB:2.65:Multimeter Problem 3z



    Hi,

    I was using NI Multisim 11.0 for making an electric circuit with a piezoelectric element as a AC source of energy (15 V). It looks like this.

    When I run a simulation, it shows:Error Message From Simulation: tu1: transmission line z0 must be given. Could you help me solve this problem, since this was my first time working in this program?

    Thank you.

    DB:2.65:Multimeter Problem 3z


    Hi,

    The MAX1675 component does not have a SPICE model, that's why the simulation doesn't work. Right-click the component and select Properties, go to the Value tab, you will see that the Edit model button is disabled since this feld is empty.

    I tried to find amodel for this component in the vendor's websitewith no luck.

    Regards,




    Fernando D.National Instruments

  • RELEVANCY SCORE 2.64

    DB:2.64:Hardware Co-Simulation: Java.Lang.Nullpointerexception jx



    Hi,

    when I try to generate a hardware co-simulation target (ML402 Ethernet P2P) from the example code in

    Xilinx/12/ISE_DS/ISE/sysgen/examples/shared_memory/hardware_cosim/conv5x5_video/

    I get the following error:

    Begin generation Checking model status Checking simulation times Performing compilation and generation Compilation and generation completed in 875.1302 seconds*** ERROR ***An error was encountered while compiling the design for hardware co-simulation. Please refer to hwcosim_compile_error.log for details.

    Checking the contents of hwcosim_compile_error.log does not reveal much:

    Java exception occurred: com.xilinx.sysgen.netlist.NetlistInternal: at com.xilinx.sysgen.netlist.PerlScripter.quickCall(Unknown Source) at com.xilinx.sysgen.netlist.PerlScripter.quickCall(Unknown Source) at com.xilinx.sysgen.netlister.m.a(Unknown Source) at com.xilinx.sysgen.netlister.m.if(Unknown Source) at com.xilinx.sysgen.netlister.m.do(Unknown Source) at com.xilinx.sysgen.netlister.HwcosimWrapperBuilder.a(Unknown Source) at com.xilinx.sysgen.netlister.HwcosimWrapperBuilder.buildHwcosimFiles(Unknown Source)

    I get this with both MATLAB 2009a and 2009b (ISE 12.1). Any help tracking down the source of this problem is much appreciated!







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.64

    DB:2.64:Strange Mux Simulation am



    I am getting the "X" signal for simple mux simulation, what could cause this problem?

    with mux_txF select tx_w_data = cal_req_w_data when '0', peripheral_data when '1';







    Solved!
    Go to Solution.

    DB:2.64:Strange Mux Simulation am


    Now i tried to implement design and it showed an error "Signal is connected to multiple drivers". When i solved this, the simulation problems were gone.

    It is strange that simulation does not report this error.

  • RELEVANCY SCORE 2.64

    DB:2.64:In Simulation Bmd Not Read Request And Completions 7f



    Hi all,

    I want to simulate BMD by modelsim se 6.5.

    I have a htg v5 fx100t board , and now i am trying to understand how BMD (xapp1052) works . i did it step by step like this

    1. I generated the integrated block for pci express v1.15 (verilog)

    2. after that i put folder from xapp1052.zip in my PCIe folder

    3. for Simulation i used all source files in folder dsport ( rootport) and for unit under test i used all bmd files instead of Pio files

    4. i have changed pcie_2_0_rport_v6.v file such as AR33918

    5.Replace the pci_exp_usrapp_cfg.v with the one that is included in the zip file in AR33918

    6.Call the task TSK_WRITE_CFG_DW in testbench (AR33918)

    board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000004, 32'h00000007, 4'b1110); 

    7. then i start to write the length , amount , address and finally start the Memory read Request test such as "dma_mrd_test".

    vsim +notimingchecks -t 1ps +TESTNAME=dma_mrd_test -voptargs="+acc" -L work -L secureip -L unisims_ver \ work.board glblrun -all

    Result

    1. after starting the memory Read request ( mrd_start was set ) , BMD not sent any mermory read request.

    please help me solve this problem.

    thetranscript result attached.

    and "dma_mrd_test" is:

    **************************************************​**************************************************​**********************else if(testname == "dma_mrd_test")begin TSK_SIMULATION_TIMEOUT(5050); //System Initialization TSK_SYSTEM_INITIALIZATION; TSK_BAR_INIT; $display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID); //Read command reg $display("[%t] : Read Command Reg",$realtime); fork TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG,12'h04​,4'hF); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_WAIT_FOR_READ_DATA; join $display("[%t] :Command Reg Data is :%x", $realtime, P_READ_DATA); //Set the DMA(2) and Interrupt(10) bit in command P_READ_DATA = P_READ_DATA | 32'h0404; $display("[%t] :New Command Reg Data is :%x", $realtime, P_READ_DATA); //Write Command Reg $display("[%t] : Write Command Reg",$realtime); fork TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG,12'h0​4,P_READ_DATA[31:0],4'hF); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join //------------------------------------------------​-------------------------- // Write DMA configuration //------------------------------------------------​-------------------------- $display("[%t] : Writing DCR1 With 0x01", $realtime); fork data=32'h01; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,​1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing DCR1 With 0x00", $realtime); fork data=32'h0; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,​1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPA", $realtime); fork data=0; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h1c,4'b0,4'hF​,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPS", $realtime); fork data=32'h20;//tlps; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h20,4'b0,4'hF​,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPC", $realtime); fork data=32'h10;//tlpc; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h24,4'b0,4'hF​,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing DCR2 With 0x00010000", $realtime); fork data=32'h00010000; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h04,4'b0,4'hF​,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $finish;end**************************************************​**************************************************​**********************

    thank you very much,

    armando.

    










    Attachments:







    transcript1 ‏33 KB

    DB:2.64:In Simulation Bmd Not Read Request And Completions 7f

    Hi luisb,What about those tasks TSK_EXPECT_MEMWR or TSK_EXPECT_MEMRD? I'm trying to use first one but always get message "TEST FAILED --- Haven't Received All Expected TLPs".

  • RELEVANCY SCORE 2.64

    DB:2.64:Re: Simulation Cfd 2013 Result Problem zc



    i read every toturials about thermal comfort

    i model a room with an occupant,i tried to inter a 0.1 m/s velocity to the room with boundry condition on window

    the first few times i get the result but now it show temperature without change inside of the room and the plane result doesnt work anymore,i tried to reinstall it but nothing happend,i really need help bcuz i need those result for my thesis







    Solved!
    Go to Solution.

    DB:2.64:Re: Simulation Cfd 2013 Result Problem zc


    Again, you didn't post the image so I can't know your definition of linear

    The reason for its flatness may be that that there is hardly any change in it over the iterations, meaning, probably the initial guess was too good for the temperature hence it didn't need significant changes during iterations and there aren't large temperature differences in the room so the average temperature didn't change drastically over the region. Also, you may want run for more iterations until your pressure, velocity and turbulence numerics also gets flatter.

  • RELEVANCY SCORE 2.64

    DB:2.64:Pcie Bmd Reference Design zm



    Hi ,

    I'm trying to integrate PCIe endpoint reference design with theBMDexample design of XAPP1052, the documentation of XAPP1052 recommends to run the design in fedora 10 but iam using REDHAT linux. Is there any issue in running the bmd reference design in REDHAT

    Thanks in advance.

    DB:2.64:Pcie Bmd Reference Design zm

    Hi...Does xilinx provide any application to send image continuously from fpga(ml605) to PC using PCIeThanks in advance

  • RELEVANCY SCORE 2.64

    DB:2.64:Simulation Of Bmd(Xapp1052) m1



    After I have written the DMA control registers, the BMD send mrd requests in trn_td,

    but I cannot get the requests in trn_rd of RP,Why?

    I use the test bench gernetated by corgen:

    else if(testname == "dma_mrd_test")begin TSK_SIMULATION_TIMEOUT(5050); //System Initialization TSK_SYSTEM_INITIALIZATION; TSK_BAR_INIT; $display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID); //Read command reg $display("[%t] : Read Command Reg",$realtime); fork TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG,12'h04,4'hF); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_WAIT_FOR_READ_DATA; join $display("[%t] :Command Reg Data is :%x", $realtime, P_READ_DATA); //Set the DMA(2) and Interrupt(10) bit in command P_READ_DATA = P_READ_DATA | 32'h0404; $display("[%t] :New Command Reg Data is :%x", $realtime, P_READ_DATA); //Write Command Reg $display("[%t] : Write Command Reg",$realtime); fork TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG,12'h04,P_READ_DATA[31:0],4'hF); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join //-------------------------------------------------------------------------- // Write DMA configuration //-------------------------------------------------------------------------- $display("[%t] : Writing DCR1 With 0x01", $realtime); fork data=32'h01; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing DCR1 With 0x00", $realtime); fork data=32'h0; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h0,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPA", $realtime); fork data=0; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h1c,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPS", $realtime); fork data=tlps; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h20,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing RDMATLPC", $realtime); fork data=tlpc; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h24,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $display("[%t] : Writing DCR2 With 0x00010000", $realtime); fork data=32'h00010000; DATA_STORE[0] = data[7:0]; DATA_STORE[1] = data[15:8]; DATA_STORE[2] = data[23:16]; DATA_STORE[3] = data[31:24]; TSK_TX_MEMORY_WRITE_32(DEFAULT_TAG, DEFAULT_TC,10'd1,BAR_INIT_P_BAR[0]+8'h04,4'b0,4'hF,1'b0); DEFAULT_TAG = DEFAULT_TAG + 1; TSK_TX_CLK_EAT(100); join $finish;end

    The Simulation retrun errors:

    XILINX_PCIE_311 : RECEIVED UNSUPPORTED REQUEST COMPLETION.

    DB:2.64:Simulation Of Bmd(Xapp1052) m1


    I have resolved this problem by AR33918.thanks.

  • RELEVANCY SCORE 2.64

    DB:2.64:Firefox Cannot Find Server, No Problem Before. m1



    I have a folder in my yahoo mail named bmd, when I click it comes up but then firefox says it cannot find server. I have been using this web site for months with no problem.

    This is a legitimate site for unwanted ancestry certificates.
    it doesnt work either when I use the search engine.
    Please help, thank you.

  • RELEVANCY SCORE 2.64

    DB:2.64:How To Measure Simulation Time With System Generator For Hardware Co-Simulation? 9j



    I am using hardware co-simulation now , and I find xapp1031.pdf is very helpful. But I have a question that how to measure simulation time with system generator for hardware co-simulation?

    Could anyone help me ?

    Thanks!

    DB:2.64:How To Measure Simulation Time With System Generator For Hardware Co-Simulation? 9j

    As per the Xapp1031 note, various timing results are shown in table form e.g (Table 6: Simulation Runtimes for Software-based Shared FIFOs , page 21)
    If we read it carefully , they never mentioned any script or file in the generated folder which shows those numbers which they displayed in various tables except for model implementation_2 ( for which one script is given for modelsim).

    I have a big doubt Is there any ways to get these results , since an excel sheet is given to make our own results in their format( but how?).

    lastly i am interested to get timing for my model for parameters like table 6 for various implmentation
    Simulink: Outside System Generator
    Sysgen: Block Configuration
    Sysgen: Compile
    Sysgen: Initialize Simulation
    Sysgen: Simulation

    please help me!
    thanks
    gaurav

  • RELEVANCY SCORE 2.64

    DB:2.64:Post Synthesis Simulation Error, But Behaviorial Simulation Is Correct zf


    I used vivado 2014.1 and win7 64 bits to run simulation for my custom IP.

    Behaviorial simulation is correct and I get the correct wavefroms from simualation.

    But it failed inpost synthesis Simulation .

    One of the errors:

    [VRFC 10-35] reg_ctrl_sts_S00_AXI_default has no port called ADC_enable ["C:/**/Data_Mover_Bridge_v1_01_project.sim/sim_top_module/synth/timing/TB_data_mover_bridge_time_synth.v":7156]

    Actually the module ofreg_ctrl_sts_S00_AXI does not have anyport called ADC_enable .

    Very confused with this error.

    Log file is attached.

    Please help.

    Thank you.Sam










    Attachments:







    xelab.log ‏27 KB

    DB:2.64:Post Synthesis Simulation Error, But Behaviorial Simulation Is Correct zf

    In that case, I would suspect this to be a project corruption issue. You may also try to create a new project and add the files/IP to run simulation.



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.63

    DB:2.63:Problem With Post Place And Route Simulation Xilinx Ise 8.1i, pf


    I am using Model SIM SE 5.7G. When I design my code in Xilinx, even after sythesizing it without any error messages, my code does not give Post Place and Route Simulation. What am I doing wrong?? Can any one help?? Naeem Jan Amin

    DB:2.63:Problem With Post Place And Route Simulation Xilinx Ise 8.1i, pf

    I am using Model SIM SE 5.7G. When I design my code in Xilinx, even after sythesizing it without any error messages, my code does not give Post Place and Route Simulation. What am I doing wrong?? Can any one help?? Naeem Jan Amin

  • RELEVANCY SCORE 2.62

    DB:2.62:Simulation Interface Toolkit Not Working kd



    I am working on a simulation and control problem using LABVIEW and Matlab. I have installed the simulation interface toolkit. But, the SIT server is not running. I have added the lines:

    "addpath('C:\SimulationInterfaceToolkit'); NISIT_AddPaths; NISITServer('start',6011);"

    in the matlabrc.m file. The NI SIT blocks are available in the simulink library. When I start matlab, the line:

    " SIT: Added paths for Simulation Interface Toolkit 2011" appears. But the lines: "Starting the SIT Server on Port 6011 SIT Server started" don't show when matlab starts. I am attaching the Matlab startup screen.

    Please help me out with this.

    Thank You










    Attachments:







    Matlab Startup Screen.PNG ‏101 KB

    DB:2.62:Simulation Interface Toolkit Not Working kd


    OK I solved )))

    Try the follwowing:

    1- uninstall Labview and Matlab and the simulation interface toolkit (SIT) (be sure that u have only one version from SIT)

    2- If you are going to use SIT 2011...then you will need Labview 2011 for sure and Maximum version of Matlab 2010 I think.

    Revise the combatibility of SIT with Matlab on google

    Be sure to use MATLAB 32-bit version

    hope it will help

    thanks




    A.Hakim

  • RELEVANCY SCORE 2.62

    DB:2.62:Value Driver Tree In Sem-Cpm d8



    Dear all,

    Iam facing a problem in copying actual or plan value fields to the simulation value field in my value driver tree with simulation presentation in web version.

    when i click copy button by giving plan value field in source field and simulation value field in target field values are not copying to simulation field.

    while assigning simulation value field to value driver tree, i defined like this..

    simulation value field : SIM1 value type : 30 this 30 is defined in the master data of value type. iam using value type instead of version. Is this causing problem?

    Please help me. Any suggestions will be appreciated..

    Thanks and Regards

    Rajesh

    DB:2.62:Value Driver Tree In Sem-Cpm d8


    Hello Rajesh,

    it seems like the assignement to planning elements is incorrect (or incomplete). Please check documentation at link http://help.sap.com/saphelp_erp2005vp/helpdata/en/48/90ad3998693f51e10000000a114084/content.htm (especially the tables describing the prerequisities and the mapping).

    Best regards,

    Ludek

  • RELEVANCY SCORE 2.61

    DB:2.61:Xapp1052:Problem With Installing The Driver 81



    Hello,

    I'm currently trying to do thisdocument design flow step by step.

    I create a route.bit file(BMD design) and use JTAG download to the board.

    Unfortunately after a warm reset,computer can't find thisPCIe device.

    But I create a route.bit file(PIO design),computer can find this PCIe device.

    How can I solve this problem?

    thanks

    Yi - Chun Chen

    DB:2.61:Xapp1052:Problem With Installing The Driver 81


    Hello,

    I'm currently trying to do thisdocument design flow step by step.

    I create a route.bit file(BMD design) and use JTAG download to the board.

    Unfortunately after a warm reset,computer can't find thisPCIe device.

    But I create a route.bit file(PIO design),computer can find this PCIe device.

    How can I solve this problem?

    thanks

    Yi - Chun Chen

  • RELEVANCY SCORE 2.60

    DB:2.60:Problem With Core Simulation... 1j


    Hello friendsI downloaded a JPEG Compressor from http://www.opencores.org/projects.cgi/web/jpeg/overview...I have some problem to simulate it with ISE Foundation...Is there any one can help me?I need it heavily...Amir.yazdanbakhsh@gmail.comthx a lot

    DB:2.60:Problem With Core Simulation... 1j

    Hello Amir,Running through Translate (NGDBuild) should pull all of your netlists (which that core is using) into one NGD file. When NGDBuild is parsing these netlists it will report on any apparent problems it sees. This will also enable you to do a Post-Translate simulation and everything should work fine. If you try to run a behavioral simulation, then the tools do not know how that core should behave. A behavioral simulation actually uses the simulator to compile the HDL source. ISE Simulator (ISIM) is looking at that netlist as a black box. For most of the cores that are designed to work with Xilinx tools, the cores have a behavioral model. This behavioral model instructs the simulator how that black box will behave. With this core that you are trying to use, you cannot expect to have a behavioral model automatically generated. Try just running with a Post-Translate simulation.-Ill

  • RELEVANCY SCORE 2.60

    DB:2.60:Problem In Pausing Chart Inside A Simulation Loop 83



    Dear Sir

    I posted these files before but I added again under the simulation loop discussion because I need any help about:

    I. Modifying the clear button to clear the graph and also initialize the simulation time to restart again.

    2. Modifying Pause button to let the chart to pause during simulation










    Attachments:






    chart problem.vi ‏57 KB

    DB:2.60:Problem In Pausing Chart Inside A Simulation Loop 83


    Hey Ahmad,

    Since you are looking to work with ODE, the simulation loop may be a better choice for your application. One of the problems you are seeing in your example code in regards to pausing, when you press your 'pause' button, you are getting zero's because you are not pausing your simulation. You are simply not passing your calculated values to your waveform. So what you really want to do is pause your application. This would be very do-able with that timed loop or as Baji has done in his example. However, like Baji pointed out, you cannot use the front panel objects in a simulation loop. So, pausing you application would be difficult. One possibility would be to simply use the 'Pause' option on your execution toolbar.

    Also, in terms of the clear button. It sounds like you are more interested in restarting the simulation so it may be useful to stop your simulation loop using the Halt vi (Functions»Control Designand Simulation»Simulation»Utilities»Halt Simulation).Then,since your simulation loop is within a while loop,you will restart the simulation.

    Hope this helps.

    -Ben




    Hope this helps.-BenWaterlooLabs

  • RELEVANCY SCORE 2.60

    DB:2.60:Pcie Bmd Design On Sp605 Using 14.2 jx



    I am new to FPGA based PCIe implementations. I am trying to get the XAPP1052 BMD design to work in a SP605. I generated the core and created a Project with the needed source code. (I could not use the scripts on 14.2) The project builds and generates a bit file without any problem. I can load this bit file into the demo board, also without an issue. However, the PCIe link is never established.

    I know the SP605 board works and the PC is OK. I know this because I can build the PIO example and it will link on the PC. With the JTAG cable, I can alternate between the PIO and BMD designs and see the link go up and down on the PC.

    I checked the UCF files and the two designs are using the same pins for IO. I opened the BMD design in FPGA editor and it all seems to be there, at least as far as I can tell.

    The one major difference between the two designs is the PCIe Core. For the BMD design, I had the generate the core. The PIO example from the SP605 reference design already had the PCIe Core included.

    Questions:

    Are there some tricks to configuring the PCIe core that are no in the XAPP1052 docs?

    Has anyone built this reference design on 14.2 for the Spartan6?

    Any hints what to try next?

    Thanks.

    DB:2.60:Pcie Bmd Design On Sp605 Using 14.2 jx


    I got it working. There were two problems.

    1. XAPP1052 has a UCF for the SP605. However, the pin assignments for the LEDs are commented out in that UCF. Therefore, until you fix the UCF, there will be no LED indicators.

    2. The second problem was that my Navigator Project file was corrupted. 14.2 had crashed badly trying to simulate PCIe before I got the SP605 demo board. This crash corrupted my project file. Even though I listed the UCF as a source file and the tree view correctly displayed that it was associated with the top module, the UCF was being ignored during PAR. Inside the project file I found:

    bindings binding xil_pn:location="/board" xil_pn:name="../../dma_performance_demo/fpga/implement/ucf/xilinx_pci_exp_s6_1_lane_ep_sp605.ucf"/ /bindings

    The ucf was being bound to a "board.v" file that was part of the simulation that crashed. That file did not exist any more. Navigator threw no warnings or errors, it just ignored my ucf constraints and assigned the pins where it felt like.

    The hard thing in finding this is that I looked at the design in FPGA Editor and verified that the PCIe signals were on the correct pins. These apparently defaulted to the correct pins. The gotcha was System Reset. That signal was being assigned to a random pin since there was not an active UCF and the design was continually stuck in reset.

  • RELEVANCY SCORE 2.60

    DB:2.60:Problems With Post Translate Simulation 7j



    Hi all,

    I am a beginner in FPGA. I have designed and implemented one small project. The function(behavioral) simulation is OK. But the post translate simulation is wrong. I do not have any clue for the problems.

    Also when I generate post translate model there is exclamation sign(?) on each of the port of my design entity. maybe this is the problem. Please help me in this problem. How can I solve this problem.

    Regards,

    Khursheed

    DB:2.60:Problems With Post Translate Simulation 7j


    Could you please give more information on the simulation. Dose it stop? or give 'X' output?

  • RELEVANCY SCORE 2.60

    DB:2.60:Simulation In Real Time 11



    Hi,

    I need help for my labview program.

    I am using ETS desktop PC as RT target and LV 8.2. My program contains three loops running at different time period. One loop is simulation loop(Control Design and simulation toolbox) I would like to execute the other loops after certain number of simulation loop cycles. My simulation loop time is 1ms and I am using RK 4th order ODE solver.Other two loops should run after every 20ms and 1s resp.

    My problem is how to count the time in simulation loop and send notification to other loops for execution and stop simulation loop until the other loop finishes its one cycle. I tried with "wait" for 20ms and 1s in while loop but as the whole program runs on real time, the while loop stops running and simulation loop takes over. I want the while loop to complete its function and then the simulation loop start.

    Please help me out.

    Rashmi

    DB:2.60:Simulation In Real Time 11


    The Timed Loop was for demonstration. As I indicated, I don't have the Control and Simulation module, so I can't create a Simulation Loop. I used the Timed Loop as a replacement. I wrote the VI so you could run it and see its behavior to determine if that's what you were looking for, conceptually. Obviously, you should use the Simulation Loop in your real code.

  • RELEVANCY SCORE 2.60

    DB:2.60:Instantiated Cores Undefined Outputs 9d



    Hello!

    I've got problem with simulating my design. It's modified version of PCIE SG DMA project from opencores.

    Project consists of VHDL desing and Verilog testbench.

    During simulation, *all* FIFO and BRAM cores have undefined outputs (I don't test PCIe core).

    Hovewer, simulation script provided with FIFO core works OK (I mean ipcore_dir/fifo/simulation/...).

    Additionaly I get some warnings in console when opening project, e.g.:

    WARNING:ProjectMgmt - Duplicate Design Unit 'sfifo_15x128' found in library 'work'
    WARNING:ProjectMgmt - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x1​28.vhd" line 43 (active)
    WARNING:ProjectMgmt - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x1​28_synth.vhd" line 57

    and when starting simulation:

    WARNING:HDLCompiler:685 - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x1​28_synth.vhd" Line 57: Overwriting existing primary unit sfifo_15x128

    Cleaning project files or regenerating cores didn't help.

    I've got "`timescale 1ns / 1ps" directive in Verilog file and I'm holding reset for 101 ns.

    I use ISE 14.2.

    DB:2.60:Instantiated Cores Undefined Outputs 9d

    Is it possible that ISim is picking up wrong files, I mean fifo_synth.vhd instead of fifo.vhd?Could that be a reason? How to fix it?

  • RELEVANCY SCORE 2.60

    DB:2.60:Veriog Simulation Models ms



    I have a problem with post synthesis verilog simulation models.

    The model ignores any inputs for the first 100 ns like it's in the reset state. I read HEREthat the reset pulse width is only available for translate,map,par. So, how i can i deal with this issue for the post synthesis model ?

    This problem does not exist in vhdl models

    The command i use is:

    netgen top_entity_name.ngc -sim -ofmt verilog

    Any help ?

    Thanks in advance

    DB:2.60:Veriog Simulation Models ms


    I have a problem with post synthesis verilog simulation models.

    The model ignores any inputs for the first 100 ns like it's in the reset state. I read HEREthat the reset pulse width is only available for translate,map,par. So, how i can i deal with this issue for the post synthesis model ?

    This problem does not exist in vhdl models

    The command i use is:

    netgen top_entity_name.ngc -sim -ofmt verilog

    Any help ?

    Thanks in advance

  • RELEVANCY SCORE 2.60

    DB:2.60:Problem In Simulation And Synthesis zx



    why does the ouput remain uninitialised plz help







    Solved!
    Go to Solution.

    DB:2.60:Problem In Simulation And Synthesis zx


    Post-translate simulation works fine for me. Is the clock signal behaving correctly in the waveform window?

    Your code still has a couple of problems, though:

    count "11" is always false, because count is only 2 bits wide.
    If you have a continuous signal assignment to counter_state, then you shouldn't give it an initial value (because counter_state is not a register). The same applies to output signals in your testbench.
    Do not use the packages std_logic_arith or std_logic_unsigned. Replace them with numeric_std, and use the types unsigned and signed instead of std_logic_vector when you want to model an unsigned or signed number.
    Use rising_edge(clk) instead of clk'event and clk='1'.




    Please google your question before asking it.If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

  • RELEVANCY SCORE 2.60

    DB:2.60:Xapp1052 Dma Simulation Help pa



    hi to all,

    I have extracted the core as described in XAPP1052 doc and implement the design it is working fine .

    Now i want to do is to add another register on BAR0. but didnt get any idea to where to put that .

    So that i have decided to simulate BMD design .

    now i have to replaced PIO with BMD design can any body help me out in setting simulation and help me out in adding up an another register.

    With best regards,

    DB:2.60:Xapp1052 Dma Simulation Help pa


    hiy2k_eng,

    i have the same problem with u . When i simulate the PCIE dma project ,signal "trn_lnk_up_n" is always deasserted . i found that u said u have solved the problem . U say "Simulation is now running actually i havent Define PCIE2_0 in simulate_mti.do fiie." , what do u mean ? How to "Define PCIE2_0 in simulate_mti.do " ? This is my .do file , are there anything that i should add ?

    i use v6 board and followed xapp1052 to design the bmd prj.

    This is my simulate_mti.do file:

    vlib workvmap workvlog -work work +incdir+../.+../../example_design+../../dma_perfor​mance_demo/fpga/BMD/common+../../dma_performance_d​emo/fpga/BMD \ +define+SIMULATION +define+PCIE_2_0\ +incdir+.+../dsport+../tests \ -f board.f

    vsim -voptargs="+acc" +notimingchecks +TESTNAME=sample_smoke_test0 -L work -L secureip -L unisims_ver \ work.board glbl +dump_all

    run -all

    i'll appreciate any reply . thanks in advance .

    Winard

    2013.5.14

  • RELEVANCY SCORE 2.59

    DB:2.59:Endpoint Block Plus 1.9 And Post-Route Simulation d8



    Hi everyone, can anybody point me out how to do the post-route simulation of the endpoint block plus 1.9? I've got no problem to run the behavioural simulation, but I cannot succeed in doing all the others (post-translate, post-map...). I'm working with Ise 10.1 and modelsim SE 6.4.

    Thanks in advance for the help

    DB:2.59:Endpoint Block Plus 1.9 And Post-Route Simulation d8


    Hi everyone, can anybody point me out how to do the post-route simulation of the endpoint block plus 1.9? I've got no problem to run the behavioural simulation, but I cannot succeed in doing all the others (post-translate, post-map...). I'm working with Ise 10.1 and modelsim SE 6.4.

    Thanks in advance for the help

  • RELEVANCY SCORE 2.59

    DB:2.59:Isim Ramb36 Simulation 91



    Hello everyone,

    I'm working with ISIM for 2 weeks now and it seems to be a very good free simulation tool.

    Now I'm trying to simulate read/write from/to an BRAM. In Modelsim there was the

    possibility to view the content of the BRAM when the simulation was stopped but in ISIM

    I didn't find this option.

    Can anyone help me please!?

    Thanks,

    Peter

    DB:2.59:Isim Ramb36 Simulation 91


    Hi,

    my approach is not a good solution but works: Just read out the BRAM within 512 ticks, 64 Bits each and

    write the values into a file (or console). This should be no great problem at the end of your simulation.

    Jotta

  • RELEVANCY SCORE 2.59

    DB:2.59:Rldram Ii Mig 3.6 Read Simulation Problem d1



    Hi,

    I have problem with MIG controller for RLDRAM II. I write the simple simulation code for read/wirte tomemory. All things ( reads and writes ) appears good in conjuction with memory model, but when i want to pass data from readFIFO of MIG to user interface, only higher bits of data transferred ( red color sectionon below schematicshows this).

    Please help me to underestand what's the problem.

    Thanks.










    Attachments:




    DB:2.59:Rldram Ii Mig 3.6 Read Simulation Problem d1


    Hi,

    If you are using your own testbench please compare MIG genarted sim_tb_top against your for all the paramters.

    Also I would suggest just to replcae tarffic gen and hook your User interface FSM so that there will be less variables.




    ---------------------------------------------------------------------------------------------Please do google search before posting, you may find relavant information.Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

  • RELEVANCY SCORE 2.59

    DB:2.59:Buffering Problem In Simulation xx


    hi..I have a question and i want help from you please..
    I have project but the simulation some time show different result in different run time
    is this related with buffering simulation ..?
    how can solve the problem and deletepreviousvalues
    Thank you

    DB:2.59:Buffering Problem In Simulation xx

    We have not heard back from you in a while. I hope you have resolved the issue. If not, please pose a new question (since answered ones are not as easily noticed) and please try to answer Ashley's questions.

  • RELEVANCY SCORE 2.59

    DB:2.59:Simulation Library Compilation Wizard Does Not Select Modeslim De 93



    When I launch the Simulation library compilation wizard gui, only one simulation option is available.

    modelsim SE

    The otherfour options e.g. PE, DE, Questa Sim, Riviera-PRO are grayed out so I cannot select modesim DE.

    Consequently, the compilation fails.

    I am using ISE 12.3 with windows 7 professional.

    modelsim DE

    Does anyone else have this problem?

    Does Xilinx ISE 12.3 suport this feature in windows 7.

    I tried to use compxlib -help in a command window, but the command is not recognised.

    I uninstalled xilinx and reinstalled again. But still have the same problem.

    Any suggestions are much appreciated.

    thanks







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.59

    DB:2.59:Modelsim Simulation Problem?? m1


    Hello,

    I am working on a vhdl project and i have a problem when i want to make a behavioral simulation...

    - I compile the project : OK
    - I then go to the Simulate Menu/Start simulation.
    - a Popup windows open asking me to select a module.
    - I select the TestBensh/behavioral module.

    And then, nothing happens... I only have "Loading..." at the bottom of the windows.....

    If i wait, i get, after a quite long time : "# Error: Failed to start simulation kernel"

    Could you help me please?

    Sincerely,

    Alex

    DB:2.59:Modelsim Simulation Problem?? m1


    It seems that this problem is caused by the wrong version of DBGHELP.DLL shipped with ModelSim. Try to copy “%SystemRoot%\system32\dbghelp.dll” to "ModelSim install folder\win64(or win32)" and see if it can solve this problem.

  • RELEVANCY SCORE 2.59

    DB:2.59:Problem With Gtx Post-Route Simulation ? pk



    Hello,I am doing the simulation of V5 GTX.

    main parameter:target line rate = 4Gbps,

    Reference Clock=125MHz,

    single lane,GTX_DUAL location X0Y5.

    The behavioral simulation works well and the rx datas(output) are right. But if i try to do post-route simulation,the phenomenon of rx data errors arises . Pleasehelp me. what's the possible reason?

    DB:2.59:Problem With Gtx Post-Route Simulation ? pk


    hello,

    what is the ISE release you are using?

    please, what is the error you find? if you do a near end PCS loopback simulation - do you still find errors?

    thanks,

    GG

  • RELEVANCY SCORE 2.59

    DB:2.59:Timing Simulation With A Simulated Ad Converter zz



    Hi,

    I try to simulate a Spartan-6 design with a simulated AD converter. In behavioral simulation there is no problem. In timing simulation the outputs of the modelAD7655 are undefined. The real design is working.

    Attached is the the top level testbench.

    What am I doing wrong?

    Erik Claij










    Attachments:







    top_tb.vhd ‏3 KB

    DB:2.59:Timing Simulation With A Simulated Ad Converter zz


    Hi,

    I try to simulate a Spartan-6 design with a simulated AD converter. In behavioral simulation there is no problem. In timing simulation the outputs of the modelAD7655 are undefined. The real design is working.

    Attached is the the top level testbench.

    What am I doing wrong?

    Erik Claij










    Attachments:







    top_tb.vhd ‏3 KB

  • RELEVANCY SCORE 2.58

    DB:2.58:Some Devices Are Not Found On 64bit Vista 1d


    Hi All,
     
    In order to sum up my problem without giving fellow readers headache,
    I'll simply state facts and scenarios quickly.
     
    Environment A contains:
    Vista 32 bit or XP sp3 32bit
    Blackmagic Decklink Card (BMD)
    Creative web Cam (USB)
     
    Environment B contains:
    Vista 64bit
    Blackmagic Decklink Card (BMD)
    Creative web Cam (USB)
     
    C1 = Code To enumerate VideoInput Devices written in C# using DirectShowLib
    C2 = Code To enumerate VideoInput Devices written in C# via exporting a TLB of DLL/interfaces
    C3 = Code To enumerate VideoInput Devices written in C++ (from BMD vendor w/source code)
     
    Running C1 in Environtment A = BMD WebCam devices found
    Running C2 in Environtment A = BMD WebCam devices found
    Running C3 in Environtment A = BMD WebCam devices found
     
    Running C1 in Environtment B = WebCam device found ONLY
    Running C2 in Environtment B = WebCam device found ONLY
    Running C3 in Environtment B = BMD WebCam devices found
     
    Although C1 relays on DirectShowLib, internally it is very similiar to C2
    C2's logic and functionality is 99% the same as C3 Only difference is C3 is natice C++.
     
    How can this be happening?
    Switching to 64bit breaks my working code, but leaves original C++ code working Just fine.and the break happens while quering specific hardware, and runs fine for usb web cam.
     
    Thanks a lot
     
    Fadi .K

    DB:2.58:Some Devices Are Not Found On 64bit Vista 1d

    Hi SitM,
     
    Actually, We have done our own since we have a commercial library.
    (this started off before they introduced the .tlb in the newer SDK).
     
    Please check out
    http://www.decklinksdk.net
    *We are a 3rd party commercial library and not affeliated with BlackMagic®.
     
    since i can't share with you the code, you are more than welcome to look at the product and evaluatewhether it is useful for you or not. In any case, maybe we can help out if you post the .tlb error log...etc
     

  • RELEVANCY SCORE 2.58

    DB:2.58:How To Use Fuzzy Logic Controller For Transfer Function In Labview Control And Simulation Loop? ak



    I am facing problem with fuzzy PD logic controller for transfer function in control and simulation loop.

    Plz Help me in this regard...................

    i have attache snapshot of my program










    Attachments:







    fuzzy in simulation loop.JPG ‏52 KB

    DB:2.58:How To Use Fuzzy Logic Controller For Transfer Function In Labview Control And Simulation Loop? ak

    Hi Sankhadip,

    Sorry for the late response. I was looking at your code and
    I noticed that the graph scale does not start from zero. That might be the
    reason why you don't see the transient in the simulation. To change the scales
    simply double click on the lower limit and set it to zero. If this is not the
    expected results, can you please post the expected results, so we can see what are the
    differences between the results . Also, you might be using different
    solvers, and that gives different results as well.

    Thanks and have a great day.

    Esmail Hamdan | Applications Engineering | National
    Instruments

  • RELEVANCY SCORE 2.58

    DB:2.58:Error Happens In Data Sequence When I Doing Pcie Memory Write z8



    I am using Virtex5 XC5VSX50T as pcie 8x solution on my board and windriver 10.20 on the PC as the driver. I am using the BMD design according to XAPP1052. It works well when I do memory read DMA, which I means PC read data from FPGA. But when I do the memory write DMA (PC writting data to FPGA), things become bad and strange.

    Here is some details of the problem.

    I write a sequence of consecutivlyincreasing data to FPGA, which is 1,2,3,4,5,6... But when I use chipscope to watch receiving data of the FPGA. I see the data is notconsecutive any more. It is partly consecutive. I think the picture canshowthe error morevividly.

    I did a data plot in the chipscope for the received data during the PCIE DMA. In this picture, there are four parts of data that is not consecutive, just as I labled in th pic. Also interesting, if I change part 1 with part 2, and part 3 with part 4, the whole data is consecutive and right. So I believe that the error happened in the data sequence during the pcie transaction not the data itself. Such error does't happen in every DMA, just randomly.

    I have no idea about the error, cause I am using the BMD design and I think it is a verified solution. Could anyone help me with it?

    DB:2.58:Error Happens In Data Sequence When I Doing Pcie Memory Write z8


    I am using Virtex5 XC5VSX50T as pcie 8x solution on my board and windriver 10.20 on the PC as the driver. I am using the BMD design according to XAPP1052. It works well when I do memory read DMA, which I means PC read data from FPGA. But when I do the memory write DMA (PC writting data to FPGA), things become bad and strange.

    Here is some details of the problem.

    I write a sequence of consecutivlyincreasing data to FPGA, which is 1,2,3,4,5,6... But when I use chipscope to watch receiving data of the FPGA. I see the data is notconsecutive any more. It is partly consecutive. I think the picture canshowthe error morevividly.

    I did a data plot in the chipscope for the received data during the PCIE DMA. In this picture, there are four parts of data that is not consecutive, just as I labled in th pic. Also interesting, if I change part 1 with part 2, and part 3 with part 4, the whole data is consecutive and right. So I believe that the error happened in the data sequence during the pcie transaction not the data itself. Such error does't happen in every DMA, just randomly.

    I have no idea about the error, cause I am using the BMD design and I think it is a verified solution. Could anyone help me with it?

  • RELEVANCY SCORE 2.58

    DB:2.58:Re: Divergence Problem With A Pipe sz



    Hello i have a little problem with my simulation.

    I have a pipe with a diameter of 2 inches; seven nozzle on the side and the end of the pipe is closed.The boundary conditions are: Inlet massflow with 1925g/s; the seven outlet 0bar pressure.And i use the turbulence model k_epsilon and i tried all advection from 1 to 5.Well i thinking the combination of ADV5 and this turbulence modell is the best variation.But in every simulation the plot begins to swing and the simulation ends on the basis of divergenz.Behind the nozzle are areas (looks like a tube; only air) to measure the massflow on the seven outlet and check the balance sheet.

    Please take a look on the following images.

    Maybe you can help me to find a solution with this problem!










    Attachments:






    boundary_condition_image_one.jpg ‏19 KB

    DB:2.58:Re: Divergence Problem With A Pipe sz

    I see that you have set it up as compressible flow, in which case you should apply the "unknown" BC at all outlets and zero gauge pressure at the inlet. Have you tried running the problem incompressible?

  • RELEVANCY SCORE 2.58

    DB:2.58:Awg Scope In Simulation Mode f1


    I have installed FGEN 2.0 (for PXI 5421) and SCOPE 2.5 (for PXI 5122). I want to experiment with the simulation mode available with the FGEN SFP SCOPE SFP.How can I acquire the Arbitrary waveform being generated from FGEN SFP in simulation mode, in SCOPE SFP (in simulation mode) ?Thanx for the help.

    DB:2.58:Awg Scope In Simulation Mode f1

    When using the FGEN SFP and the SCOPE SFP in simulation mode, there is not a way to connect the simulated signals to other programs. So there is no way to read the simulated data that you generate with FGEN SFP into the SCOPE SFP. If you do have a PXI 5421 and a PXI 5122 you can connect the output of the 5421 to the input of the 5122 and read the data you are generating, but not in simulation mode.Hope this helps clarifyRegards,Doug K.Application EngineeringNational Instruments

  • RELEVANCY SCORE 2.58

    DB:2.58:Re: Installation Problem - Help Me s3



    i have istalled with stand alone licence

    I installed Network licence manager







    Solved!
    Go to Solution.

    DB:2.58:Re: Installation Problem - Help Me s3


    i couldnt resolve the issue.please help me. i have attached the image of the problem










    Attachments:







    Capture.GIF ‏130 KB

  • RELEVANCY SCORE 2.58

    DB:2.58:Problem Of Pcie Bmd Design Using Chipscope??? c1


    Hiall,

    IbuiltthePCIEBMDprojectaccordingtotheXAPP1052.

    Now,therewasaproblemofcapturingTLPsusingchipscope.

    IusedPCIecorev1.7,Gen1x4,thecoreinterfacefrequencywas125MHz

    ML605environment.

    Chipscopesettingwas:

    TheGUIparametersweresetasbelow:

    RunCount=1,TLPSize=32DWORDS,TLPstoTransfer=16TLPs

    TLPPattern=0xFEEDBEEF

    NowstarttheMemortWrite:

    Thewaveofchipsocpeis:

    Butin my chartIcannotcaptureallthe16TLPs?WHY?

    Theidealwaveisasbelowchartwhichiscapturedfromthexapp1052

    Thankyouforhelp!!!







    Solved!
    Go to Solution.

    DB:2.58:Problem Of Pcie Bmd Design Using Chipscope??? c1


    I fix it, after setting the depth to 16384 I can clearly see all the TLPs

    Thanks...

  • RELEVANCY SCORE 2.57

    DB:2.57:Cs5.5.1 - Blackmagic 8.6.1 - Snowleopard 10.6.8 f9



    Does the subject combo work properly?

    We have a working edit bay with CS5.5 and prior BMD Multibridge Pro drivers.

    Would like to update Premiere to its current version but I see some notes of problems - eyedropper not working (Lion only?) and output to reference monitor via the BMD cards.

    Then BMD 8.6.1 driver just came out 2 days ago and shows that Premiere 5.5.1 is supported with it.

    DB:2.57:Cs5.5.1 - Blackmagic 8.6.1 - Snowleopard 10.6.8 f9


    Hands up.

    PPR 5.5.1 an BM Multibrige Pro 8.6.1 (and also 8.6) dont work properly.

    PPR 5.5.1 an BM Multibrige Pro 8.5 works fine.

    See other thread CS5.5.1 update + latest intensity pro (8.6) driver not working properly together.

    klfi

  • RELEVANCY SCORE 2.57

    DB:2.57:Xilinx Ise 10.1 {Simulation Pop Up And Disappear} 8c



    Hi Forum Users,

    I had encountered a problem with the behavioral simulation, when i click on simulate behavioral model, the thing run, but the simulation tab pop up and disappear, i had tried uninstalling and reinstalling for 6 times, but the problem still there. i have also deleted the files after uninstalling. is there any problem which lead to this bug. I am using Windows Vista Business Edition 32-Bit OS. Your help is greatly appreciated.

    Thanks Regards

    Henry (Singapore)

    DB:2.57:Xilinx Ise 10.1 {Simulation Pop Up And Disappear} 8c


    Nope it is hang there without the prompt....

    I guess maybe i am using a different OS....window 7. Everthing is fine, installing checking of syntax except this simulation. I will try exporting my files to school and test...

    Thanks for the help anyway

  • RELEVANCY SCORE 2.57

    DB:2.57:Problems About Compiling Smartmodel And Simulation With Modelsim mx



    According to the guide, I shoule firstly compile smartmodel library and then modify the 'modelsim.ini' for simulation PPC405. However, After I used 'compxlib' to compile smartmodel, I couldn't find '$LMC_HOME/lib/swiftpli_mti.so' which is needed for modelsim simulation. Could somebody help me to sovle this problem? Thanks.

    BTW, the directory under $LMC_HOME is like this:

    ---$LMC_HOME

    |

    -------- model.lst

    |_____ secureip

    |_____ simprims_ver

    |_____ unisims_ver







    Solved!
    Go to Solution.

    DB:2.57:Problems About Compiling Smartmodel And Simulation With Modelsim mx


    Hi,

    Unfortunately the answer is no. SecureIP is based on the IEEE Verilog encryption methodology and the earliest version of Modelsim that supported this was 6.3c.

    Technically you can use 6.3c, although you will need to use ISE 10.1, as in 11.1 due to some changes in the encryption algorithm we had to change supported simulation to 6.4b as compxlib wont let you compile.

    Thanks

    Duth

  • RELEVANCY SCORE 2.57

    DB:2.57:Resolve Reading Mysterious Timecode 9p



    Heres the workflow, Im cutting fast turn around short form tvcs and need to send them off to grade.

    Sometimes coming from TBs of rushes, I want to use the new Premiere Pro project manager in 2014.1 to transcode to cineform media with handles on each clip because there is invariably client editorial changes in online.

    I transfer to the colour grader via ftp 2GB of media managed clips in 20-30 minutes rather hard drives of rushes via courier etc. etc. etc.

    Everything works great except for one problem. The TC that BMD resolve reads on those media managed clips is wrong. There is consistent timecode between the media managed clips in premiere and the edl used by the grader to conform the edit, the same correct timecode is also read on those same clips in QT7 and FCP7 (just checking the TC those two other applications).

    But in resolve the timecode is offset by a random amount on each clip. First frame for clip one in the edl is asking for 10:13:59:18, the closest TC read by resolve in that clip is 10:17:11:08. Likewise for clip two is 02:22:03:22 and what is available is 02:24:41:08.

    Its a 25fps project and Ive checked at each step of the process that this is always the timebase.

    As Premiere, the edl, QT7, FCP7 are all reading the same TC, I believe the problem is with resolve but I cant work out what it is. Any help, ideas, suggestions would be great.

    Will cross post this issue across the BMD, creative cow Adobe forums.

    Cheers,

    Rob

    DB:2.57:Resolve Reading Mysterious Timecode 9p


    Since Resolve reads different timecode AND frame rate than Premiere, you have to conform the footage in Premiere Pro to match what Resolve reads.

    Load the clips into resolve, find out what the starting timecode and frame rate is. Then go back to Premiere and (right click) Modify the time code and conform the frame rate (unless the frame rates are the same).

    Then kick out an FCP XML. Load that into Resolve.

    I had to do this recently with cine files from phantom footage. Complete nightmare. TC was off on every clip and some clips had different frame rates.

  • RELEVANCY SCORE 2.57

    DB:2.57:Simulation Loop Inside Subvi Inside A Simulation Loop x9



    First of all, let me just say, I've got to hand in my work in 24 hours so please any help will be appreciated.

    I've got a simulation loop inside a subVI inside a simulation loop. If I give the inner loop enough time to run, i.e make its duration smaller than the time step of the outer simulation loop. Shouldn't everything run smoothly? Or is this just a no-no with labview?

    Thank you

    DB:2.57:Simulation Loop Inside Subvi Inside A Simulation Loop x9


    Hi VicMackie,

    This help file on the properties of the Simulation Loop is likely to help you out.

    I believe from you posts that you're wanting the loop to run every second.

    Therefore you want to check "Synchronize loop to timing source" and set your 1kHz clock or set a 1kHz reset so that it'll reset on every invocation of the loop. From your post, I understand that you've already done this.

    As the period is in milliseconds, for a period of a second you'd want to set your period to 1000 milliseconds, which is the default (1000).

    I'd recommend leaving the step size at the default for now and just modifying the Timing Parameters tab to confirm whether the loop will execute every second if you set the period to 1000.

    Best wishes,




    ToriStudent

  • RELEVANCY SCORE 2.57

    DB:2.57:Why Cant I Get Through To The Checkout On The General Register Office Site 37


    I'm trying to order bmd certificates from my laptop but it will not let me through to the 'checkout' page. I have no problem on my home computer so I think it's something to do with the laptop settings.

  • RELEVANCY SCORE 2.57

    DB:2.57:Pcie Bmd Reference Design za



    hi

    im using SP605 board and running PCIe with polling and i was looking to shift my project to BMD, i cant find anyreference design or example related to that.







    Solved!
    Go to Solution.

    DB:2.57:Pcie Bmd Reference Design za

    Check the below Xapp. This supports SP605.

    http://www.xilinx.com/support/documentation/application_notes/xapp1052.pdf




    --------------------------------------------------​--------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful.--------------------------------------------------​-------------------------------------------

  • RELEVANCY SCORE 2.57

    DB:2.57:Problem With Gtx Post-Route Simulation ? xa



    Hello,I am doing the simulation of V5 GTX, main parameter:target line rate = 4Gbps,Reference Clock=125MHz,single lane,GTX_DUAL location X0Y5. The behavioral simulation works well and the rx datas(output) are right. But if i try to do post-route simulation,the phenomenon of rx data errors begin to arise . Any idea of what might be wrong?. Please guide me.

  • RELEVANCY SCORE 2.57

    DB:2.57:Is S3ansk Support Hardware Co-Simulation Through Usb? 31


    Can anybody help me whether S3ANSK supports hardware co-simulation through USB and if not how can I use the Kit with hardware co-simulation.

    DB:2.57:Is S3ansk Support Hardware Co-Simulation Through Usb? 31

    Can anybody help me whether S3ANSK supports hardware co-simulation through USB and if not how can I use the Kit with hardware co-simulation.

  • RELEVANCY SCORE 2.57

    DB:2.57:Simulation Freeze Or Stop Or I Don't Know To Describe The Problem cd



    hi

    during making asimulation i note this problem

    i wait it for 10 minute and anything not happen

    when i remove some part of my code the simulation work

    any help!!!!




    ---------------------------------------------------------------------------------------------I am tired of the traditions of peoples --All I want is to live freely with the girl which I love --But this is impossible because the traditions of the people stronger than me.----------------------------------------------------------------------------------------------

    DB:2.57:Simulation Freeze Or Stop Or I Don't Know To Describe The Problem cd

    thank to all how suggest the solution ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,the problem was solved.the error was in the one the process which dose not has any sensitivity list . the synthesis must tell me but he don't say anything about this process; best regards:::m.s



    ---------------------------------------------------------------------------------------------I am tired of the traditions of peoples --All I want is to live freely with the girl which I love --But this is impossible because the traditions of the people stronger than me.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.57

    DB:2.57:Problem About The Driver Of Bmd Example (Xapp1052) fx



    Iset up the BMD demo and install the demo driver on windows xp. The demo application works well, and the performance is obtained.

    But when the windows is restarted, the computer fails to enter the windows, and the monitor is shut down.

    After restarting the computer, and choosing "last good configuration",I enter the windows again.

    Is there some problems with the example driver?

    Thanks in advance!

    Yu
    Message Edited by zuoyu on 07-27-2009 12:59 AM

    DB:2.57:Problem About The Driver Of Bmd Example (Xapp1052) fx

    I saw a similar problem and it was related to a conflict with the NVidia video drivers. I never resolved it but since we were moving on to a different driver anyway I never pursued it. You could try disabling the NVidia drivers and using the built-in default video drivers in Windows. Your display quality and performance may suffer but at least it will boot.

  • RELEVANCY SCORE 2.56

    DB:2.56:Flexible Cantilever Beam Simulation Control 1s



    Hi NI,

    I have a problem about make vi control design and simulation. I have a flexible cantilever plant bonded PZT actuator to suppres vibration beam. I make a simulation control but output my simulation not suitable with my excpected. please help me to solve my problem.

    1. I have transfer function from modeling my plant is 0.01/( s2 + 0.1 s + 0.5 ). input plant is voltage and output plant is deflextion and I want graph input and output plant sinusoidal like picture attached.

    2. how to auto tuning parameter PID??

    3. please correct my vi control design and simulation(my design vi attached).

    I hope reply and help me as soon as possible.

    best regards,

    yani.ahmad










    Attachments:







    untitled.JPG ‏11 KB

    DB:2.56:Flexible Cantilever Beam Simulation Control 1s


    Hi somen,

    I can't really help you design the plant for your system. Did you try taking a look at the tutorials I linked above? They will help you implement your plant designs in LabVIEW.




    Stephen MeserveNational Instruments

  • RELEVANCY SCORE 2.56

    DB:2.56:Bmd Shuttle Issues zc



    My capture stop with blackmagic shuttle usb3.0 appear "save as..." and not continue capture video... any idea?... this problem appear with capture audio/video or only capture audio... with only video capture no problem... any idea? Please help me....

    [Please use a short description for the thread title, and ask the question only in the main body.]

    Message was edited by: Jim Simon

    DB:2.56:Bmd Shuttle Issues zc


    My capture stop with blackmagic shuttle usb3.0 appear "save as..." and not continue capture video... any idea?... this problem appear with capture audio/video or only capture audio... with only video capture no problem... any idea? Please help me....

    [Please use a short description for the thread title, and ask the question only in the main body.]

    Message was edited by: Jim Simon

  • RELEVANCY SCORE 2.56

    DB:2.56:Help ; Water Simulation With Pf Source a8


    hi,how to make thise water simulation with PF source ????????THANKS

    DB:2.56:Help ; Water Simulation With Pf Source a8

    If you want to simulate it, you'll need a fluids plugin like glu3d or real flow. If you're trying to just use pflow to make it look like water, I'd say look at Allan McKay's rain dripping tutorial for the pflow setup and maybe Pete Draper's rain drop ripples tutorial for when the drops hit the water below.



    3ds Max 2009 SP1, 2010 SP1Maya 2012Windows 7 Professional 64-bitDual Intel Xeon E5520, 6 GB RamNVIDIA GeForce GTX 460 OC