• RELEVANCY SCORE 3.99

    DB:3.99:Vivado Hls Systemc Hdl Co-Simulation (Without Synthesizing) mj





    Hi there,

    I know it is possible with Vivado HLS to synthesize SystemC code into HDL and simulate it. How about simulating a VHDL module which I have written earlier with a SystemC testbench? Again, HDL module is not synthesized from SystemC code. Is it possible to do that?

    Thanks.

    Mehmet







    Solved!
    Go to Solution.

    DB:3.99:Vivado Hls Systemc Hdl Co-Simulation (Without Synthesizing) mj


    Thank you debrajr. But isn't it nice if Vivado HLS can do that. Maybe Xilinx can consider this in next releases.

  • RELEVANCY SCORE 3.95

    DB:3.95:Black Box Modelsim Co-Simulation dc





    Hi

    I have imported my HDL code into a black box, and am trying to simulate it.

    The simulation works fine with ISE simulator, but with ModelSim it gives me the following error

    Internal error occurred while preparing the design for HDL co-simulation.Error occurred during "Simulation Configuration".Reported by: 'dibo_spi/ModelSim'

    Could someone please help me solve this...

    thanks,

    Prasanthi

    DB:3.95:Black Box Modelsim Co-Simulation dc


    Thanks a lot for your response.

    The simulation works fine though now... I am not sure what the mistake was... thought it was something related to the sample period...

  • RELEVANCY SCORE 3.67

    DB:3.67:Error While Hardware Cosimulation mz





    Hi

    I am trying to do hardware co simulation usign SYSTEM GENERATOR Tool of xilinx for a small application i.e matrix transpose my code is performing well while HDL co-simulation using black box concept of system generator but while doing actual co simulation by generating a co simulation block for SPARTAN 3E STARTER KIT i am getting errors while the Xflow creation its not creating the bit file can u plz let me know possible error and how can i handle iti am attaching my project files for your reference

    thanks and regardsteja




    Thanks and RegardsTeja

    DB:3.67:Error While Hardware Cosimulation mz


    Thaanks A lot Eilert

    That was really awesome debugging

    First i saved both mdl anf vhd files with same name it prompted that both cannot have samename in hurry i sud have changed the wrong one.

    Ya actually that is the only kit available in my lab so i created the user defined board support for that.

    Thanks and Regards

    Teja




    Thanks and RegardsTeja

  • RELEVANCY SCORE 3.61

    DB:3.61:Plz Help Hardware Co-Simulation p3



    hi..!

    i need your help, my target board is ML505 xc5vlx110t-1ff1136(i dont know if it is also called as ML509 or XUPV5-LX110T)

    in above figure iam able to generate HDL netlist for my target device virtex5 xc5vlx110t-1ff1136

    but i wanna do hardware co-simulation, so in system generator token i
    took option "Hardware co-simulation" as shown below, but my target
    board ML505 is not in the list, so i chose "New Compilation Target".

    and how to fill those options?
    in "System Generator Board Description Builder"

    i think for hardware co-simulation any board with jtag can be used...also installation of new board in "System Generator Board Description Builder" (for example ML505) is very easy if xilinx support provides .xml files for that particular board
    so that by clicking button "Load" in "System Generator Board Description Builder" we can input .xml file you give and install support for new board.because adding ports or pins that are about 1000, is a headache, so xilinx must have a solution....!!!!!

    if images above are not clear u can plz go here and zoom


    http://picasaweb.google.co.in/prem.gprec/Project

    DB:3.61:Plz Help Hardware Co-Simulation p3


    and how to fill those options in "System Generator Board Description Builder"?

    I'm probably stating the obvious here: if you hit the "Help" button, the help page for the xlSBDBuilder wil pop up (see below), which has descriptions on all the options. If you still have specific questions, feel free to ask. Regarding the "Non-memory mapped" ports, you don't need to enter them if you don't use them in your hwcosim. In most of cases, you will need very few if any of them for the hwcosim.

    Cheers,

    Jim




    Cheers,Jim

  • RELEVANCY SCORE 3.60

    DB:3.60:Error When Generating Simulation Hdl Files jp



    Hi:

    When I try to generate simulation files from EDK, I get the following errors:

    ERROR:MDT - Ucf2Vhdl Conversion Generated Errors.ERROR:MDT - Error creating memory initialization filesmake: *** [simulation/behavioral/system.do] Error 1Done!

    The attachment shows the full output from EDK.

    Pls can anyone help?

    Regards










    Attachments:







    edkerror.txt ‏86 KB

    DB:3.60:Error When Generating Simulation Hdl Files jp


    Hi,

    The reason for this was because of a "." in the EDK Install path. For example /proj/xbuilds/EDK_8.2/...

    Thanks.




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.36

    DB:3.36:Hardwere Co Simulation c1



    hello

    i m used ise 10.1 and matlab 2008a with system generator 10.1 i want use SPARTEN 3E starter kit for hardwere co simulation..what settings i have to do????

    when i was used 9.1 version with matlab 2006a we have to make a folder in

    C:\Program Files\MATLAB\R2006a\toolbox\xilinx\sysgen\plugins\compilation\Hardware Co-Simulation

    but in matlab 2008athere is no such types of directory..

    and what is the settings..

    plz tell me what is the boundry scan position of sparten 3e kit??

    pin location of clock is c9..and IR length is 6,8,8..

    DB:3.36:Hardwere Co Simulation c1


    hai sir, boundary scan postion is 1 for impact because in spartran there are 3 devices 1 for fpga,2 for prom and 3 for cpld

    thanks

    prasad

  • RELEVANCY SCORE 3.30

    DB:3.30:Isim Failure While Trying To Simulate Design Using Microblaze Mcs zs



    I am using vivado 2013.3 and have a design that uses microblaze mcs. I have created an elf file using the sdk and associated it with the microblaze core for simulation (under simulation sources). Now when I try to run simulation, I get the following errors:

    Starting static elaborationWARNING: [VRFC 10-727] function f_payload_width has no return value assignment [c:/HDL/quickdrive/quickdrive.srcs/sources_1/ip/pcie_rcv_demux/axis_interconnect_v1_1/hdl/verilog/axis_interconnect_v1_1_axis_infrastructure.vh:251]ERROR: [VRFC 10-451] cannot open file 'int_infile' [/proj/rdi/builds/2013.3/continuous/2013_09_27_320841/data/vhdl/src/unisims/primitive/RAMB36E1.vhd:1100]ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

    Sumit

    DB:3.30:Isim Failure While Trying To Simulate Design Using Microblaze Mcs zs

    Resolved - I found the "Associate ELF" function that I had missed earlier. It's odd that you have to add the ELF file twice - specifically as a design source and specifically as a simulation source to make this work. Marking a single copy of the ELF file as "Implementation" and and "Simulation" is not adequate - you must truly add the file twice.

  • RELEVANCY SCORE 3.29

    DB:3.29:Vivadohls Co-Simulation Error fa



    Hi everyone,

    I am new to Vivado HLS. When I want to perform a C/RTL co-simulation with SystemC I get the following error:

    ----------------------------------------------------------------------------------------------------

    In memory model top.AESL_inst_dstGrid.core_inst, during a write cycleERROR: Address 32570 for port '1' is outside the legal range [0..25999].Fatal: (F1000) unknown idIn file: AESL_automem_dstGrid.h:102In process: top.AESL_inst_dstGrid.core_inst.proc_mem @ 105 ns@E [SIM-304] Aborting co-simulation: C simulation failed.@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

    ----------------------------------------------------------------------------------------------------

    Had anyone encountered something similar? How could I fix this issue?

    I would appreciate any help.

    Thank you,

    Alex

    DB:3.29:Vivadohls Co-Simulation Error fa


    Hello,

    Please start a new thread explaining what you see and attach a testcase, to make it easier to reproduce.

    The thread you're replying is too old, and there are a few issues in the code (!).

    The OP was also using a year old tool version which may have other issues than the current version.

    Thanks.




    - HervéSIGNATURE:* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369* Please mark the Answer as "Accept as solution" if information provided is helpful.* Give Kudos to a post which you think is helpful and reply oriented.

  • RELEVANCY SCORE 3.28

    DB:3.28:Spartan 3an Starter Kit And Simulink Hardware Cosimulation f3



    Hi! I have one question about JTAG and Spartan 3AN starter kit: I
    managed to make a simple program from Simulink/System generator blocks,
    but I have problems with hardware co-simulation: my Simulink model
    consists of one input gateway(mapped to a switch0) and one output
    gateway(mapped to led 0) connected. I made files for this board in
    hardware co-simulation property tab in system generator block, and
    everything works on board, but when I want to see in Simulink (on Scope
    block) output from spartan (I connected scopes on every single net) in
    hardware co-simulation, it shows zero always. Is it possible to watch
    in real time voltages(or levels) on FPGA pins in Slimulink model ?

    Thank u for reply







    Solved!
    Go to Solution.

    DB:3.28:Spartan 3an Starter Kit And Simulink Hardware Cosimulation f3


    You may want to first take a look a couple get-started materials mentioned in this message: http://forums.xilinx.com/xlnx/board/message?board.​id=DSPTOOLthread.id=2080 to get familiar with SysGen

    FPGA is a digital component (i.e only 1's and 0's), so you will need ADC/DAC for your project. Take a look at the documents for the Spartan3AN starter kit to find out what ADC/DAC are on the board and read their datasheets to understand how they work and how to interface to them.

    Cheers,

    Jim




    Cheers,Jim

  • RELEVANCY SCORE 3.21

    DB:3.21:Matrixx Plugsim Capability (Co-Simulation) sk


    ISI, developer of MATRIXx, had a MATRIXx product called PlugSim which allowed co-simulation with other simulation engines like ADAMS, EASY5 using CORBA through TCP/IP. This product was dropped during the transfer to The Mathworks. Is National Instruments planning on addressing the co-simulation and distributed simulation interests that drove this product developement? Would not the market for this product increase as time progresses and users require simulation of mechanical, electrical and other control systems? Could this be addressed through 3rd party or NI Alliance products?

    DB:3.21:Matrixx Plugsim Capability (Co-Simulation) sk

    As part of the MATRIXx acquisition, NI acquired an OEM license to PlugSim from Wind River. We are evaluating if it makes sense for this and other co-simulation technology to fit into the long-term NI product development strategy.Ash RazdanNational Instrumentsash.razdan@ni.com

  • RELEVANCY SCORE 3.19

    DB:3.19:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... as


    hi,I wanted to simulate an ipcore with xps.I compiled the simulation libraries,then I generated simulation HDL files.but when I select the launch HDL simulatorI enconter the following:make: nothing to be done for "simmodel'best regards

    DB:3.19:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... as


    XPS is makefile based. That means that it should only run a compiler, or generate netlists if something has changed since the last time you ran a command.

    It looks like you have previously run the simulation generator (simgen) to generate the simulation models for your system.

    Launch HDL simulator should launch your simulation tool (ie Modelsim, Ncsim).

    It would be worth checking that the executable for your simulator is in your path. Check /doc/usenglish/help/platform_studio/html/ps_p_sim_​setting_up_modelsim_for_using_smartmodels.htm or /doc/usenglish/help/platform_studio/html/ps_p_sim_​setting_up_ncsim_for_using_smartmodels.htm to see if that helps.




    Kris ChaplinXilinx UK

  • RELEVANCY SCORE 3.11

    DB:3.11:Can I Use System Generator To Simulate Verilog Module With Another Verilog Called In It? fc



    Hi,

    I am using ISE11.4 with system generator. I want to simulate a verilog module in which I am calling another module. Its showing error:-

    "HDL simulation model compilation failed.

    ERROR:HDLCompiler:559 -
    "xlisim_trye.v" Line 1001: Could not find module/primitive
    AddSub.

    ERROR:Simulator:778 - Static
    elaboration of top level Verilog design unit(s) in library work failed

    Error occurred during
    "Simulation Initialization".

    "

    Does system generator support this type of simulation?

    Thankx

    -Kalyani







    Solved!
    Go to Solution.

    DB:3.11:Can I Use System Generator To Simulate Verilog Module With Another Verilog Called In It? fc

    Use the black box feature. You'll have to list all the dependencies (in the configuration file). Check the System Generator user guide for more info on black boxes.

  • RELEVANCY SCORE 3.11

    DB:3.11:Problems With Simulation Isim Fatal_Error zz









    Solved!
    Go to Solution.

    DB:3.11:Problems With Simulation Isim Fatal_Error zz


    Well few hours later,

    I suspect reading the http://www.xilinx.com/support/answers/32357.htmonly solution 6 call me atention, then i revised my programs, i looked

    C:\Mingw\ ----this for a program called Code Blocks

    C:\Program Files\EGCS ---don't remember

    Yes, those directories are the Minimalist GNU for Windows

    Then i uninstall Code Blocks, and delete those 2 directories.

    Well, reboot mi PC

    Try again and console output:

    Started : "Simulate Behavioral Model".Starting fuse...fuse -intstyle ise -incremental -o C:/Project/ISim_Tutorial/drp_demo_tb_isim_beh.exe -prj C:/Project/ISim_Tutorial/drp_demo_tb_beh.prj drp_demo_tbRunning: C:\Xilinx\11.1\ISE\bin\nt\unwrapped\fuse.exe -ise C:/Project/ISim_Tutorial/ISim_Tutorial.ise -intstyle ise -incremental -o C:/Project/ISim_Tutorial/drp_demo_tb_isim_beh.exe -prj C:/Project/ISim_Tutorial/drp_demo_tb_beh.prj drp_demo_tb -mt off -v 1 Turned off multi-threading for compilationDetermining compilation order of HDL filesThe vhdl library search path for library \"std\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/std\"The veri library search path for library \"std\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/std\"The vhdl library search path for library \"ieee\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/ieee\"The veri library search path for library \"ieee\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/ieee\"The vhdl library search path for library \"ieee_proposed\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/ieee_proposed\"The veri library search path for library \"ieee_proposed\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/ieee_proposed\"The vhdl library search path for library \"vl\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/vl\"The veri library search path for library \"vl\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/vl\"The vhdl library search path for library \"synopsys\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/synopsys\"The veri library search path for library \"synopsys\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/synopsys\"The vhdl library search path for library \"simprim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/simprim\"The veri library search path for library \"simprim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/simprim\"The vhdl library search path for library \"unisim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/unisim\"The veri library search path for library \"unisim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/unisim\"The vhdl library search path for library \"unimacro\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/unimacro\"The veri library search path for library \"unimacro\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/unimacro\"The vhdl library search path for library \"aim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/aim\"The veri library search path for library \"aim\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/aim\"The vhdl library search path for library \"cpld\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/cpld\"The veri library search path for library \"cpld\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/cpld\"The vhdl library search path for library \"pls\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/pls\"The veri library search path for library \"pls\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/pls\"The vhdl library search path for library \"xilinxcorelib\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/xilinxcorelib\"The veri library search path for library \"xilinxcorelib\" is now \"c:/xilinx/11.1/ise/vhdl/hdp/nt/xilinxcorelib\"The vhdl library search path for library \"aim_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/aim_ver\"The veri library search path for library \"aim_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/aim_ver\"The vhdl library search path for library \"cpld_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/cpld_ver\"The veri library search path for library \"cpld_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/cpld_ver\"The vhdl library search path for library \"simprims_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/simprims_ver\"The veri library search path for library \"simprims_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/simprims_ver\"The vhdl library search path for library \"unisims_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/unisims_ver\"The veri library search path for library \"unisims_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/unisims_ver\"The vhdl library search path for library \"uni9000_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/uni9000_ver\"The veri library search path for library \"uni9000_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/uni9000_ver\"The vhdl library search path for library \"unimacro_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/unimacro_ver\"The veri library search path for library \"unimacro_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/unimacro_ver\"The vhdl library search path for library \"xilinxcorelib_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xilinxcorelib_​ver\"The veri library search path for library \"xilinxcorelib_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xilinxcorelib_​ver\"The vhdl library search path for library \"secureip\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/secureip\"The veri library search path for library \"secureip\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/secureip\"The vhdl library search path for library \"gt_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt_ver\"The veri library search path for library \"gt_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt_ver\"The vhdl library search path for library \"gt10_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt10_ver\"The veri library search path for library \"gt10_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt10_ver\"The vhdl library search path for library \"gt11_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt11_ver\"The veri library search path for library \"gt11_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gt11_ver\"The vhdl library search path for library \"gtp_dual_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtp_dual_v​er\"The veri library search path for library \"gtp_dual_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtp_dual_v​er\"The vhdl library search path for library \"gtp_dual_fast_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtp_dual_f​ast_ver\"The veri library search path for library \"gtp_dual_fast_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtp_dual_f​ast_ver\"The vhdl library search path for library \"gtx_dual_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtx_dual_v​er\"The veri library search path for library \"gtx_dual_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtx_dual_v​er\"The vhdl library search path for library \"gtx_dual_fast_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtx_dual_f​ast_ver\"The veri library search path for library \"gtx_dual_fast_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/gtx_dual_f​ast_ver\"The vhdl library search path for library \"emac_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/emac_ver\"The veri library search path for library \"emac_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/emac_ver\"The vhdl library search path for library \"temac_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/temac_ver\​"The veri library search path for library \"temac_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/temac_ver\​"The vhdl library search path for library \"ppc405_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc405_ver​\"The veri library search path for library \"ppc405_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc405_ver​\"The vhdl library search path for library \"ppc405_adv_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc405_adv​_ver\"The veri library search path for library \"ppc405_adv_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc405_adv​_ver\"The vhdl library search path for library \"ppc440_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc440_ver​\"The veri library search path for library \"ppc440_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/ppc440_ver​\"The vhdl library search path for library \"pcie_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/pcie_ver\"The veri library search path for library \"pcie_ver\" is now \"c:/xilinx/11.1/ise/verilog/hdp/nt/xip/pcie_ver\"The vhdl library search path for library \"work\" is now \"c:/project/isim_tutorial/isim/work\"The veri library search path for library \"work\" is now \"c:/project/isim_tutorial/isim/work\"The vhdl library search path for library \"drp_tb_lib\" is now \"c:/project/isim_tutorial/isim/drp_tb_lib\"The veri library search path for library \"drp_tb_lib\" is now \"c:/project/isim_tutorial/isim/drp_tb_lib\"

    -- Dumping Relevant ParametersXILINX = C:\Xilinx\11.1\ISEPATH = C:\Xilinx\11.1\ISE\lib\nt;C:\Xilinx\11.1\ISE\bin\n​t;C:\WINDOWS\system32\WindowsPowerShell\v1.0;C:\WI​NDOWS\system32\wbem;C:\WINDOWS\system32;C:\Xilinx\​11.1\PlanAhead\bin;C:\Xilinx\11.1\common\bin\nt;c:​\progra~1\pscad4~1\bin\ffilter;c:\program files\smart projects\isobuster;%gcc_exec_prefix%\libexec\gcc\m​ingw32\3.4.5;%gcc_exec_prefix%\lib\bin;C:\Program Files\QuickTime\QTSystem\;C:\Program Files\TortoiseSVN\bin;C:\WINDOWS;C:\MCC18\mpasm;C:​\MCC18\binCWD = C:/Project/ISim_TutorialGCC = C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe-- Done dumping Relevant Parameters

    -- Dumping System Informationrelease = 5.1 Service Pack 3machine = x86-- Done dumping System Information

    -- Dumping Loaded ModulesC:\WINDOWS\System32\NETAPI32.dllC:\WINDOWS\System32\NETRAP.dllC:\WINDOWS\System32\NETUI0.dllC:\WINDOWS\System32\NETUI1.dllC:\WINDOWS\System32\SAMLIB.dllC:\WINDOWS\System32\davclnt.dllC:\WINDOWS\System32\drprov.dllC:\WINDOWS\System32\ntlanman.dllC:\WINDOWS\WinSxS\x86_Microsoft.VC80.CRT_1fc8b3b9a​1e18e3b_8.0.50727.3053_x-ww_b80fa8ca\MSVCP80.dllC:\WINDOWS\WinSxS\x86_Microsoft.VC80.CRT_1fc8b3b9a​1e18e3b_8.0.50727.3053_x-ww_b80fa8ca\MSVCR80.dllC:\WINDOWS\system32\ADVAPI32.dllC:\WINDOWS\system32\GDI32.dllC:\WINDOWS\system32\IMM32.DLLC:\WINDOWS\system32\MPR.dllC:\WINDOWS\system32\PSAPI.DLLC:\WINDOWS\system32\RPCRT4.dllC:\WINDOWS\system32\Secur32.dllC:\WINDOWS\system32\USER32.dllC:\WINDOWS\system32\VERSION.dllC:\WINDOWS\system32\WS2HELP.dllC:\WINDOWS\system32\WS2_32.dllC:\WINDOWS\system32\WSOCK32.dllC:\WINDOWS\system32\dbghelp.dllC:\WINDOWS\system32\kernel32.dllC:\WINDOWS\system32\msvcrt.dllC:\WINDOWS\system32\ntdll.dllC:\WINDOWS\system32\ole32.dllC:\Xilinx\11.1\ISE\bin\nt\unwrapped\fuse.exeC:\Xilinx\11.1\ISE\lib\nt\SHSMP.DLLC:\Xilinx\11.1\ISE\lib\nt\boost_filesystem-vc71-mt​-p-1_33_1.dllC:\Xilinx\11.1\ISE\lib\nt\boost_iostreams-vc71-mt-​p-1_33_1.dllC:\Xilinx\11.1\ISE\lib\nt\boost_program_options-vc​71-mt-p-1_33_1.dllC:\Xilinx\11.1\ISE\lib\nt\boost_regex-vc71-mt-p-1_​33_1.dllC:\Xilinx\11.1\ISE\lib\nt\boost_thread-vc71-mt-p-1​_33_1.dllC:\Xilinx\11.1\ISE\lib\nt\libICR.dllC:\Xilinx\11.1\ISE\lib\nt\libMiniZip.dllC:\Xilinx\11.1\ISE\lib\nt\libPersonalityModule.dllC:\Xilinx\11.1\ISE\lib\nt\libPort_Std.dllC:\Xilinx\11.1\ISE\lib\nt\libPortability.dllC:\Xilinx\11.1\ISE\lib\nt\libPrjrep_Archive.dllC:\Xilinx\11.1\ISE\lib\nt\libPrjrep_Clientac.dllC:\Xilinx\11.1\ISE\lib\nt\libPrjrep_Repository.dllC:\Xilinx\11.1\ISE\lib\nt\libStaticFileParsers.dllC:\Xilinx\11.1\ISE\lib\nt\libThread.dllC:\Xilinx\11.1\ISE\lib\nt\libUtilC_MessageDispatch​er.dllC:\Xilinx\11.1\ISE\lib\nt\libUtilities.dllC:\Xilinx\11.1\ISE\lib\nt\libVrfc_Verific.dllC:\Xilinx\11.1\ISE\lib\nt\libVrfc_Vhdl_Sort.dllC:\Xilinx\11.1\ISE\lib\nt\libZlib.dllC:\Xilinx\11.1\ISE\lib\nt\libisl_iostreams.dllC:\Xilinx\11.1\ISE\lib\nt\libpthread.dllC:\Xilinx\11.1\ISE\lib\nt\libxercesc.dllC:\Xilinx\11.1\ISE\lib\nt\stlport.5.1.dll-- Done dumping Loaded Modules

    -- Dumping library mappingaim=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/aimaim_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/aim_vercpld=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/cpldcpld_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/cpld_ve​rdrp_tb_lib=isim/drp_tb_libemac_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/ema​c_vergt10_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/gt1​0_vergt11_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/gt1​1_vergt_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/gt_ve​rgtp_dual_fast_ver=C:/Xilinx/11.1/ISE/verilog/hdp/n​t/xip/gtp_dual_fast_vergtp_dual_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip​/gtp_dual_vergtx_dual_fast_ver=C:/Xilinx/11.1/ISE/verilog/hdp/n​t/xip/gtx_dual_fast_vergtx_dual_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip​/gtx_dual_verieee=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/ieeeieee_proposed=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/ieee_​proposedpcie_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/pci​e_verpls=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/plsppc405_adv_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/x​ip/ppc405_adv_verppc405_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/p​pc405_verppc440_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/p​pc440_versecureip=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/sec​ureipsimprim=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/simprimsimprims_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/sim​prims_verstd=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/stdsynopsys=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/synopsystemac_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/xip/te​mac_veruni9000_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/uni9​000_verunimacro=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/unimacrounimacro_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/uni​macro_verunisim=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/unisimunisims_ver=C:/Xilinx/11.1/ISE/verilog/hdp/nt/unis​ims_vervl=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/vlwork=isim/workxilinxcorelib=C:/Xilinx/11.1/ISE/vhdl/hdp/nt/xilin​xcorelibxilinxcorelib_ver=C:/Xilinx/11.1/ISE/verilog/hdp/n​t/xilinxcorelib_ver-- Done dumping library mapping

    Parsing VHDL file "C:/Project/ISim_Tutorial/drp_stmach.vhd" into library workParsing entity drp_stmach.Parsing architecture Behavioral of entity drp_stmach.Parsing VHDL file "C:/Project/ISim_Tutorial/drp_dcm.vhd" into library workParsing entity drp_dcm.Parsing architecture BEHAVIORAL of entity drp_dcm.Parsing VHDL file "C:/Project/ISim_Tutorial/drp_tb_pkg.vhd" into library drp_tb_libParsing package drp_tb_pkg.Parsing package body drp_tb_pkg.Parsing VHDL file "C:/Project/ISim_Tutorial/drp_demo.vhd" into library workParsing entity drp_demo.Parsing architecture Behavioral of entity drp_demo.Parsing VHDL file "C:/Project/ISim_Tutorial/drp_demo_tb.vhd" into library workParsing entity drp_demo_tb.Parsing architecture behavioral of entity drp_demo_tb.Starting static elaborationExecuting drp_demo_tb(behavioral)Executing drp_demo_default(Behavioral)WARNING:HDLCompiler:746 - "N:/L.57/rtf/vhdl/src/ieee/numeric_std.vhd" Line 878: Range is empty (null range)WARNING:HDLCompiler:746 - "N:/L.57/rtf/vhdl/src/ieee/numeric_std.vhd" Line 879: Range is empty (null range)Executing drp_dcm_default(BEHAVIORAL)Executing BUFG_default(BUFG_V)Executing \DCM_ADV(true," ",true,false,2.0,2,2,false,10.0,"NONE","1X",true,"​MAX_SPEED","SYSTEM_SYNCHRONOUS","LOW","LOW",true,"​1111000011110000",0,"VIRTEX5",false)\(DCM_ADV_V)WARNING:HDLCompiler:321 - "N:/L.57/rtf/vhdl/src/unisims/primitive/DCM_ADV.vh​d" Line 831: Comparison between arrays of unequal length always returns FALSE.WARNING:HDLCompiler:321 - "N:/L.57/rtf/vhdl/src/unisims/primitive/DCM_ADV.vh​d" Line 960: Comparison between arrays of unequal length always returns TRUE.WARNING:HDLCompiler:321 - "N:/L.57/rtf/vhdl/src/unisims/primitive/DCM_ADV.vh​d" Line 975: Comparison between arrays of unequal length always returns TRUE.Executing dcm_adv_clock_divide_by_2_default(dcm_adv_clock_di​vide_by_2_V)Executing \dcm_adv_maximum_period_check(" ","CLKIN",1000000)\(dcm_adv_maximum_period_check_V​)Executing \dcm_adv_maximum_period_check(" ","PSCLK",100000000)\(dcm_adv_maximum_period_check​_V)Executing dcm_adv_clock_lost_default(dcm_adv_clock_lost_V)WARNING:HDLCompiler:321 - "N:/L.57/rtf/vhdl/src/unisims/primitive/DCM_ADV.vh​d" Line 1990: Comparison between arrays of unequal length always returns FALSE.WARNING:HDLCompiler:321 - "N:/L.57/rtf/vhdl/src/unisims/primitive/DCM_ADV.vh​d" Line 1997: Comparison between arrays of unequal length always returns FALSE.Executing drp_stmach_default(Behavioral)Completed static elaborationFuse Memory Usage: 67628 KBFuse CPU Usage: 687 msUsing precompiled package standard from library stdUsing precompiled package std_logic_1164 from library ieeeICR Memory Use: 4294967295 bytesUsing precompiled package std_logic_arith from library ieeeICR Memory Use: 4294967295 bytesUsing precompiled package std_logic_unsigned from library ieeeICR Memory Use: 4294967295 bytesUsing precompiled package textio from library stdICR Memory Use: 4294967295 bytesUsing precompiled package numeric_std from library ieeeICR Memory Use: 4294967295 bytesUsing precompiled package vital_timing from library ieeeICR Memory Use: 4294967295 bytesUsing precompiled package vital_primitives from library ieeeICR Memory Use: 4294967295 bytesCompiling package drp_tb_pkg - p_2310507927ICR Memory Use: 18523 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/drp_tb_lib/p_231​0507927.c to isim/drp_demo_tb_isim_beh.exe.sim/drp_tb_lib/p_231​0507927.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/drp_tb_lib/p_23​10507927.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/drp_tb_lib/p_23​10507927.c"Compiling package vcomponents - p_0947159679ICR Memory Use: 4294967295 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_0947159​679.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_0947159​679.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_094715​9679.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_094715​9679.c"Compiling package vpkg - p_3222816464ICR Memory Use: 596742 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_3222816​464.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_3222816​464.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_322281​6464.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_322281​6464.c"Compiling architecture bufg_v of entity bufg [bufg_default] - a_1490675510_1976025627ICR Memory Use: 2574 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_1490675​510_1976025627.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_1490675​510_1976025627.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_149067​5510_1976025627.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_149067​5510_1976025627.c"Compiling architecture dcm_adv_clock_divide_by_2_v of entity dcm_adv_clock_divide_by_2 [dcm_adv_clock_divide_by_2_defaul...] - a_4167558488_0695499473ICR Memory Use: 26451 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_4167558​488_0695499473.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_4167558​488_0695499473.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_416755​8488_0695499473.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_416755​8488_0695499473.c"Compiling architecture dcm_adv_maximum_period_check_v of entity dcm_adv_maximum_period_check [\dcm_adv_maximum_period_check(" ...] - a_0905426929_3703648270ICR Memory Use: 20500 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0905426​929_3703648270.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0905426​929_3703648270.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_090542​6929_3703648270.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_090542​6929_3703648270.c"Compiling architecture dcm_adv_maximum_period_check_v of entity dcm_adv_maximum_period_check [\dcm_adv_maximum_period_check(" ...] - a_0512141565_3703648270ICR Memory Use: 20500 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0512141​565_3703648270.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0512141​565_3703648270.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_051214​1565_3703648270.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_051214​1565_3703648270.c"Compiling architecture dcm_adv_clock_lost_v of entity dcm_adv_clock_lost [dcm_adv_clock_lost_default] - a_0435408399_0783196562ICR Memory Use: 86166 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0435408​399_0783196562.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_0435408​399_0783196562.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_043540​8399_0783196562.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_043540​8399_0783196562.c"Compiling architecture dcm_adv_v of entity dcm_adv [\DCM_ADV(true," ",true,false,2.0...] - a_3183481032_0551479669ICR Memory Use: 55708 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_3183481​032_0551479669.c to isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_3183481​032_0551479669.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_318348​1032_0551479669.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_318348​1032_0551479669.c"Compiling architecture behavioral of entity drp_dcm [drp_dcm_default] - a_3860148221_3212880686ICR Memory Use: 4500 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/work/a_386014822​1_3212880686.c to isim/drp_demo_tb_isim_beh.exe.sim/work/a_386014822​1_3212880686.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38601482​21_3212880686.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38601482​21_3212880686.c"Compiling architecture behavioral of entity drp_stmach [drp_stmach_default] - a_2521883737_3212880686ICR Memory Use: 71921 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/work/a_252188373​7_3212880686.c to isim/drp_demo_tb_isim_beh.exe.sim/work/a_252188373​7_3212880686.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/work/a_25218837​37_3212880686.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_25218837​37_3212880686.c"Compiling architecture behavioral of entity drp_demo [drp_demo_default] - a_1043879889_3212880686ICR Memory Use: 20373 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/work/a_104387988​9_3212880686.c to isim/drp_demo_tb_isim_beh.exe.sim/work/a_104387988​9_3212880686.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/work/a_10438798​89_3212880686.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_10438798​89_3212880686.c"Compiling architecture behavioral of entity drp_demo_tb - a_3877462617_3212880686ICR Memory Use: 132152 bytesCompiling isim/drp_demo_tb_isim_beh.exe.sim/work/a_387746261​7_3212880686.c to isim/drp_demo_tb_isim_beh.exe.sim/work/a_387746261​7_3212880686.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38774626​17_3212880686.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38774626​17_3212880686.c"Time Resolution for simulation is 1ps.Compiling isim/drp_demo_tb_isim_beh.exe.sim/work/drp_demo_tb​_isim_beh.exe_main.c to isim/drp_demo_tb_isim_beh.exe.sim/work/drp_demo_tb​_isim_beh.exe_main.nt.obj with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -c -o "isim/drp_demo_tb_isim_beh.exe.sim/work/drp_demo_t​b_isim_beh.exe_main.nt.obj" -I"C:/Xilinx/11.1/ISE/data/include" "isim/drp_demo_tb_isim_beh.exe.sim/work/drp_demo_t​b_isim_beh.exe_main.c"Linking with command:C:/Xilinx/11.1/ISE/gnu/MinGW/5.0.0/nt/bin/gcc.exe -Wa,-W -O -Wl,--large-address-aware,--stack,104857600 -o "isim/drp_demo_tb_isim_beh.exe.sim/drp_demo_tb_isi​m_beh.exe" "isim/drp_demo_tb_isim_beh.exe.sim/work/drp_demo_t​b_isim_beh.exe_main.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/drp_tb_lib/p_23​10507927.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_094715​9679.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/p_322281​6464.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_149067​5510_1976025627.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_416755​8488_0695499473.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_090542​6929_3703648270.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_051214​1565_3703648270.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_043540​8399_0783196562.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/unisim/a_318348​1032_0551479669.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38601482​21_3212880686.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_2521883737_3212880686.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_10438798​89_3212880686.nt.obj" "isim/drp_demo_tb_isim_beh.exe.sim/work/a_38774626​17_3212880686.nt.obj" "C:/Xilinx/11.1/ISE/vhdl/hdp/nt/std/STD.nt.a" "C:/Xilinx/11.1/ISE/vhdl/hdp/nt/ieee/IEEE.nt.a" "C:/Xilinx/11.1/ISE/lib/nt/libhsimengine.lib"Compiled 30 VHDL UnitsBuilt simulation executable C:/Project/ISim_Tutorial/drp_demo_tb_isim_beh.exeFuse Memory Usage: 81464 KBFuse CPU Usage: 1046 msLaunching ISim simulation engine GUI..."C:/Project/ISim_Tutorial/drp_demo_tb_isim_beh.exe​" -gui -tclbatch isim.cmd -wdb "C:/Project/ISim_Tutorial/drp_demo_tb_isim_beh.wdb​"ISim simulation engine GUI launched successfully

    Process "Simulate Behavioral Model" completed successfully ---------------------!!!!!!!!!!!!!OK

    :smileyhappy:

    I postes this because maybe can help someone.

    Sorry for my english.

  • RELEVANCY SCORE 3.10

    DB:3.10:How To Measure Simulation Time With System Generator For Hardware Co-Simulation? 9j



    I am using hardware co-simulation now , and I find xapp1031.pdf is very helpful. But I have a question that how to measure simulation time with system generator for hardware co-simulation?

    Could anyone help me ?

    Thanks!

    DB:3.10:How To Measure Simulation Time With System Generator For Hardware Co-Simulation? 9j

    As per the Xapp1031 note, various timing results are shown in table form e.g (Table 6: Simulation Runtimes for Software-based Shared FIFOs , page 21)
    If we read it carefully , they never mentioned any script or file in the generated folder which shows those numbers which they displayed in various tables except for model implementation_2 ( for which one script is given for modelsim).

    I have a big doubt Is there any ways to get these results , since an excel sheet is given to make our own results in their format( but how?).

    lastly i am interested to get timing for my model for parameters like table 6 for various implmentation
    Simulink: Outside System Generator
    Sysgen: Block Configuration
    Sysgen: Compile
    Sysgen: Initialize Simulation
    Sysgen: Simulation

    please help me!
    thanks
    gaurav

  • RELEVANCY SCORE 3.09

    DB:3.09:Ml605 Pcie - Isim Simulation Problem - 64 Elements ; Expected 32 9s



    Hi everybodyI have built a system for my ML605 (Virtex-6) with BSB (XPS).The specific system is AXI, microblaze based snd I have also added PCIe core in the very begining of BSB configuration.Implementation flow runs OK, but I get the following ERRORS in pcore library files with iSim simulation flow:ERROR:HDLCompiler:410 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 723: Expression has 64 elements ; expected 32ERROR:HDLCompiler:1318 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 744: Left bound value 127 of slice is out of range [63:0] of array wdataERROR:HDLCompiler:1318 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 757: Left bound value 95 of slice is out of range [63:0] of array wdataERROR:HDLCompiler:1318 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 765: Left bound value 127 of slice is out of range [63:0] of array wdataERROR:HDLCompiler:1318 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_write_req_tlp.vhd" Line 768: Left bound value 95 of slice is out of range [63:0] of array wdataERROR:HDLCompiler:1318 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_read_cpl_tlp.vhd" Line 495: Left bound value 127 of slice is out of range [63:0] of array tdata_regERROR:HDLCompiler:410 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_read_cpl_tlp.vhd" Line 589: Expression has 64 elements ; expected 32ERROR:HDLCompiler:410 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_mm_s_v1_02_a/hdl/vhdl/slave_read_cpl_tlp.vhd" Line 651: Expression has 64 elements ; expected 32ERROR:HDLCompiler:845 - "/tools/Xilinx/ISE/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_enhanced_pcie_v1_02_a/hdl/vhdl/axi_enhanced_pcie.vhd" Line 2032: Type of aggregate cannot be determined without context ; 11 visible types match hereFATAL_ERROR:Simulator:CompilerAssert.h:40:1.20 - Internal Compiler Error in file ../src/VhdlTreeTransform.cpp at line 1634 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.FATAL_ERROR:Simulator:CompilerAssert.h:40:1.20 - Internal Compiler Error in file ../src/VhdlTreeTransform.cpp at line 1634 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.PCIe configuarion in BSB is the default one (64-bit for axi master and slave data bus).I work with 13.4 ISE in Ubuntu OS.Can anybody help ?Regardslatal

    DB:3.09:Ml605 Pcie - Isim Simulation Problem - 64 Elements ; Expected 32 9s


    This AR has the fix:http://www.xilinx.com/support/answers/46563.htm

  • RELEVANCY SCORE 3.09

    DB:3.09:Wrong Output Value Of Co-Simulation On Zynq Zc702 Evaluation Board 3k



    Hi

    I am doing the co-simulation with Zynq zc702 evaluation board as following figure.

    also, I am using matlab 2013b, xilinx ISE 14.7 system generator.

    there is wrong output value after running the co-simulation.

    plz help me if you know about this.

    thanks in advance.










    Attachments:







    sg_tut_add.mdl ‏78 KB

    DB:3.09:Wrong Output Value Of Co-Simulation On Zynq Zc702 Evaluation Board 3k


    Hi all,

    I want to make co-simulation for simple adding operationand the board used isML605. The cosimulation block is generated and I run cosimulation in single stepping mode. In addition,number of bit and binary point is set to 16 and 14 ingateway In blocks, respectively. Simulation is in discrete (no continuous). But, the outputs of simulation and co-simulation is not matched. Are there anybody to help me about this one. where do i makewrong. I would be so glad if you help me. Thanks in advance

  • RELEVANCY SCORE 3.06

    DB:3.06:Microblaze Simulation fk



    Hi,

    I have some problems on microblaze project simulation. My XPS version is 14.4. I can successfully generate the HDL simulation files, but it seems I can't get the right .mem files for instruction memory initialization. My flow is:

    1. Create and edit the XPS project, and import XPS project into SDK.

    2. Create a SDK application project and edit the source code. Generate .elf file.

    3. Go back to XPS, click Project - Select elf file - choose simulation elf file - navigate to and choose the .elf file mentioned above.

    4.Click Project - project options. Config the Design flow as the picture:

    5.Simulation - Generate simulation HDL files

    but when I started simulation, microblaze failed to execute instruction. And I found there's no correct .mem file. I uploaded the .mem, .elf, simgen.log, simgen.opt files.

    Is there any wrong procedure I made? Or did I miss something?










    Attachments:







    simulation_test.zip ‏41 KB

    DB:3.06:Microblaze Simulation fk


    Hi,

    The steps seem to be fine. Where is the application running from? is it external memory model/bram?

    --HS




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.01

    DB:3.01:Is Modelsimxe3 6.4b Supports Mixed Hdl ? j8



    I have installed Starter edition of ModelsimXE3 6.4b and simulate design it contains mixed HDL ...

    I got error like XE version supports only single HDL..

    Is Xilinx - Modelsim versions supports only Single HDL?


    DB:3.01:Is Modelsimxe3 6.4b Supports Mixed Hdl ? j8


    Hi,

    Please see the MXE FAQ on this:

    http://www.xilinx.com/support/answers/24506.htm

    Modelsim Xilinx Edition does not support mixed-language only the non-OEM versions provide this option from Mentor. Or you can use ISim.

    ThanksDuth

  • RELEVANCY SCORE 3.00

    DB:3.00:Vivado Hls C/Rtl Cosimulation Performing For Ages Without Result fp



    Hello everyone;

    I am using Vivado HLS 2012.4 for my design using C, the C simulation is successful but I am not able to do the SystemC Co-simulation. I am not having any error but the Co-simulation is in progress for ages without any result until I stop it manually.

    Does anyone have the same problem? or why the co-simulation is in progress for too long?

    The Co-simulation is working fine with other designs.

    Regards,

    Amine.

    DB:3.00:Vivado Hls C/Rtl Cosimulation Performing For Ages Without Result fp

    Hi, Debrajr, Since this is not an open project. I will send you a private email. :-)Regards,Henry

  • RELEVANCY SCORE 3.00

    DB:3.00:Vivado 14.5 And Questasim 10.2c 33



    Hellow,

    I am working with ISE 14.5 and it is compatible with Questa Sim-64 10.1b, but I do not know if it is , also, compatible with QuestaSim 10.2c (I have this last version)).

    I introduce the simulator "questasim.exe" in ISE (preferences, etc.)

    I compile the libraries (Compile HDL Simulation Libraries) without problems.

    I have a problem in ISE when I wor with Simulate Behavioral Model", obtaining an error as: libraries compiled with 'questasim 10.2c' but the simulator selected is 'questasim 2013.07'.

    The version of the questasim 10.2c is 2013.07 July 19 2013).

    Thanks.

    Guillermo

    DB:3.00:Vivado 14.5 And Questasim 10.2c 33

    Hello,Set the modelsim enviornmental variable to modelsim.ini located in compiled library location ORcopy the modelsim.ini file from compiled library folder to project directory.Thanks,Vinay



    --------------------------------------------------------------------------------------------Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

  • RELEVANCY SCORE 2.98

    DB:2.98:Test Bench Waveform Editor 93



    ISE 9.2, Is there a way to copy and paste signal in existing waveform?

    So far I had to work with the generated HDL code directly.

    thanks,
    Message Edited by legendbb on 02-27-2009 03:48 PM

    DB:2.98:Test Bench Waveform Editor 93


    The testbench waveform editor does not have this feature. We apologize for the inconvenience.

    Be advised, the Testbench Waveform Editor has been depracated starting the upcoming version of ISE. As a replacement, you can use the "Language Templates" in the Edit menu, as well as the templates created for you when using "Add New Source" -- "VHDL testbench" / "Verilog test fixture" to write HDL testbench files.




    Eddie

  • RELEVANCY SCORE 2.97

    DB:2.97:Comparison Of Time For Co-Simulation With System Generator zc



    Hello, I am new to everything about fpga and currently I am working with matlab system generator, I am working on image processing.

    What I do is to compare times between simulation and co-simulation, what I want is to show that the processing is faster does the FPGA priate.

    many Thanks

    DB:2.97:Comparison Of Time For Co-Simulation With System Generator zc

    Sounds reasonable. What is your question?I will caution you (because everyone always runs into this when doing this type of measurement...), be aware that there is non-trivial overhead associated with transferring between FPGA board and host PC during hardware co-sim that is not really representative of the end system.



    www.xilinx.com

  • RELEVANCY SCORE 2.97

    DB:2.97:Simulation In Xps 93



    Hi All,

    I would like to simulation myapplication in XPS (without real hardware). My steps are shown below:

    - Compile ISE and EDK libraries

    - Generate simulation HDL files with behavioral option

    - Launch EDK shell and disassembly the appcation which the output file is the .dis file

    - In XPS, select Simulation - Launch HDL Simulator

    In last step, the wanrning message shows me that it is used for Top level module only. Please anyone suggest me a simple example for simulating in XPS fileon Xilinx virtex 2Pro.

    Regards,

    DB:2.97:Simulation In Xps 93


    Hi,

    Please check Behavioral Simulation topic starting page 39 of this doc.

    http://www.xilinx.com/support/documentation/tutori​als/EDK92_PPC_tutorial.pdf

    Thnx




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.96

    DB:2.96:Not Getting Proper Output From Hardware-Software Co-Simulation Generated Block jx


    respected sir ,i tried with digitlent board ,xc3s500e-4fg320,but my output software and hardware are different.pls suggest if can identify the problem to get proper output. iam not getting the proper output as simulation output.second row is my output.this is the ask modulation output generated from hardware -software co-simulation.pls suggest me to get the proper output.

    thanks

    prasad

    Attachments:

    DB:2.96:Not Getting Proper Output From Hardware-Software Co-Simulation Generated Block jx

    respected sir ,i tried with digitlent board ,xc3s500e-4fg320,but my output software and hardware are different.pls suggest if can identify the problem to get proper output. iam not getting the proper output as simulation output.second row is my output.this is the ask modulation output generated from hardware -software co-simulation.pls suggest me to get the proper output.

    thanks

    prasad

    Attachments:

  • RELEVANCY SCORE 2.96

    DB:2.96:Hardware Co-Simulation Kintex7 And Fmc150 kf



    My aim is to do hardware co-simulation in Matlab using the reference design for hardware co-simulation (using kintex 7 and fmc 150 card) provided on the site.

    Steps followed :-Downloaded the using-xilinx-system-generator-for-dsp-with-simulin​k-and-hdl-coder.zip file containing the plugins and the reference design.

    1) I installed the plugin as suggested in the Using Xilinx System Generator for DSP with Simulink and HDL Coder Tutorial v1_0 pdf document.

    2) Running only the simulation works properly.getting the constellation plot on the scope.

    3)For doing hardware co-simulation I changed the compilation mode to data acquisition mode.

    4)And then running the simulation, the fpga is programmed through the JTAG

    5) But the constellation scope on the Simulink model shows nothing.

    I also checked the DAC C D port output on oscilloscope but nothing was coming on it. For checking whether the card is working properly I dumped the reference bit file on it and checked the output of the DAC C D port on oscilloscope .it was correctly producing the sine wave output.But the hardware co-simulation design file is dumping on FPGA but no output is coming on scope in Simulink and also no output is coming on DAC Port C D.if somebody can help me with this?

    gitanjali

    DB:2.96:Hardware Co-Simulation Kintex7 And Fmc150 kf


    Hi,

    i changed my ram from 3 to 3.8 gb and now it is showing the output but the constellationplot is not locking.

    if i see on the oscilloscope the dac output always comes as square wave type signal with frequency 50Hz.

    i donot know why . if u can help?

    thanks a lot

    gitanjali

  • RELEVANCY SCORE 2.96

    DB:2.96:Microblaze Project Simulation In Edk (With Isim) aj



    Hi everybody,

    I have connected a coprocessor to Microblaze in EDK through FSL

    Unfortunately, I have some problems on microblaze project simulation. I have an XPS version is 12.4. I can successfully generate the HDL simulation files, but it seems I can't get the rightinput/output data after simulation. I'm getting always 0 for FSL_S_Data (input data) and FSL_M_Data (outputData).

    Can you help me please.

    DB:2.96:Microblaze Project Simulation In Edk (With Isim) aj

    Hi,Please check the following thread which may be helpful to youhttp://forums.xilinx.com/t5/Embedded-Processor-Sys​tem-Design/Read-from-FSL-is-always-zero/td-p/10832​7



    Thanks,Vijay--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 2.96

    DB:2.96:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... d7


    hi,I wanted to simulate an ipcore with xps.I compiled the simulation libraries,then I generated simulation HDL files.but when I select the launch HDL simulatorI enconter the following:make: nothing to be done for "simmodel'best regards.

    DB:2.96:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... d7


    Hi,

    There's nothing wrong with the message. It means that it's not necessary to generate simulation HDL files again.

    The ModelSim is supposed to be launched soon after the message shown up.

    -XFMessage Edited by xiaofeip on 12-12-2007 11:05 PM

  • RELEVANCY SCORE 2.95

    DB:2.95:Error: [Simtcl 6-50] Simulation Engine Failed To Start: Cannot Create Simualtion Database Drawing File. jm



    What can be the cause for this error?

    How can I find out which path the uncreatable "simualtion [sic] database drawing file" has?

    Here is the compete TCL Console output:

    launch_simulation
    WARNING: [Vivado 12-3661] Failed to remove file:c:/users/makra/hdl/schepers/egrabox/ip_repo/s​teppermotor_pulse_generator_1.0/steppermotor_pulse​_generator_v1_0_project/steppermotor_pulse_generat​or_v1_0_project.sim/sim_1/behav/xelab.pb
    INFO: [USF-XSim-27] Simulation object is 'sim_1'
    INFO: [USF-XSim-37] Inspecting design source files for 'steppermotor_pulse_generator_v1_0' in fileset 'sim_1'...
    INFO: [USF-XSim-97] Finding global include files...
    INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
    INFO: [USF-XSim-2] XSim::Compile design
    INFO: [USF-XSim-61] Executing 'COMPILE' step in 'c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/steppermotor_pulse_gen​erator_v1_0_project/steppermotor_pulse_generator_v​1_0_project.sim/sim_1/behav'
    "xvhdl -m64 -prj steppermotor_pulse_generator_v1_0_vhdl.prj"
    Determining compilation order of HDL files.
    INFO: [VRFC 10-163] Analyzing VHDL file "c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/hdl/steppermotor_pulse​_generator_v1_0_S00_AXI.vhd" into library xil_defaultlib
    INFO: [VRFC 10-307] analyzing entity steppermotor_pulse_generator_v1_0_S00_AXI
    INFO: [VRFC 10-163] Analyzing VHDL file "c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/hdl/steppercontroller.​vhd" into library xil_defaultlib
    INFO: [VRFC 10-307] analyzing entity steppercontroller
    INFO: [VRFC 10-163] Analyzing VHDL file "c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/hdl/steppermotor_pulse​_generator_v1_0.vhd" into library xil_defaultlib
    INFO: [VRFC 10-307] analyzing entity steppermotor_pulse_generator_v1_0
    INFO: [USF-XSim-3] XSim::Elaborate design
    INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/steppermotor_pulse_gen​erator_v1_0_project/steppermotor_pulse_generator_v​1_0_project.sim/sim_1/behav'
    Vivado Simulator 2014.4
    Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.
    Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xela​b.exe -wto 8540dae593e541e0bf48bbf3d0090e06 --debug typical --relax -L xil_defaultlib -L secureip --snapshot steppermotor_pulse_generator_v1_0_behav xil_defaultlib.steppermotor_pulse_generator_v1_0 -log elaborate.log
    Multi-threading is on. Using 6 slave threads.
    Starting static elaboration
    Completed static elaboration
    Starting simulation data flow analysis
    Completed simulation data flow analysis
    Time Resolution for simulation is 1ps
    Compiling package std.standard
    Compiling package ieee.std_logic_1164
    Compiling package ieee.numeric_std
    Compiling architecture arch_imp of entity xil_defaultlib.steppermotor_pulse_generator_v1_0_S​00_AXI [\steppermotor_pulse_generator_v1...]
    Compiling architecture behavioral of entity xil_defaultlib.steppercontroller [steppercontroller_default]
    Compiling architecture arch_imp of entity xil_defaultlib.steppermotor_pulse_generator_v1_...
    Built simulation snapshot steppermotor_pulse_generator_v1_0_behav
    INFO: [USF-XSim-4] XSim::Simulate design
    INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'c:/users/makra/hdl/schepers/egrabox/ip_repo/stepp​ermotor_pulse_generator_1.0/steppermotor_pulse_gen​erator_v1_0_project/steppermotor_pulse_generator_v​1_0_project.sim/sim_1/behav'
    INFO: [USF-XSim-98] *** Running xsim
    with args "steppermotor_pulse_generator_v1_0_behav -key {Behavioral:sim_1:Functional:steppermotor_pulse_ge​nerator_v1_0} -tclbatch {steppermotor_pulse_generator_v1_0.tcl} -log {simulate.log}"
    INFO: [USF-XSim-8] Loading simulator feature
    Vivado Simulator 2014.4
    Time resolution is 1 ps
    ERROR: [Simtcl 6-50] Simulation engine failed to start: Cannot create simualtion database drawing file.
    Please see the Tcl Console or the Messages for details.

    ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.
    launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1102.602 ; gain = 0.000







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.94

    DB:2.94:Error Hdl Compiler 410 x3



    I am trying to simulate the behaviour of a Virtex 5 project bought from a third party supplier. I am using ISE 11.1 and trying to use iSim as the simulation tool. The code was built in ise9.3 and 10 but was supposed to be updated for 11.

    The code synthesises ok but I get the following error on simulation: ERROR hdl compiler 410 'k:/IP1_L.24/env/Database/ip/export/prefetchmodels​/ntopt/vhdl/src/XilinxCoreLib/fifo_generator_v4_2.​vhd' Line 3629:Expression has 10 elements;expected 11.

    looking on previous info for this error it has something to do with a resizing command but I cannot access it as it is a generated core.

    Any sugestions greatfully recieved!!

    Graham

    DB:2.94:Error Hdl Compiler 410 x3


    HI Graham,

    Can you start by talking to your IP provider to confirm it has been verified against the latest version of the ISE SW - 11.4?

    This looks like a design problem that the IP provider can fix since they have the source code.

    Thanks

    Duth

  • RELEVANCY SCORE 2.94

    DB:2.94:Dsp Coregen And Hardware Cosimulation 1f



    Hello,

    I have a ML507 (V5FX70T) Evaluation board and I try to implement HW co simulation. In my previous post, I did a HW co simulation with only LUTs in my design. Now, I want to make a HW co simulation with a DSP included in an entity. You can see the hierarchy in the attach file.

    When I run the simulation, I have the following error :

    ++++++++++++++++++++++++++++++++++++++++++++++++++​+++++++++++++++++++++++++++++++++++++

    INFO:HWCoSim - Implementing hardware co-simulation top-level through NGDBuild, MAP and PARERROR:HWCoSim - Program 'xflow' reported the following errors:--------------------------------------------------​------------------------------ERROR:NgdBuild:604 - logical block 'hwcif/hwcosim_dut_inst/DSP_COREGEN_INST/MULT_INST​' with type 'MULTIPLIEUR' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'MULTIPLIEUR' is not supported in target 'virtex5'.ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...--------------------------------------------------​------------------------------ERROR:HWCoSim - Program 'xflow' returned with a non-zero exit code 1. Please refer to log file 'E:\SEBASTIEN_LAMONNIER\Fonctionnalites\CoSimuHard​ware\XST_SelectMap_Reconf_DSP\synthese\Cosimu\isim​\hwcosim_tmp\jtag\xflow\xflow.log' for further details. HDL wrapper and bitstream generation process failed.

    ++++++++++++++++++++++++++++++++++++++++++++++++++​++++++++++++++++++++++++++++++++++++++

    So I think the error is concerning the instance U0 in the VHD generated by Coregen (instanciation of wrapped_Multiplieur).

    I regenerated the Coregen, I imported ngc, vhd etc without success... but I can make HW cosimulation if I declare a bloc without Coregen in it (I_COMPTEUR for example in my design).

    Perhaps anyone will have a good idea to help me !!!

    Thanks a lot :)

    Lamonnis







    Solved!
    Go to Solution.

    DB:2.94:Dsp Coregen And Hardware Cosimulation 1f


    How can you add ngc files if you are using fuse with command line? I see the same error as described previously, but there is no .xise file when using command line.

    Thanks.

  • RELEVANCY SCORE 2.94

    DB:2.94:Simulation Error cp



    Hi

    I have been making changes in my HDL codes and running test bench with each change in ISim simulator. But suddenly after I made some changes in some of the input size the simulation is not running and giving me error message that :

    INFO:ProjectMgmt - The selected process was not run because a prior process failed.

    When I am running Behavior Check Systax it is showing successful.

    Can anyone please tell me what might have gone wrong?

    DB:2.94:Simulation Error cp


    Hi..

    I was getting the same error, and I corrected acoording to your instruction. but now the problem is double clicking on stimulas behabviour keeps it running and running continuously, what can be done to further?

  • RELEVANCY SCORE 2.94

    DB:2.94:Pcie Vhdl Simulation With Active-Hdl ja



    I'm trying to get the Spartan 6 PCIe endpoint example simulated in Aldec Active-HDL (VHDL-only license), but I'm running into an issue with axi_basic_top - there seem to be only Verilog files for this portion of the project. Is it possible to simulate the Spartan 6 integrated block for PCIe within Aldec Active-HDL with only a VHDL simulation license?Thanks.

    Damon

    DB:2.94:Pcie Vhdl Simulation With Active-Hdl ja


    Hi,

    If you use ISE 13.2 and generate a v2.3 S6 core, you will get VHDL files for the AXI wrapper source.

    It will have to be able to simulate the underlying SecureIP model which requires a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator The SecureIP models the GTPs and the PCIe block. I am not familiar with how Aldec would handle this but for a simulator like MTI, there is a way to enable this functionality without getting a full Verilog license.

    Hope this helps,

    John

  • RELEVANCY SCORE 2.93

    DB:2.93:Error In Simulation Using Modelsim Xe Iii c9



    Hi all

    I am trying to simpulate vhdl code written using ise 10.1 (nt) application version K 31, and using simulator ModelSim SE III / starter 6.3c, then it shows following error, please guide me, how to remove the error. In the vhdl code I am using library unisim.

    # ** Error: clock_gen.vhd(27): Library unisim not found.# ** Error: clock_gen.vhd(28): (vcom-1136) Unknown identifier "unisim".# ** Error: clock_gen.vhd(30): VHDL Compiler exiting# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.

    According some posts, Itried to comple the library (i.e. selecting device in 'sources' window and choosing 'complile HDL Simulation Libraries' from process window. but it again shows a message window with message "compilation of HDL simulation Libraries for ModelSim XE-VHDL is not supported"







    Solved!
    Go to Solution.

    DB:2.93:Error In Simulation Using Modelsim Xe Iii c9


    Thankx

    as per your instruction I downloaded the library from the site, now its working

    Regards

  • RELEVANCY SCORE 2.92

    DB:2.92:Exuberant Compile Time For Hdl Netlist sd



    G'day,

    ISE 13.2

    Virtex6 (ML605 dev kit)

    I'm have no idea how long a system generator project to compile to a HDL netlist is supposed to take, but so far I've been waiting well over an hour. Is this normal? Xilinx blockset design isn't huge, ( Simple AM demodulator so a few filters, squarer etc) I don't have this problem when running HW co simulation, only now when I'm trying to add a system generator (sgp) source to ISE. I thought it just produced VHDL code?

    DB:2.92:Exuberant Compile Time For Hdl Netlist sd


    Compilation time can vary. Usually it has to do with how large and full your part is, and how difficult your timing constraints are to meet. If you are trying to run at a high frequency that can cause the compilation to be longer because it might not be easy for the tools to meet the requested timing.




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 2.89

    DB:2.89:Problems With System Generator!!!! s3


    Hi,we created a OFDM model in Simulink and It was right
    when we did the simulation . However ,when the model was complied to HDL
    Netlist ,we discovered (in ISE Sources window) that some instances were
    lost,those instances are as follows:?inst - C_COUNTER_BINARY_V7_0?inst - BLKMEMSP_V6_1?inst - C_DIST_MEM_V7_1?inst - C_DDS_V4_1?inst - C_SHIFT_RAM_V7_0?inst - BLKMEMDP_V6_1and there are also some clock problems listed as follow:in xlclockdriver_1:?clr_reg - synth_reg_w_init?ce_reg - synth_reg_w_initin xlclockdriver_5:?clr_reg - synth_reg_w_init?ce_reg - synth_reg_w_init Version is ISE 9.2,SystemGenerator 9.2,and Matlab 2007a.we
    checked those instances in the simulink model ,but can't find them,I
    think it may have something to do with my software, but we can't solve
    the problem!!!please help!!!Regardsjames chan






    Solved!
    Go to Solution.

    DB:2.89:Problems With System Generator!!!! s3


    hello mazene.. i have a question, if you could help me with your design.. i'm making a modem ofdm according to 802.16d but i'm having problems with some blocks. ex fft i cant configure it the right way.. in the modulator side

    could you upload your file?

  • RELEVANCY SCORE 2.88

    DB:2.88:Why Can't I Generate Simulation Hdl In 13.3 Edk? x7



    I am having problems generating simulation HDL in 13.3 EDK.

    I did generate the 13.3 Modelsim libraries outside of EDK because inside EDK it would only allow me SE and I have PE.

    Now when I try to generate the simulation HDL I get the message: " The selected simulator is mti; the specified simulation library was compiled with mti_pe"

    I have selected the path in the EDK preferences as simulator path:.../win32pe and library path:.../13.3 (where all the libraries are.)

    Does anyone know where (what file) the selected simulator is defined in so I can change it to mti_pe?

    Can I generate the simulation HDL from the command line?

    Where can I change the default selection of SE to PE so that I can generate the libraries from inside EDK?

    Why did Xilinx remove the simulation selection when EDK in invoked from ISE?

    Thanks

    Orlee







    Solved!
    Go to Solution.

    DB:2.88:Why Can't I Generate Simulation Hdl In 13.3 Edk? x7


    Thank you John. The issue is simply fixed by using the 32-bit version of the Library Compilation Wizard. Thanks for pointing me in the right direction :)

  • RELEVANCY SCORE 2.88

    DB:2.88:What Design Files Are Need For Timing (Post Route) Simulation In Modelsim? kf



    For Behavioral simulation in Modelsim, the design files I need are HDL files (If I design with HDL). However, there are other three levels simulation, post-translate, post-map, post-route.I think the most important I think post route simulation. So what design files I need?

    If someone who is familar with all these levels simulation is willing to explain what design files needed for each level individually, that will be great!

    Thanks a lot!

  • RELEVANCY SCORE 2.88

    DB:2.88:Trouble With Post Synthesis Functional Sim 19



    I am getting the following error when i try running a post synthesis functional sim. Any pointers will help.

    Starting static elaborationCompleted static elaborationStarting simulation data flow analysisCompleted simulation data flow analysisERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.Printing stacktrace...

    [0] (KiUserExceptionDispatcher+0x2e) [0x77b01248][1] (memmove+0x39) [0x7fef4e7c3b9][2] [0xffffffb0][3] [0x9c4000][4] (ISIMC::Options::parseVlogcompCommandLine+0xcba7c) [0x13f6f0f0c][5] (ISIMC::Options::parseVlogcompCommandLine+0xa54d8) [0x13f6ca968][6] (ISIMC::Options::parseVlogcompCommandLine+0x9ce69) [0x13f6c22f9][7] (ISIMC::Options::parseVlogcompCommandLine+0x9f5fc) [0x13f6c4a8c][8] (ISIMC::Options::parseVlogcompCommandLine+0x9f0e5) [0x13f6c4575][9] (ISIMC::VhdlCompiler::saveParserDump+0x7917d) [0x13f6131cd][10] [0x13f48273a][11] [0x13f484fbd][12] [0x13f483d9f][13] (ISIMC::Options::parseVlogcompCommandLine+0x122673​) [0x13f747b03][14] (BaseThreadInitThunk+0xd) [0x779a59ed]

    Donerun_program: Time (s): cpu = 00:00:02 ; elapsed = 00:03:53 . Memory (MB): peak = 4590.086 ; gain = 0.000ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '' file for more information.launch_simulation: Time (s): cpu = 00:01:21 ; elapsed = 00:07:38 . Memory (MB): peak = 4590.086 ; gain = 0.000

    Log file output

    Vivado Simulator 2014.3Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.Running: C:/Xilinx/Vivado/2014.3/bin/unwrapped/win64.o/xela​b.exe -wto 0784bce1831d4b3f89d627679fe7d87d --debug typical --relax --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Projects/INTEREST_POINT_PLDA/FPGA/hdl/verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Projects/INTEREST_POINT_PLDA/FPGA/ip/ila_133_204​8/ila_v5_0/hdl/verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Projects/INTEREST_POINT_PLDA/FPGA/ip/ila_133_204​8/ltlib_v1_0/hdl/verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Projects/INTEREST_POINT_PLDA/FPGA/ip/ila_133_204​8/xsdbs_v1_0/hdl/verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/sop/operator/fast_hessian_v1_00_a/hdl/​verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/sop/operator/orientation_assign_v1_00_​a/hdl/verilog --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/sop/sop_ip_detector_v2_00_a/hdl/verilo​g --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/vcores/cores/nif_mem_v1_00_a/hdl/veril​og --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/vcores/cores/nif_mem_v2_00_a/hdl/veril​og --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/vcores/cores/qpcie_x8_gen2_v1_00_a/hdl​/verilog/source/include --include ../../../../../../istc_ec_repository/ReALM/hardwar​e/Vortex/hw/vcores/cores/vortex_include_v3_00_a -L xil_defaultlib -L unisims_ver -L secureip --snapshot fpga_func_synth xil_defaultlib.fpga xil_defaultlib.glbl -log elaborate.log Multi-threading is on. Using 6 slave threads.Starting static elaborationCompleted static elaborationStarting simulation data flow analysisCompleted simulation data flow analysisERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

    DB:2.88:Trouble With Post Synthesis Functional Sim 19

    Hi,Is it possible to test in 2014.4? Many of such crashes are addressed in the latest version.I will try in the latest build if you can provide me the archived project.



    Thanks,Vijay--------------------------------------------------------------------------------------------Please mark the post as an answer "Accept as solution" in case it helped resolve your query.Give kudos in case a post in case it guided to the solution.

  • RELEVANCY SCORE 2.87

    DB:2.87:Problems Compiling Simulation Libraries In Xps m8



    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

    DB:2.87:Problems Compiling Simulation Libraries In Xps m8


    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

  • RELEVANCY SCORE 2.86

    DB:2.86:System Generator For Dsp Crashes Matlab While Compiling Netlist s8



    Hi,

    I have Matlab 2010a Student Edition and Xilinx ISE 13.3 which I upgraded from 13.1 that came with the Virtex-6 FPGA ML605 Evaluation Kit from Avnet (i.e. node-locked license). My environment is Windows 7 Enterprise 64-bit running on a HP Elitebook 8440p core i5 quad core with 4GB RAM and a SSD.

    I had to manually install the 32-bit ISE as my Matlab is 32-bit.

    The problem I have is that system generator for DSP simulates fine with no problems - I get the notification that the compiler is running and then the simulation runs OK.

    BUT, if I try to co-sim or in any way run the HDL compiler I get the 'compilation starting' pop-up and immediately Matlab crashes and burns. This happens for every model including the basic lab exercises in sysgen /examples directory. No logs - apart from useless 'there has been an internal error 0001' sysgen_error log.

    So. I ran Windows Error Reporting and obtained a core dump (attached). I also ran Process Monitor from sys utils on it and get this event immediately before the crash :

    MATLAB.exe RegOpenKey HKCU\SOFTWARE\FLEXlm License Manager NAME NOT FOUND

    As I understand it, Matlab Student Edition does not contain the FLEXlm license manager? I don't know if this is the cause of the crash but that is the last event before it goes phut.

    Anyone any ideas?

    Brian.










    Attachments:







    MATLAB.dmp ‏243 KB

    DB:2.86:System Generator For Dsp Crashes Matlab While Compiling Netlist s8


    See the screenshot of my XLCM - note the stated serial number matches the host id but it still says 'No' in Host Id Matches?

    ... I'll try the MAC address approach.

    Many thanks,

    Brian.










    Attachments:




  • RELEVANCY SCORE 2.85

    DB:2.85:Hw Co-Simulation For Multiple Subsystem Generator 78



    I have seen two following messages and i totally mixed up!

    http://forums.xilinx.com/t5/DSP-Tools/Multiple-Dime-Clocks-Co-Simulation/m-p/71785

    http://forums.xilinx.com/t5/DSP-Tools/Co-simulation-with-Multiple-Subsystems-in-SysGen/m-p/38978

    First one states that "The Multiple Subsystem Generator doesn't support HW-CoSim generation", but in the second one,edwarwlis cosimulating his own multiple clock design.

    So,question is :

    Is HW cosim possible for multiple clock design? If so, how?

    Thanks

  • RELEVANCY SCORE 2.85

    DB:2.85:Is S3ansk Support Hardware Co-Simulation Through Usb? 31


    Can anybody help me whether S3ANSK supports hardware co-simulation through USB and if not how can I use the Kit with hardware co-simulation.

    DB:2.85:Is S3ansk Support Hardware Co-Simulation Through Usb? 31

    Can anybody help me whether S3ANSK supports hardware co-simulation through USB and if not how can I use the Kit with hardware co-simulation.

  • RELEVANCY SCORE 2.84

    DB:2.84:Cannot Generate Simulation Hdl Files On Linux 89



    Hi,

    I am using version 13.1 and I cannot generate the simulation HDL files on linux. Each time I try, I get this error:

    The current EDK version is 13.1. The specified simulation library /home/duhem/simlib/13.1 was compiled with version 13.1:13.1. Please recompile the simulation library with the current EDK software.

    The simulation library has been successfully generated with this version, so I do not understand this error message... Any clue?

    Regards,

    fduhem

  • RELEVANCY SCORE 2.83

    DB:2.83:Simulation Of Design Having Ip Core And Simulator Is Modelsim Se (Vhdl Only) sa



    Since IP core instantiation templates available in xilinx ISE are in both HDL( VHDL and Verilog).

    I Have modelsim SE (VHDL only) license . I want to use DDS IP core in my design and also simulation of design with available modelsim SE (VHDL) tool. It is possible or it requires modelsim SE ( mixed) licens,since IP core are written in either VHDL or verilog.

    DB:2.83:Simulation Of Design Having Ip Core And Simulator Is Modelsim Se (Vhdl Only) sa


    Some cores have simulation models/wrappers available in both VHDL and Verilog, while some others in just one language. Fortunately for you most IP models are available in VHDL, the DDS Compiler being one of them. So you should be good with the ModelSim SE VHDL only version.




    Eddie

  • RELEVANCY SCORE 2.83

    DB:2.83:Hdl Simulation Libraries Cross Ise Version? 8d



    I could not resolve the library compilation problem (smartmodel, vhdl, simprim, 14 Errors) at this moment, can I copy the library from another working machine (ISE 8.2i) to current machine ISE 9.2i?

    Thanks,







    Solved!
    Go to Solution.

    DB:2.83:Hdl Simulation Libraries Cross Ise Version? 8d


    Yes and No. It depends on how "complex" your design is. NetGen in ISE 9.2 builds a Post-PAR simulation model that instantiates SIMPRIM primitives from that same version. That is, you may find a situation where a SIMPRIM primitive from the generated simulation model is not available in the 8.2 libraries. Also, the primitives in these libraries may be updated, with either added/removed parameters to the models. As such, even though the primitive exists in the SIMPRIM libraries, the instantiation may not match the module/entity declaration of the models, causing a failure in simulation.

    However, if the design is small, using an older part such as a Virtex-II or Spartan-2, then it's likely that the models have remained the same between these two versions. However, this practice is neither recommended nor supported, so it's best that you use this forum, as well as the Xilinx Answers, to resolve the library compilation problems you are encountering.

    -edv




    Eddie

  • RELEVANCY SCORE 2.83

    DB:2.83:Question About Fir Compilers In Hardware Co-Simulation. kp


    Hello all,

    I am now trying to filter an image with the hardware co-simulation by p2p ethernet.
    The FIR filter compilers(1.0-3.1) with 41 coefficients work correctly at the software simulation stage.
    However, it do nothing after generating the LIB with system generator and downloading into the FPGA.
    Is that any parameter uncorrect? Or isthe coefficient too many?

    DB:2.83:Question About Fir Compilers In Hardware Co-Simulation. kp

    You should use the latest version of the FIR Compiler available in System Generator which is v3.1. The number of coefficients you've chosen is perfectly valid. I suspect the problem may be with your hardware co-simulation setup. You may want to try a basic "pass through" design with a couple registers only to confirm that your hardware co-simaultion is set up properly before moving on to a more complex design.

  • RELEVANCY SCORE 2.82

    DB:2.82:Co-Simulation Mode For Zedboard... zz



    Hi,

    I switched from using Simulink Blocks + HDL Coder to using Xilinx System Generator Blocks for implementation of OFDM Transceiver (Last year Project).

    Though blocks are easy to use but I loose the ability to do co-simulation with Zedboard.Using Simulink+HDL Coder Co-simulation was really good i.e I was able to provide input from Simulink, Run my IP Core on Zedboard and get the output back to Simulink.

    In Compilation - Hardware Co-Simulation - There is no Zedboard mentioned.

    Can someone tell if Zedboard Co-Simulation can be supported? If yes I need some instructions.

    Thanks

    Raj

    DB:2.82:Co-Simulation Mode For Zedboard... zz


    Hi,

    I am not be able to answer all your questions.

    But to start with I would suggest you to install Documentation Navigator, go to Design Hub View, Vivado 2013.4 Design hubs and start with Getting Started Section

    Install Vivado full edition along with Doc Nav from this link

    http://www.xilinx.com/support/answers/58485.html

    For Vivado Sysgen all documentation refer below link

    http://xgoogle.xilinx.com/search?output=xml_no_dtdie=UTF-8oe=UTF-8client=supportproxystylesheet=supportsite=Answers_Docsfilter=0resultsView=categorytab=dtnum=200sortBy=dateshow_dynamic_navigation=1sort=date%3AD%3AR%3Ad1documentClass=Docu...

    ISE is for all 4, 5, 6 and 7 series but have limited features for 7 series

    Vivado is only for 7 series and is enhanced tool with lot of features.

    If yourdesign iswith Zynq I would suggest to choose Vivado as going forward it will have all the enhancements and comparitively good support.

    ISE is supported but might not have any enhacements as no further releases are planned.

    For Matlab, HDL coder please vivit Mathworks site, I think you will find enough info

    Hope this helps

    Regards,

    Vanitha




    ---------------------------------------------------------------------------------------------Please do google search before posting, you may find relavant information.Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

  • RELEVANCY SCORE 2.82

    DB:2.82:Re: Hardware Co-Simulation - System Generator pj



    Respected

    Sir

    While implementing multirate filter I am facing the problem which I have attached with this mail(.bpm format). Please help me in this regard.

    Thanks in advance

    Shanoli










    Attachments:




    DB:2.82:Re: Hardware Co-Simulation - System Generator pj


    thanks a lot....my design is now working properly..

    Shanoli

  • RELEVANCY SCORE 2.82

    DB:2.82:The Advantages Of Using Chipscope Pro Analyzer With Jtag Hardware Co-Simulation 19



    Hi all,

    Can someone explain the advantages of Using ChipScope Pro Analyzer with JTAG Hardware Co-Simulation for the SysGen design? I can find some info in the SysGen user guide. But I cannot understand them well. Can you give me some

    example?

    Thanks.

    Best Regards.

    DB:2.82:The Advantages Of Using Chipscope Pro Analyzer With Jtag Hardware Co-Simulation 19


    Hi all,

    Can someone explain the advantages of Using ChipScope Pro Analyzer with JTAG Hardware Co-Simulation for the SysGen design? I can find some info in the SysGen user guide. But I cannot understand them well. Can you give me some

    example?

    Thanks.

    Best Regards.

  • RELEVANCY SCORE 2.81

    DB:2.81:Trouble With Modelsim 10 And Xilinx Libraries cz



    Hi,

    I am trying to run a simulation using ModelSim, but when I run startsim.do, I get these messages

    Loading work.local_max_tb(fast)# Loading work.fifo_1kx32(fast)# Loading unisims_ver.FDC(fast)# Loading unisims_ver.FDP(fast)# Loading unisims_ver.FIFO36E1(fast)# Loading work.sep_buf_x(fast)# Loading unisims_ver.FIFO18E1(fast)# Loading unisims_ver.FIFO36E1(fast__1)# Loading work.glbl(fast)

    and when I add the waves I do not see most of my signals

    I then tried adding the -novopt flag, but I get an error

    Failed to open lock file "/home/software/xilinx-13.2/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/unisims_ver/_lock" in create mode.# Permission denied. (errno = EACCES)

    Below is my startsim.do file

    --------------------------------------------

    # Create work libraryvlib work# Compile sourcesvlog "../hdl/reg_ff.v"vlog "../hdl/fifo_512x72.v"vlog "../hdl/fifo_512x32.v"vlog "../hdl/fifo_4kx32.v"vlog "../hdl/fifo_2kx32.v"vlog "../hdl/fifo_1kx32.v"

    .......

    .......vlog "lm_tb_new.v"vlog "$env(XILINX)/verilog/src/glbl.v"# Call vsim to invoke simulatorvsim -novopt -L work -L secureip -L unisims_ver -L xilinxcorelib_ver work.local_max_tb glbl# Add signalsdo wave.do# Run simulationrun -all---------------------------------------------

    My modelsim.ini points to 13.2 xilinx libraries at

    /home/software/xilinx-13.2/ISE_DS/ISE/verilog/mti_se/10.0c/lin64/

    Not really sure if there is an installation issue or something to do with my scripts. Any help will be appreciated.

    Thanks,

    Sid







    Solved!
    Go to Solution.

    DB:2.81:Trouble With Modelsim 10 And Xilinx Libraries cz


    Hi,

    1) Check the directory permissions for the compiled library directory.

    2) Try simulating any other example design and check if it works in Modelsim

    3) Check that the compiled libraries versions is same as the ISE tool version.

    Let me know the update after trying these steps.




    Thanks,AnirudhPS: Please MARK this is as an answer in case it helped resolve your query.Give kudos in case the post guided to the solution.

  • RELEVANCY SCORE 2.81

    DB:2.81:Problems With Hdl Co-Simulation!!!! s7



    Hi:

    everyone!

    There is a blackbox in my SystemGenerator model,and I think I have done the right setting of the blackbox block ,cause if I chose ISE simulator as the simulation mode, the whole simulation was OK. However,when I chose ModelSim as the simulator, there will be some errors listed as follows:

    An internal error occurred in the Xilinx Blockset Library.(reported by SystemGenerator)

    (imformation listed as follows in Transcript Window when ModelSim was compliling)

    # Model Technology ModelSim SE vcom 6.3c Compiler 2007.09 Sep 11 2007# -- Loading package standard# -- Loading package std_logic_1164# -- Loading package numeric_std# -- Compiling package conv_pkg# -- Compiling package body conv_pkg# -- Loading package conv_pkg# -- Compiling package clock_pkg# ** Error: ofdm_txrx_mimo_coded_cosim.vhd(1410): Library unisim not found.# ** Error: ofdm_txrx_mimo_coded_cosim.vhd(1411): (vcom-1136) Unknown identifier "unisim".# -- Loading package conv_pkg# ** Error: ofdm_txrx_mimo_coded_cosim.vhd(1416): VHDL Compiler exiting# ** Error: f:/Modeltech_6.3c/win32/vcom failed.# Executing ONERROR command at macro ./ofdm_txrx_mimo_coded_cosim_cw.tcl line 141

    The question is that why ModelSim would compile the VHDLmodules while my module included by blackbox is a verilog module? I mean the HDL file format in the directory is #.v not #.vhd, the ModelSim should do the verilog compiling .

    Version : ModelSim 6.3c ,Matlab 2008a ,ISE 10.1,SystemGenerator 10.1

    I had complied the library unsim and xilinxcore to ModelSim, and it was OK when I did simulation using ModelSim in other project.

    Please help!!

    DB:2.81:Problems With Hdl Co-Simulation!!!! s7


    Thank you again ! benchan.

    I think Xilinx should hire you as an employee !

  • RELEVANCY SCORE 2.81

    DB:2.81:Isim, Hardware Co Simulation f8



    Hello,

    I try to implement a hardware cosimulation, I work with a ML507 and ISE 13.1. At first, I use the JTAG Interface. I used UG817 as reference to put configuration for HW co-simulation in ISE.

    I have a little design composed by 2 main modules. I run HW co-simulation on the module which has many counters. The other module is composed by states machines (and not interessant).

    When I run ISIM, performances in HW co-simulation are worse than in a normal SW simulation... As I saw in other topics it seems HW co-simulation is very efficient when there are DSP. For my design whitout DSPs or DPRAMs, can I expect better performances with Hardware co-simulation or the fact that performances are worse is normal?

    I also would like to use Ethernet to improve (if possible) performances, can anyone indicate a tutorial to achieve that.

    Thanks a lot for your answer

    lamonnis

    DB:2.81:Isim, Hardware Co Simulation f8


    Hello,

    In fact I am a beginner with this functionnality, so, at first it seems very easy to use the JTAG interface and in UG817 it seems I can have performances with JTAG and incremental compilation. So if it is not the case, I will implement an Ethernet interface but I just found UG819 which is, i think, a bit complicated for my application.

    Do you know other tutorial which can help me?

    Thanks

    lamonnis

  • RELEVANCY SCORE 2.80

    DB:2.80:Hwicap Simulation Model Problem k3



    I am trying to simulate with HWICAP but I've ran into inconsistent library versions being called by the HDL model.

    The hwicap_wrapper.vhd calls xps_hwicap_v5_01_a library. However, the library model references v6_01_a model which is not available. How do I get around this problem?

    J

    DB:2.80:Hwicap Simulation Model Problem k3


    I am trying to simulate with HWICAP but I've ran into inconsistent library versions being called by the HDL model.

    The hwicap_wrapper.vhd calls xps_hwicap_v5_01_a library. However, the library model references v6_01_a model which is not available. How do I get around this problem?

    J

  • RELEVANCY SCORE 2.80

    DB:2.80:How To Increase The Simulation Speed Of Hw Co-Simulation 1j



    Hello,

    I am currently using HW Co-Simulation to speed up the simulation of a sysgen design. The design needs very long input samples to see the performance.

    Using HW Co-Simulation, the simulation speed increases about 8-10 times compared with that of a pure sysgen/simulink simulation, but I stillhave to wait for days to see the final performance.

    The evaluation board is ZC702 with the maximal clock of 100MHz.

    The input of this sysgen block is from matlab workspace repeatly using 100M samples of data. As the input needs to be sent to FPGA board by JTAG cable when HW Co-SImulation. At first, I think JTAG is the bottle neck, so I only use 16384 samples repeatly instead of the original 100M sapmles as the input and put them into FPGA ROM. Out of my expectation, the simulation speed is not increased.

    Later, I tried the free running clock instead of the single-step clock, but there is neither any improvement of simulation speed.

    I can understand why the speed is slow in free running clock mode. As in free running clock mode, FPGA is clocked from simulink.But why is the simulation speed the same infree-runningclock?

    Also, is there any other method to speed up the simulation speed?

    DB:2.80:How To Increase The Simulation Speed Of Hw Co-Simulation 1j


    Hi,

    this seems to be the worst case I/O situation for sysgen.

    An I/O happening on each cycle and also waiting for Matalb to perform the feedback operation.

    This means the hardware will be put on hold por every piece of data and I/O takes a lot of time compared to native FPGA speed.

    Your second approach seems to be better, still there's one question:

    Input and feedback happens inside the FPGA, but what's the role of sysgen then?

    If you still send back some data on each clock cycle there's not much gain.

    What you could try is to collect some data (e.g. Fifo, shared memory) and send bigger blocks back to the host system.

    This would allow the design to process data continuously for some time and then the accumulated data can be sent as a block which reduces the communication and synchronisation overhead.

    There are a few hints in the sysgen documentation abut such approaches. You need to find out what suits best for your system.

    Have a nice simulation

    Eilert

  • RELEVANCY SCORE 2.80

    DB:2.80:Generate Simulation Hdl Files 7c



    Hello!

    Im trying to generate the simulation HDL files for a project with EDK 10.1. First, I have tried to compile the simulation libraries using the GUI, but I ended up with many errors in the compilation :( when i try to generate the simulation HDL files i get the following error.. How can i fix this problem?

    thx in advance

    Faraj

    ERROR:MDT - Unable to locate the precompiled library microblaze_v7_10_d. The file C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\​microblaze_v7_10_d\hdl\vhdl \microblaze_types_pkg.vhd is distributed by Xilinx encrypted and will not be read by any simulator. Please use compedklib to setup the EDK precompiled libraries and provide the path to them using the -E switch.ERROR:MDT - Error while creating simulator compile scriptmake: *** [simulation/behavioral/system_setup.do] Error 1Done!

    DB:2.80:Generate Simulation Hdl Files 7c


    Hi,

    You can't perform the simulations with a lower version of ModelSIM, and I don't think you can do it with with Xilinx Version of ModelSIM.

    I think there are answer records that describe this too.

    Regards

    Lachlan.

  • RELEVANCY SCORE 2.79

    DB:2.79:Timing Constraints Getting Silently Dropped jd



    We seem to have encountered a bug in the tool flow where if you build things a certain way, timing constraints will get dropped such that static timing analysis passes, but postroute timing simulation shows setup/hold violations and the actual device will exhibit timing related bugs.

    This flow causes problems:

    1) build dsp core cdontaining multicycle paths with sysgen targeting hdl netlist

    2) synthesize core with ise using the generated project file (after disabling iobuf insertion)

    3) copy sysgen ucf file into larger fpga ucf file

    4) build larger fpga with other cores, etc.

    result will pass static timing but fail post route timing sim real world testing

    This flow will work:

    1) build dsp core cdontaining multicycle paths with sysgen targeting NGC netlist

    2) copy sysgen ucf file into larger fpga ucf file

    3) build larger fpga with other cores, etc.

    Note: if we build using the hdl netlist flow without doing an intermediate step of synthesizing the core, the tool bombs out complaining of problems with constraints. Apparently synthesizing the core causes the downstream build process to not notice these timing errors.

    Has anyone else noticed this sort of thing?

    Why does the sysgen HDL netlist compilation generate NGC netlists along with the vhd/v files? And why are these NGC files incompatible with the generated ucf file?

    -Jeff







    Solved!
    Go to Solution.

    DB:2.79:Timing Constraints Getting Silently Dropped jd


    Turns out that for some reason when in hdl mode, sysgen does not write timing constraint info, and the ise project that it creates is set to NOT write timing constraints through to the ncg netlist when synthesized. When in ngc mode, sysgen it does write the timing constraints. I've been told change request 575329 has been filed to address this issue.

  • RELEVANCY SCORE 2.79

    DB:2.79:Not Compiled Until The End Hdl Simulation Library For Modelsim 10.0c (64-Bit) In Ise 14.2 8c



    Not compiled until the end HDL Simulation Library for modelsim 10.0c (64-bit) in ISE 14.2. Процесс компиляции останавливается на одном и том же месте (смотри лог in Attachments ), процесс компиляции никогда не заканчивается.Необходимо только принудительній останов. Помогите пожалуйста










    Attachments:







    log.txt ‏1 KB

    DB:2.79:Not Compiled Until The End Hdl Simulation Library For Modelsim 10.0c (64-Bit) In Ise 14.2 8c


    Hello,

    I think the first place to start is that the supported Modelsim version 10.1. Versions in the 10.0 series have been seen to have issues with library compilation. Can you please try the newer release versions and see if the problem continues?

    OK, hope this helps,

    Scott

  • RELEVANCY SCORE 2.78

    DB:2.78:Can I Do Hardware Co-Simulation Using System Generator With Jtag Rather Than Pci? Can It Support Pcie? mf


    My computer is without PCI and only has PCIe interface. So if I want to do hardware co-simulation using system generator, do I only have to use JTAG? Does hardware co-simulation support PCIe?

    DB:2.78:Can I Do Hardware Co-Simulation Using System Generator With Jtag Rather Than Pci? Can It Support Pcie? mf


    The JTAG co-simulation is always possible if you have a JTAG header in your board. The PCIe co-simulation is not documented and Xilinx will provide a help only if you are a major compagny with an NDA. It's prety frustrating that Xilinx didn't make any effort to provide enough informations about their co-simulation other than the JTAG.

    For the JTAG, the main problem is that you can't get full speed and you can't perform burst transfers.

    I already tried to play with the boards provided with systeme generator, but they use an *.lna file that is a kind of netlist protected and with some informations about the chip used. So if the FPGA you are using didn't match the ones they provide you are done.

    Can any body give more information about this *.lna files????

    J

  • RELEVANCY SCORE 2.78

    DB:2.78:Hardware Co-Simulation Question c1



    hi,

    when i using hardware co-simulation shared memory(FIFO),there is a errer:

    Could not create shared memory. A shared memory with the name "BA_pipe" is already in use.

    This could be because another System Generator block is executing that is set to "own and initailize" a memory of this name. If you are using System Generator's shared memory C++ API directly, it could also be because you have started another process that has created a memory with this name.Error occurred during "Simulation Initialization".

    I don't know how to deal, so need help, please

  • RELEVANCY SCORE 2.77

    DB:2.77:Hdl Protection Or Encryption 9j



    Hi All,

    Guys I have 3 questions??

    1. Is there any application or command in xilinx ISE using which I can protect my HDL files (Both Verilog and VHDL) as per the IEEE standards (pragma protect , protect begin, ...etc)????. If so what is that and where can I get detailed documentation of these???

    2. I have tried with cadence ncprotect and could generate the encrypted hdl files. How Can I use these protected files in XILINX Environment??

    3. Can I use these protected HDL files for synthesis also or else they are just limited to simulation????

    Thanks Regards

    Sanjay :smileyhappy:

    DB:2.77:Hdl Protection Or Encryption 9j


    I'm also wondering the answer for these questions:)

    Can anyone help about that?

    Thanks.

  • RELEVANCY SCORE 2.77

    DB:2.77:Black Box In System Generator d1



    Hi

    I am tring to generate Systen Generator Black box for hardware co simulation using the hand writen VHDL code and using i in the system as below but the results are zero always unable to detect erroe can u plz let help me i am attachin my design and hdl code with the mfunction to this mail. In the code i am just tring take a matrix as input by taking one element per clock cycle in row major format and store the matrix in coloum major format in VHDL and send back the transposed matrix serially.

    Thanks and Regards

    teja




    Thanks and RegardsTeja

    DB:2.77:Black Box In System Generator d1


    Hi Teja,

    the coding problems are already answered in your other thread by now.

    For the modelsim problem, you should check how the two versions are installed in your system.

    Sysgen/Matlab probably just asks vsim to start and gets the first one found via the PATH variable.

    So you should ensure that for the specific toolchain (Libero vs. ISE/Sysgen) the PATH variable leads to the correct tool versions.

    Another possible solution might be to compile the Xilinx libraries for the Libero version of Modelsim.

    However this only works if Lattice has not created any brand dependent limitations in their provided Modelsim version.

    But it might be worth a try. Use the compxlib or cmpxlibgui script for that purpose.

    Have a nice simulation

    Eilert

  • RELEVANCY SCORE 2.77

    DB:2.77:Problem With Ip Cores Within A User Ip 87



    Hi, i have a problem with an user ip core which contains a xilinx ip core.

    Im using vivado 2014.2 and centos 6.5. I already read AR# 60975 but i still have problems:

    When i use my user ip i get the following synthesis error:

    [Synth 8-493] no such design unit 'blk_mem_gen_sum' [".../sources_1/ipshared/my-brand.com/MOD_SUM_v1_0/fafa9a0c/hdl/cmp_bram.vhd":99]

    I hope the following step by step plan helps reconstruct the problem:

    Creating the User IP:1. Create new Project (RTL - VHDL):1a. Add all HDL files to the project The HDL files are in a Subdirectory of the Project (UserIpDir\hdl). The HDL files are only added, not copied.1b. Add the Constraint files to the project The constraint files are only added, not copied.1c. Add the VC707 Board constraints2. IP Catalog - Block Memory Generator - Customize IP IP Location - (UserIpDir\hdl) Component Name - blk_mem_gen_sum Application dependent customization of Block Memory Generator3. OOC Module Runs for blk_mem_gen_sum Create Oputput Products OOC Synthesis OOC Implementation---------------------------- Backup Project Dir ----------------------------4. Instantiation Template used blk_mem_gen_sum Don't use Blackbox attributes added "work" to the instatiation "blk_mem_gen_sum_inst: entity work.blk_mem_gen_sum" Without "work" the following error occurs: [Synth 8-998] blk_mem_gen_sum is not a entity ["User_Ip/hdl/cmp_bram.vhd":93]5. Project Synthesis and Implementation Synthesis BRAM used: 0.00 % success Implementation BRAM used: 22.52 % success6. Tools - Create and Package IP... Package your current Project Include .xci files7. IP File Groups contains: VHDL Synthesis UserIP_Constraints (the files imported earlier) UserIP_HDL (the files imported earlier) hdl/blk_mem_gen_sum/blk_mem_gen_sum.xci VHDL Simulation UserIP_HDL (the files imported earlier) hdl/blk_mem_gen_sum/blk_mem_gen_sum.xci8. Package IP and Close ProjectUsing the User IP:1. Create new Project (RTL - VHDL):1a. Add the VC707 Dev. Board Constraint1b. Create Block Design2. Copy the User IP Project Directory into the new Project Directory (NewProjectDir\UserIpDir)3. Add User IP to Project3a. Project Settings - IP - Add Repository: NewProjectDir\UserIpDir3b. Add IP - Select User IP and add4. Add AXI Memory Mapped to PCIe (Include Shared Logic in Core)4a. Run connection automation4b. Make REFCLK and pcie_7x_mgt ports external5. Validate Design - Validation successful.6. Save Block Design6a. Generate Block Design.6b. Create HDL Wrapper Let Vivado manage wrapper and auto update7. Open Sources Panel and verify design sources: Synthesis design_1_USER_IP_0_0 design_1_USER_IP_0_0.vhd UserIP_Constraints (the files imported in User IP) UserIP_HDL (the files imported in User IP) blk_mem_gen_sum blk_mem_gen_sum_ooc.xdc blk_mem_gen_sum.vhd design_1_axi_pcie and other IP used in the test project design_1.vhd design_1_ooc.xdc Implementation8. Project Synthesis [Synth 8-493] no such design unit 'blk_mem_gen_sum' ["/mnt/Projects/Testing_Project/Testing_Project.srcs/sources_1/ipshared/my-brand.com/MOD_SUM_v1_0/fafa9a0c/hdl/cmp_bram.vhd":91] (This is the hdl where the instatiation template is used)Second Attemp to Create User IP from Backup Checkpoint:4. Instantiation Template used blk_mem_gen_sum Use Blackbox attributes added "work" to the instatiation "blk_mem_gen_sum_inst: entity work.blk_mem_gen_sum" Without "work" the following error occurs: [Synth 8-998] blk_mem_gen_sum is not a entity ["User_Ip/hdl/cmp_bram.vhd":93]5-6 [Identical to first attemp]7. IP File Groups contains: VHDL Synthesis UserIP_Constraints (the files imported earlier) UserIP_HDL (the files imported earlier) hdl/blk_mem_gen_sum/blk_mem_gen_sum.xci xilinx.com:ip:blk_mem_gen:8.2 NEW VHDL Simulation UserIP_HDL (the files imported earlier) hdl/blk_mem_gen_sum/blk_mem_gen_sum.xci xilinx.com:ip:blk_mem_gen:8.2 NEW8. [Identical to first attemp]Second Attemp to use User IP:1-6. [Identical to first attemp]7. Open Sources Panel and verify design sources: Synthesis design_1_USER_IP_0_0 design_1_USER_IP_0_0.vhd UserIP_Constraints (the files imported in User IP) UserIP_HDL (the files imported in User IP) blk_mem_gen_sum blk_mem_gen_sum_ooc.xdc blk_mem_gen_sum.vhd design_1_axi_pcie and other IP used in the test project design_1.vhd design_1_ooc.xdc Implementation8. Project Synthesis [Synth 8-493] no such design unit 'blk_mem_gen_sum' ["/mnt/Projects/Testing_Project/Testing_Project.srcs/sources_1/ipshared/my-brand.com/MOD_SUM_v1_0/fafa9a0c/hdl/cmp_bram.vhd":91] (This is the hdl where the instatiation template is used)

    What am i doing wrong, i would be pleased if anyone can help me.

    Regards,

    Andreas







    Solved!
    Go to Solution.

    DB:2.77:Problem With Ip Cores Within A User Ip 87


    Hi Deepika,

    thank your so much for your patience and help.

    My mistake was to instatiante as entity instead of component. Also i don't use the blackbox attributes now.

    The remaining error is related to a different problem where i am using a clock multiplexer / BUFGMUX to access logic alternating from two different clock domains. Thi leads to a construct where the input from the BUFGMUX is driven by the output of a BUFG, this should be avoided. (See BUFG Cascade / BUFG Cascade 2)

    I came to the conclusion that a fifo is a better solution for transfering data between the clock domains.

    Regards,

    Andreas

  • RELEVANCY SCORE 2.77

    DB:2.77:Hardware Co-Simulation Using Avnet Memec V4sx35 7x



    I'm trying to cosimulate with v4mb. dsp library for system generator is provided installed. However there is a problem with Generation JTAG Co-simulation. Anyone has tried HW Cosim/HTIL with Memec boards?

    DB:2.77:Hardware Co-Simulation Using Avnet Memec V4sx35 7x


    I'm trying to cosimulate with v4mb. dsp library for system generator is provided installed. However there is a problem with Generation JTAG Co-simulation. Anyone has tried HW Cosim/HTIL with Memec boards?

  • RELEVANCY SCORE 2.77

    DB:2.77:Post-Place Route Simulation Model j9



    Hi,

    I'm new with Xilinx software and I have got a question.

    I'm working with a project that include sub-module (hierarchical modules).

    I'm trying to made a post PR simulation with modelsim. I can generate the model top_module_timesim and .sdf.

    But, when I run my simulation, the result is not correct (flat signals). It seems that only the top_module is generate and not the sub-module.

    Indeed, when I add the HDL file from the sub-model in my simulation, the result is correct. But doing this, I didn't made a real post PR simulation (only for the top module). I went to have a complete PR model.

    Maybe it is only an option to check but I didn't found it.

    I hope you could help me, have a good day

    Ben







    Solved!
    Go to Solution.

    DB:2.77:Post-Place Route Simulation Model j9


    Hi,

    sorry, sometimes I forgot to take into account the jet lag and weekend (student live ;-) ).

    Actually, I forgot to check the keep hierarchy option for the synthesis. I did it only for the PR step. Maybe it is why the simulation model wasn't correct.

    Checking this option in both step give coherent results. Moreover the signals are expanded with the module/instance name.

    Thanks for your answer

  • RELEVANCY SCORE 2.76

    DB:2.76:Error:Mdt - File Not Found In Any Repository x1


    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/common_types_pkg.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/proc_common_pkg.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/conv_funs_pkg.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/ipif_pkg.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/addsub.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/counter_bit.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/counter.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/direct_path_cntr.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/direct_path_cntr_ai.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/down_counter.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/eval_timer.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/inferred_lut4.v'
    ERROR:MDT - File not found in any repository
    'proc_common_v2_00_a/hdl/verilog/ipif_steer.v'
    ERROR:MDT -

    im having the following error ,there is a solution

    Description
    Keywords: PAODuring the generation of simulation libraries, the following error occurs:"ERROR:MDT - File not found in any repository"The files are in the correct pcore directory and structure. How can I resolve this error?

    Solution

    This issue can occur when an underlying pcore library referenced in a pcore uses a different HDL language than the top-level HDL, and the underlying pcore's PAO does not specify an HDL type for each of the files. An example is the Verilog xcl_bfm core that uses the VHDL opb_ipif_v3_01_c library.When a library is used without an HDL specified, the tools use the same language as the parent pcore for the underlying library, which causes the tools to look in the wrong HDL directory for the source files.You can resolve this issue by using one of the following solutions:- Correct the underlying pcore PAO to specify a language for each HDL source file.- Change the parent pcore PAO to specify each underlying pcore HDL with a specified language for each source file instead of the usual "all" keyword.

    BUT I DONT KNOW HOW TO IMPLEMENT THIS SOLUTION...

    ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/common_types_pkg.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/proc_common_pkg.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/conv_funs_pkg.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/ipif_pkg.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/addsub.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/counter_bit.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/counter.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/direct_path_cntr.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/direct_path_cntr_ai.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/down_counter.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/eval_timer.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/inferred_lut4.v'ERROR:MDT - File not found in any repository 'proc_common_v2_00_a/hdl/verilog/ipif_steer.v'ERROR:MDT -

    DB:2.76:Error:Mdt - File Not Found In Any Repository x1


    There is a *.pao file for this design. Inside you should find lines like

    lib proc_common_v2_00_a counter.*

    you need to change this to

    lib proc_common_v2_00_a counter.vhd vhdl

    or

    lib proc_common_v2_00_a counter.vverilog

    to specifiy the language needed.

    See http://www.xilinx.com/support/documentation/sw_manuals/edk10_psf_rm.pdffor more explanation on this file and it's syntax.

    -R

  • RELEVANCY SCORE 2.76

    DB:2.76:Problem For The Simulation With Ncsim js



    Hi,

    I have a problem when I want to simulated my project with Ncsim. When I compile HDL SimulationLibraries, Xilinx shows an error:

    ERROR:CAEInterfaces:418 - COMPXLIB[env]: unable to automatically find simulator (ncsim) executables.

    What can I do to resolve this error ?

    My computer run windows XP

    Xilinx ISE Design Suite 10.1

    Cadence SPB 16.01

    Thank you very much

    DB:2.76:Problem For The Simulation With Ncsim js


    I have resolved the probleme. The compilator don"t like when the project name contains space.

  • RELEVANCY SCORE 2.76

    DB:2.76:Use Of Mig Tools Generated Hdl Files With Custom Memory Controller 33


    Hi

    I went through the following guide for PHY only Design
    http://www.xilinx.com/support/answers/51204.html

    It only gives the details of various interfacing signals between Memory Controller and PHY Core.

    But how do we use the generated HDL files from MIG for PHY only design. Else/otherwise does MIG have the option to generate HDL files for PHY only. And after the HDL files have been generated how do I go about their simulation.

    Best Regards
    Devendra






    Solved!
    Go to Solution.

    DB:2.76:Use Of Mig Tools Generated Hdl Files With Custom Memory Controller 33


    There is no option to generate a PHY-only design.phy_top.v is the top-level module for the PHY-Only design. For the exception of infrastructure and the XADC instantiation I believe the rest of the files can be removed. There is no simulation test bench for PHY-only but you can run the default example design simulation and then pull out the signals from phy_top.v to see how te interface works.

  • RELEVANCY SCORE 2.76

    DB:2.76:Filter Design Hdl Coder Or Fir Compiler? ja



    Hi there,

    I need some advice figuring out which way seems is the more efficient/flexible way to design a FIR Filter and integrate it into my existing design. Basically, I have two options:

    Option 1: Generating a filter using FIR compiler (coeffs by fdatool)

    Testbench: Generating signal input in MATLAB, writing filter_input file in MATLAB, executing HDL simulation (e.g. ISim) and reading it back to MATLAB, plotting filter output in MATLAB

    Advantage: full control and most features in FIR Compiler filter generation (e.g. multiple input signal using same filter)

    Option 2: Generating HDL code by Filter Design HDL Coder in MATLAB

    Testbench: automatically generated by HDL Coder

    Advantage automated testbench generation with a whole bundle of stimulus by HDL coder, automated integration in ISE project.

    It's kinda obvious that Option 2 should be the most flexible one by means of creating a testbench and validate the filter, generation of the testbench stimulus, Option 1 might be more efficient in terms of resource utilization and the broad range of features.

    What is in your opinion the "best" way to rapid prototype my filter and integrate it into my existing FPGA system? (Spartan-3A DSP)

    Thanks, Flo

    DB:2.76:Filter Design Hdl Coder Or Fir Compiler? ja


    I was not thinking of sysgen in Option 1 but actually exactly the same you described in your second paragraph.

    Basically, the fundamental question is which Options of both is the more efficient one in terms of HDL code generation.

    Can one assume that the resource utilization of a Xilinx core is the more efficient one? I am aware of that if I would asked that in a Matworks forum I would definitely get the answer that Filter Design HDL Coder is the better choice.

    But does anybody here has some objective experiences in both options?

  • RELEVANCY SCORE 2.75

    DB:2.75:Jtag Hardware Co-Simulation And Chipscope ac



    Hi all

    I have a question

    I am doing JTAG hardware Co-simulation with system generator and my board does not support ethernet co-simulation

    My question is

    Can I use chipscope while doing the co-simulation "i.e: use system generator and chipscope simultaneously"

    or system generator locks the JTAG and prohibits any other tool from using it

    note that chipscope also uses the JTAG

    Thanks

    DB:2.75:Jtag Hardware Co-Simulation And Chipscope ac


    Hi benchan,

    I have the same problem (using both Chipscope and JTAG cosimulation) . I followed your instructions (including the one regarding the boundary scan instruction), but it doesn't work. It looks like Chipscope analyzer, while waiting for the trigger, freezes during the cosimulation (therefore missing the triggering signal) and then unfreezes after the cosimulation has finished, and keeps waiting.

    I believe the problem is that in my version of System Generator (9.1) there's no "Share JTAG cable for concurent access" option, and so access to the bus is mutually exclusive. Do you think this can be the problem? If so, is there a solution (besides using Ethernet cosimulation)?

    Thank you!

  • RELEVANCY SCORE 2.75

    DB:2.75:Isim 13.1 Tcl Console Recompile With Standalone Gui mj



    I have been using Modelsim XE for several and my verification design flow is often as follows:

    Modify HDL sources
    Compile
    (Re-)start simulation
    Configure wave window
    Analyze waveform and assertions
    Goto 1.

    This could be done by calling a single user macro from interactive Modelsim tcl console.

    Is something similar possible using ISIM?

    Are there any tcl examples? I am especially interested in tcl-based recompilation of my HDL sources.

    Is it possible, that new "Relaunch" button only fits well for auto-generated simulation from ISE project navigator?

    DB:2.75:Isim 13.1 Tcl Console Recompile With Standalone Gui mj


    Hi,

    Unfortunately there is no Tcl way to do this, as you have to call the compiler inside the executable in order to get this feature to work. This is why when you click on the button, it kills the current engine invocation recompiles the files and loads up a new invocation. Thus since you have to kill it and the Tcl is inside the engine, this cannot work.

    That said, for your use case I cant see why you even need to do any of this.

    You can just write a script file to handle everything you are trying to do and just run that, without even opening up Project Navigator. The ISim UG, has examples on how to do this.

    http://www.xilinx.com/support/documentation/sw_man​uals/xilinx13_1/plugin_ism.pdf

    Just like in Modelsim XE, where you are writing Tcl to do this, you can do the same in ISim. The only difference is that ModelSim's engine invocation allows you to compile and elaborate inside the simulator. ISim has this as a two step process instead.

    Thanks

    Duth

  • RELEVANCY SCORE 2.75

    DB:2.75:Matlab/Simulink - Isim (Modelsim) Co-Simulation - How ? pd



    Hi all,

    I am wondering is there any way to do hdl co-simulation with Simulink + ISim?

    I know about the SystemGenerator, but I don't want to use it (commercial, too big/complex, eval. version is not an option for me, etc.).

    I need to perform some 'simple' co-simulation where my mathematical model is built in Simulink and some portion of the algorithm is built in Verilog HDL. Now I want to test this hdl module within Simulink.

    I'veonlyheard there was some possibility to do this with ModelSim XE, but newer versions of the ISE do not support it.

    So my question is: is there a way to co-simulate with Simulink + ISim? If not, can it be done with Simulink + ModelSim PE Student Version? Can you offer any clues for this with some very simple example?

    Thanks

    DB:2.75:Matlab/Simulink - Isim (Modelsim) Co-Simulation - How ? pd


    You can do this with using HDL-Verifier product from mathworks. With this product you can produce Modelsim block with using hand written or automatic generated hdl code.

    It initiate modelsim and wait for simulation. When you start simulation inputs from simulink send to modelsim and result send back to simulink.

    Also you can do FPGA in the loop simulation with HDL-coder product with supported board.

  • RELEVANCY SCORE 2.75

    DB:2.75:Microblaze 10.1 Verilog Simulation jf



    Hello all, I'm trying to perform a simulation of my Microblaze system. I am using ModelSim 6.3C on windows and I only have a Verilog license. I've followed all of the instructions in XPS. I've compiled the necessary ISE and EDK libraries for Verilog. In my Project Options under the "HDL and Simulation" tab I have the HDL set for Verilog (VHDL is grayed out anyway), the compiler script is set for ModelSim and I've chosen the Behavioral simulation model though I understand that according to the documentation, most of the cores will degenerate to structural.

    Now when I try to generate the HDL files for simulation using the "Simulation-Generate Simulation HDL Files" command, I get the following error in a dialog box:

    "EDK Sim Library: Currently selected HDL language is VHDL; the specified simulation library C:\Xilinx\10.1\edk_sim_lib\ was compiled with VERILOG"

    What gives? This doesn't make sense as my project options are set to Verilog and not VHDL. Do I just chalk this up as yet another one of the myriad XPS bugs?

    Jake

    DB:2.75:Microblaze 10.1 Verilog Simulation jf


    I just realized I had neglected to apply service pack 3 to my EDK installation. If that doesn't take care of the problem I'll try the 'simgen'. Thanks alot.

    Dan

  • RELEVANCY SCORE 2.75

    DB:2.75:Co Simulation (Chip Die And Package And Pcb Board) af



    Hello,

    Is it possible to perform the co simulation ( Chip Die and Package and PCB board) with HyperLynx?

    If not possible, what if uisng s-parameters extracted from the package and PC board?

    Thanks.

    DB:2.75:Co Simulation (Chip Die And Package And Pcb Board) af


    I have modeled the PCB, IC Package, and Die Capacitance information with S-Parameters before in HyperLynx. It is time consuming but it did work. I wish HyperLynx would allow you to assign package information in BoardSim when running decoupling or plane noise analysis.

    If you want to simulate the impedance like I have done above then you need to export the PCB and IC Package as separate S-Par models. Following this you need to connect them up in LineSim and place ports at whatever locations you wish to view the impedance. I had to add a SPICE model for the die capacitance (simple lumped capacitor model). You can use the capacitor model in HyperLynx if you want but you can't completely get rid of the parasitics that come with the capacitor, that's why I used a SPICE model.

    Then just export the entire setup as an S-Par model and then convert to a Z-parameter model if you wish.

    I also attached a current source (SPICE Model) to the die node to simulate gate switching and then measuring the ripple voltage on the PDN with the O-scope. Similarly you could attach a Sine source (SPICE - singular frequency) at a PDN node and measure the response at the die. This is useful for seeing how your system reacts to certain frequencies or harmonics in the time domain.

  • RELEVANCY SCORE 2.74

    DB:2.74:Edk Launch Hdl Simulator Error sk


    Hi, I am attempting to simulate a Microblaze design to test a custom peripheral. But in EDK, when I click on Generate Simulation HDL files, nothing happens. Also, when I click Launch HDL Simulator I get this error:"Simulation is supported only for top-level designs"My EDK project is a smaller part of a toplevel ISE design and I am guessing this is the problem? Does anyone have experience with this and know to fix it? Thanks,Mike Pratt



    Redefine Technologies, Inc

    DB:2.74:Edk Launch Hdl Simulator Error sk

    Thanks for your suggestions. I will see about simulating the toplevel ISE project. I also had some errors in my EDK design which may have been messing things up. Mike

  • RELEVANCY SCORE 2.74

    DB:2.74:Simulation With Mpmc ? p7


    Hi. How to simulate embedded system with program located in sdram (controlled by MPMC)? Should I get the hdl model of my sdram, connect to ports of MPMC and init it with the content of myprogram.elf file? Seems rather difficult. I'm on right way? Thanks!
    Message Edited by k-50 on 10-21-2009 11:08 AM

    DB:2.74:Simulation With Mpmc ? p7


    There're scripts provided in this app note http://www.xilinx.com/support/documentation/applic​ation_notes/xapp1003.pdf

    that can initialize the memory model with ELF.

    -Felix

  • RELEVANCY SCORE 2.74

    DB:2.74:Rtl Co-Simulation Of A Systemc Source Fails as


    Hi.

    I've successfully synthesized a SystemC code in vivado HLS. Now I want to make a RTL Co-Simulation (using systemc), but I have the following problems:

    - Two new inputs are created.

    - For outputs I use the definition sc_inbool, but in the synthesized code they are defined as sc_insc_lv1 . The types are not compatible, so it's not possible to run the simulation.

    Any ideas to solve this?

    Thanks for your help.

    DB:2.74:Rtl Co-Simulation Of A Systemc Source Fails as

    Hi.

    I've successfully synthesized a SystemC code in vivado HLS. Now I want to make a RTL Co-Simulation (using systemc), but I have the following problems:

    - Two new inputs are created.

    - For outputs I use the definition sc_inbool, but in the synthesized code they are defined as sc_insc_lv1 . The types are not compatible, so it's not possible to run the simulation.

    Any ideas to solve this?

    Thanks for your help.

  • RELEVANCY SCORE 2.74

    DB:2.74:Edk 13.4 Simulation Problem Of User Plb Peripheral 8d



    Hi all,

    I created an user peripheral as a slave of plb. In my peripheral, I have a user package and some FIFOs created Coregenerator. I successfully update my peripheral through "create or import peripheral.. " option. All vhdl files are compiled and FIFO's ngc file are copied to the local project and parsed in BDD file. Now, I want to run a simulatino in EDK with .elf installed in my microblaze to test my peripheral design but I got errors below:

    ERROR:HDLCompiler:104 - "C:/CZ/NoC_delta_EDK/EDK/Single_uBlaze_16K/pcores/bridge_noc_plb_v1_00_a/hdl/vhdl/user_logic.vhd" Line 61: Cannot find pkg_nocem in library bridge_noc_plb_v1_00_a. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.ERROR:HDLCompiler:69 - "C:/CZ/NoC_delta_EDK/EDK/Single_uBlaze_16K/pcores/bridge_noc_plb_v1_00_a/hdl/vhdl/user_logic.vhd" Line 111: arb_cntrl_word_in is not declared.ERROR:HDLCompiler:69 - "C:/CZ/NoC_delta_EDK/EDK/Single_uBlaze_16K/pcores/bridge_noc_plb_v1_00_a/hdl/vhdl/user_logic.vhd" Line 114: arb_cntrl_word_out is not declared.

    ........

    The "pkg_nocem.vhd" is a the package where I define user data types like "arb_cntrl_word_in", "arb_cntrl_word_out" and so on. I've copied them into the "pcores/hdl/vhdl/" of my peripheral file when updating it. How can I parse my package file and fifo's .ngc files into simulation compiler?

    Thanks in advance. I really appreciate your helps.

    DB:2.74:Edk 13.4 Simulation Problem Of User Plb Peripheral 8d


    I am also interested in this problem. The import peripheral wizard passes when I tell it to use a custom library (a homebrew serial interface), but fails in the same manner when attempting to build simulation files.

    -J

  • RELEVANCY SCORE 2.74

    DB:2.74:Problems Using Modelsim Xe To Do Co-Simulation With System Generator 7d



    Hi,

    I met a problem when trying to import verilog files into a black box and do co-simulation with System Generator. When I used ModelSim as the external simulator, an error occurs:

    # ** Error: try_verilog_cosim.vhd(1410): Library unisim not found.# ** Error: try_verilog_cosim.vhd(1411): (vcom-1136) Unknown identifier "unisim".# -- Loading package conv_pkg# ** Error: try_verilog_cosim.vhd(1416): VHDL Compiler exiting# ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed.# Executing ONERROR command at macro ./try_verilog_cosim_cw.tcl line 116

    My system generator is version 10.1 and my ModelSIM XE version is 6.3c with a starter license. I chose full verilog when installed MXE since I prefer to work with verilog than VHDL. I have also downloaded the precompiled library. As a result, I can find unisim_ver available in my library tab. (Unisim library is listed as unavailable.) As my design is done in Verilog and MXE is chosen as Verilog version, why is the tool looking for VHDL library-unisim instead of unisim_ver? I wrote a simple Verilog file and used MXE to simulate(without integrating with system generator), it worked fine and posted the correct waveform. Moveover, when I re-install MXE with VHDL installation, it can perform co-simulation with System Generator and shows the perfect waveform. (Of course, I imported some VHDL files into the black box at this time). I can also find VHDL library-unisim under path:\xilinx\vhdl\unisim; but all of the files are zipped. Do I have to unzip all of them manually? There are so many files. (Actually, all of the Verilog files under \xilinx\verilog\unisim_ver have been unzipped automatically...)

    I really prefer to work with Verilog. So could you tell me a way to do co-simulation with Verilog? I think maybe it's because I didn't configure the path of the library correctly.

    Thanks,

    Tan

  • RELEVANCY SCORE 2.74

    DB:2.74:Xapp1170 Matrix Multiplication: Not Able To Do C/Rtl Co-Simulation In Order To Verify Rtl Generated By Vivado Hls 3c



    Hi,I was trying to use xapp1170 (Hardware Accelerator for Matrix Multiplication) in one project on face recognition. I need matrix multiplication of rectangular matrices with large dimensions(like: 1x1665 and 1665 x 9). For this before going to SDK, i need to verify whether Vivado HLS generates accurate RTL. Thus I have to do C/RTL Co-simulation. For Co-simulation, I must have testbench that will call the function to be synthesized. What Xilinx provides with xapp1170 is self-checking program file (not a separate testbench), hence Co-simulation will not work here. So i need to make separate testbench. Here I am having problems. I tried to move main() in another file(testbench), but had errors. I also tried to use header files but efforts went in vain as I am not familiar with use of template in cpp. So if anyone helps me, I shall be highly grateful to him/her. Thanks in advance.







    Solved!
    Go to Solution.

    DB:2.74:Xapp1170 Matrix Multiplication: Not Able To Do C/Rtl Co-Simulation In Order To Verify Rtl Generated By Vivado Hls 3c


    Thank You for your kind reply. I started from scratch and wrote testbench as well as source. Now C/RTL simulation is working.

  • RELEVANCY SCORE 2.73

    DB:2.73:Simulink Hdl Coder Error k7



    I'm using DDS FFT in a Sys Gen mdl. Not able to generate HDL although simulation is working. Throws the following error.

    Error from hdlshared : dtconvertsl2pir: invaliddatatype

    Unknown data-type Fix_10_9 is the error.

    Any ideas?

    DB:2.73:Simulink Hdl Coder Error k7


    Update diagram (^+D) works.Simulation Passes shows intended results.

    Versions Sys Gen 11.1 Matlab R2008b

    DDS output (sine) Fix_12_11 is connected to input of FFT core (xn_re). should any component be added in between dds fft for compatible data types?

    For xn_im i'm giving input through constant(xilinx block) with signed (fix_12_11) as input.

  • RELEVANCY SCORE 2.73

    DB:2.73:Anyone Can Help Me To Fix That System Generator Error ! 7j



    Hi everyone !

    I'm using System Generator to design FIR filter for audio.

    I have ISE(System Generator) 14.6 and Matlab R2013a when generate with System Generator token.

    I have the same error with previous tools with ISE 13.2 and Matlab R2010a.

    Please have me to fix this error, i really want to generate HDL file and trying Hardware Co simulation.

    The error as below:

    INFO:encore:314 - Created non-GUI application for batch mode execution.

    INFO:sim:172 - Generating IP...Resolving generic values...

    WARNING:sim:597 - The parameter 'Sample_Frequency' is disabled and can't be set to any other value than '0.001'. Its value will be reset from '0.00100000000' to its last valid value '0.001'.

    WARNING:sim:597 - The parameter 'Clock_Frequency' is disabled and can't be set to any other value than '250.0'. Its value will be reset from '250' to its last valid value '250.0'.

    WARNING:sim:192 - Xco Parameter changed from (Sample_Frequency,0.00100000000) to (Sample_Frequency,0.001) during Recustomization.

    WARNING:sim:192 - Xco Parameter changed from (Clock_Frequency,250) to (Clock_Frequency,250.0) during Recustomization.Finished resolving generic values.Generating IP...

    WARNING:sim:472 - The chosen IP does not support a Verilog behavioral model, generating a Verilog structural model instead.XST: HDL CompilationXST: Design Hierarchy AnalysisXST: HDL AnalysisXST: HDL Synthesis

    ERROR:coreutil - Exception caught when running synthesis!

    ERROR:coreutil - Failure to generate output products

    WARNING:coreutil - WARNING: Default charset MS932 not supported, using ISO-8859-1 insteadERROR:coreutil - An error occurred while running Java. Please examine the console or CoreGen log file for a specific IP related error. For more information please search the Xilinx Answers Database for this error: http://www.xilinx.com/support

    ERROR:coreutil - XST has returned an error: coreutil:1012 - Command

    ERROR:sim - Error found during generation.ERROR:sim - Failed to generate 'fr_cmplr_v5_0_49918feee1962d15'. XST has returned an error: coreutil:1012 - CommandERROR:sim:877 - Error found during execution of IP 'FIR Compiler v5.0'










    Attachments:




    DB:2.73:Anyone Can Help Me To Fix That System Generator Error ! 7j


    This may or may not be the reason but based on the warnings message incorporated in the error section of your screenshot:

    WARNING: Default charset MS932 not supported, using ISO-8859-1 instead

    Try setting regional settings to English US on you PC or if using non-english characters in installation or project paths, remove these and use only English ISO-8859-1 characters.

    I hope this helps.

  • RELEVANCY SCORE 2.73

    DB:2.73:How To Integrate Xilinxblackbox In An Hdl-Coder Ise Project ? 1m


    Hey there

    I started a project using HDL Coder. As a few parts of my algorithms are not feasible with the HDL-Coder library, I have to use Xilinx' System Generator for those particular parts of the algorithm.

    For the simulation my algorithm works now, using both the System Generator and HDL-Coder library. The translation in VHDL succeeded as well for both tools. The configuration can be looked up in the attached project. I did take care of the following in particular:

    The signal names for HDL-Coder fit to the signal names in System Generator (ce, clk, ...). The timings are the same.

    Both System Generator and HDL-Coder create ISE-projects. As the major part of my project is translated by the HDL-Coder I use the ISE-Project generated by HDL-Coder and then add the sources generated by the System Generator.

    Now my question: no matter which sources I add (filename_cw.vhd, filename_cw.xise, ...) int the ISE environment, ISE is not able to put the project together nicely. I always have either sources outside of my project or (as I will explain neatly in the following section) the project reports some errors, I don't understand in this context.

    When I add the filename_cw.xise (for the project it is: ngc_netlist/systgenenerator_cw.xise), I get the error message when synthesizing: "structural is not an architecture body for systgenenerator_cw in library work."

    This is because ISE does not know the architectures "structural" yet, as it does not include the appropriate source when adding ngc_netlist/systgenenerator_cw.xise.

    I tried some time now to find the right combination of files I need to add to the ISE-Project, but I have failed so far.

    Anyone can help me putting this project together? :)

    thanks in advance pascal

    you can download the project here: http://www.datafilehost.com/download-3b13969f.html







    Solved!
    Go to Solution.

    DB:2.73:How To Integrate Xilinxblackbox In An Hdl-Coder Ise Project ? 1m


    Hallo,

    could you tell me why I do not have this options in HDL Code Generation - Block Propertise ? I also use matlab 2012, but cannot choose between architectures, I only have Module architecture ?

    Thanks

  • RELEVANCY SCORE 2.73

    DB:2.73:System Generator Meets Ngdbuild:604 - Logical Block dc



    Hi there,

    I'm testing a transmitter system written by myself (in Verilog HDL) in the Simulink environment by the help of System Generator. Here's what I've done:

    1: Write the HDL code, as I need a Block RAM module in my design, I generated the RAM block (blk_mem_gen_v4_1.v and blk_mem_gen_v4_2.v) by using Core Generator.

    2: Build a .mdl module in Simulink environment, add a Black Box in the module and then import the HDL code into the Black Box.

    3: Simulation results of the Black Box is correct.

    4: Generate the bitstream for Hardware Co-simulation by using System Generator block. The Synthesis tool is XST.

    Then during the XFLOW stage, I got the following warning and errors:

    Checking expanded design ...

    WARNING:NgdBuild:443 - SFF primitive

    'sysgen_hwcosim_iface/sysgen_dut/default_clock_driver_x0/xlclockdriver_1/clr_

    reg/has_latency.fd_array[1].reg_comp_1/fd_prim_array[0].rst_comp.fdre_comp'

    has unconnected output pin

    ERROR:NgdBuild:604 - logical block

    'sysgen_hwcosim_iface/sysgen_dut/test_ram_x0/black_box/time_domain/Block_ram'

    with type 'blk_mem_gen_v4_2' could not be resolved. A pin name misspelling

    can cause this, a missing edif or ngc file, case mismatch between the block

    name and the edif or ngc file name, or the misspelling of a type name. Symbol

    'blk_mem_gen_v4_2' is not supported in target 'virtex5'.

    ERROR:NgdBuild:604 - logical block

    'sysgen_hwcosim_iface/sysgen_dut/test_ram_x0/black_box/Pilot_Gard/Block_ram'

    with type 'blk_mem_gen_v4_1' could not be resolved. A pin name misspelling

    can cause this, a missing edif or ngc file, case mismatch between the block

    name and the edif or ngc file name, or the misspelling of a type name. Symbol

    'blk_mem_gen_v4_1' is not supported in target 'virtex5'.

    ERROR:NgdBuild:604 - logical block

    'sysgen_hwcosim_iface/sysgen_dut/test_ram_x0/black_box/clockdevider' with

    type 'clk_wiz_v1_5_test' could not be resolved. A pin name misspelling can

    cause this, a missing edif or ngc file, case mismatch between the block name

    and the edif or ngc file name, or the misspelling of a type name. Symbol

    'clk_wiz_v1_5_test' is not supported in target 'virtex5'.

    I have check some solutions, but still doesn't work.

    The software version is ISE 12.1 design suit. What kinds of problem and how should I solve these errors?

    Thanks a lot for all the help!

    DB:2.73:System Generator Meets Ngdbuild:604 - Logical Block dc

    Thanks for your information.I'm not just import the RAM in the black box, but the whole system, the RAM module is a component inside my HDL code.

  • RELEVANCY SCORE 2.72

    DB:2.72:The Problems About Building A Carry Chain In Spartan6 3f


    Hello.
    Now, I want to create a carry chain to measure time in Spartan6 xc6slx9. There are many carry chains CARRY4 in xcslx9, so I want to use CARRY4 to build a 128bits carry chains to measure time. And this plan can improve the precision of the measurement. But some problems arise.
    When CYINIT is '0', CI is '1', S(3:0) is “1111” and D(3:0)is “0000”, CO(3:0) should equal to "1111" and O (3:0) should equal to "0000" through to analyze the internal structure of CARRY4. And the results of the behavioral simulation are same to them. But the results of post-route simulation are that CO (3:0) equals to "0000" and O (3:0) equals to "1111", and the results are not same to them. At the beginning I don’t believe the results. Then I use the Chipscope to catch the result of CO and O, the results are same to the post-route simulation. The values of CO and O are not changed no matter what CI is ‘0’ or ‘1’, but it seems that CO and O can changed with CYINIT. Could you explain to me why is the result and where is my mistake?

  • RELEVANCY SCORE 2.71

    DB:2.71:Doubt Regarding Xapp1136 Document About Integrating Vfbc With Sysgen am



    Hi there :-)

    This question is in reference to the XAPP1136 document which talks about integrating the VFBC core with Sysgen.

    Suppose I import the EDK processor to Sysgen for HDL netlisting, is it also possible to implement the system or the

    document is only meant for co-simulation?

    If it is also meant for implementation then when I import the processor into Sysgen then does it import my software for the processor as well?

    What should I do if I am executing my software from an external flash?

    Please do answer my questions.

    Thank you :-)







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.70

    DB:2.70:Ddr Dq(S) Signals Hi-Z In Simulation cd



    I am using EDK9.2.02 and Spartan3E 1600e dev brd, I quickly created a edk microblaze design with only rs232 and mpmc ddr in order to see the activities on ddr dq and dqs, first I downloaded the design to s3e 1600e brd and from hyperterminal I have seen memory test pass which is expected, then I generated simulation HDL files and test bench and hooked-up the memory model from micron in my system_tb.vhd and add compile command in system.do, then invoke modelsim se 6.2b run for 1 ms, from the wave window, I saw signal MPMC_initDone went '1' a bit after 200 us which is good, however, the DDR_DQ and DDR_DQS were constant 'Z', I don't know if there is anything I am missing, pls advise.

    here is the steps I did for simulation:

    1)Project - Project Options - HDL and Simulation tab, tick 'Generate test bench template'.

    2)Simulation - Generate simulation HDL Files.

    3)In system_tb.vhd, declare ddr.v (from Micron) using vhdl syntax and hook it up with signlas from edk system.

    4)copy micron ddr model ddr.v and related files to project\simulation\behavioral.

    5) in system.do, add "vlog -incr -work work +define+x16 +define+FULL_MEM +define+sg6T "ddr.v" " before testbench compile command.

    6)invoke modelsim, execute do system_setup.do, then type C,S,W, there is no error or warnings when testbench was compiled.

    7) check wave window.

    yzca

    DB:2.70:Ddr Dq(S) Signals Hi-Z In Simulation cd


    Similar problem, but a little different.

    In ISE 13.4, simulating with ISIM, DDR2 controller wrapped in MPMC. Device = Spartan 6.

    DQS and DQS_N signals are X from the beginning of time and never change. Tracing down the hierarchy I see that they are driven by 2 primitives inside the controller: an iobuf and pulldown. The pulldown is the one driving 'X'. The iobuf has legal, non-Z inputs on its I and T ports and during (attempted) initialization when T toggles, the X on the net does not change.

    This is a VHDL design.

    I have done this before on another project with a Verilog top-level design and it worked fine! I even went back and re-ran my old simulation to see for certain and there was no similar problem.

    Things I've tried:

    - Run with and without DDR memory model in testbench

    - Run with and without additional "PULLDOWN" in the testbench

    - Run fuse specifying --timescape 1ps/1ps --override_timeunit and --override_timeprecision

    None of these have any effect.

    Help!!!!

  • RELEVANCY SCORE 2.70

    DB:2.70:Hdl Simulation Works, Post Synthesis Simulation Doesnt zx



    Dear all,

    I'm currently trying to use a statemachine to configure the clock IC on the VC709 eval board. The code is written in VHDL and has been implemented last year on a Spartan 6 and was tested successfully/worked in the hardware. I wrote a small testbench, supplying clock and reset signals, the rest comes from a small design with a I2C master component and a statemachine, that selects the registers to write.

    When I run a behavioural simulation, the output is as expected. Data is written on the outputs and the statemachine finishes with a flag set high.

    When I now synthesize the design and run a post synthesis functional simulation, I can see, that input data is created by the testbench correctly, but my statemachine is stuck even before the first data is send. I can also see different internal signals, that are marked red and with an X to show different driver forcing against each other, e.g. on a counter.

    I have never encountered such a big difference between HDL synthesis and synth/implementation result. The HDL hasn't been altered but now synthesized for a different FPGA and with newer tools. Can anyone point me in the right direction on how to debug this problem? I'm not quite sure where to start, since synthesis-tools are blackbox for me with not much to influence.

    Best Regards,

    Björn

    DB:2.70:Hdl Simulation Works, Post Synthesis Simulation Doesnt zx


    Hi,

    I checked the synth messages and there is no critical warning. There are 24 normal warnings about unused signals, which have been removed (unused RX related registers, since the FSM only writes data, and a not connected warning, since I have still the port in the top sheet, but doesn't use it in this reduced design). I can't identify a problem with these optimizations.

    I also deactivated the flatten_hierarchy feature and tried every option of the -fsm_extraction, without any changes in the simulation behavior, without any effect on the outcome.

    Any further ideas? I will read into ug901 to see, if any other options may be more convincing.

    Best Regards,

    Björn

  • RELEVANCY SCORE 2.69

    DB:2.69:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... xk


    hi,

    I wanted to simulate an ipcore with xps.
    I compiled the simulation libraries,
    then I generated simulation HDL files.

    but when I select the launch HDL simulator
    I enconter the following:

    make: nothing to be done for "simmodel'

    best regards

    DB:2.69:Hi, I Wanted To Simulate An Ipcore With Xps. I Compiled... xk

    The line means there is no change to your simulation files located in the simulation directory
    in your project directory.

    Try delete all the sim file gen by XPS and rerun lauch again.

  • RELEVANCY SCORE 2.69

    DB:2.69:Hls Co-Simulation Failed cs



    Hi,

    I'm using HLS co-simulating my project. But when I start co-simulation with verilog and VHDL, HLS returns the message "Failed to open tv file .../tv/rtldatafile/rtl.EAV_deinterleave.autotvout_​out_V_V.dat". It seems that HLS can not open a file?

    BR,

    wtiandong

    DB:2.69:Hls Co-Simulation Failed cs

    1. What is the Simulation tool option selected by you? Is it Modelsim? If its Modelsim, what happens if you use XSIM?2. What all options did you select: SystemC, VHDL, Verilog?3. If you select Setup, it generates lot of script files and under the sim "language" folder, sim.bat would be seen. Use this file and run simulation in command line by sourcing the .bat file



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.69

    DB:2.69:Vivado Hls Co-Simulation Fail c3



    Hi

    I am trying to run co-simulation for an HLS design.

    The process ends with an error from "ap_source":

    @I [SIM-14] Instrumenting C test bench ...
    @E [SIM-4] *** C/RTL co-simulation finished: FAIL ***
    command 'ap_source' returned error code
    while executing
    "source [lindex $::argv 1] "
    ("uplevel" body line 1)
    invoked from within
    "uplevel \#0 { source [lindex $::argv 1] } "

    @I [LIC-101] Checked in feature [HLS]

    I am using vivado 2013.4.

    I also have another vivado_hls (2013.2) installation in a different machine that works properly. :?

    Any idea on what's going on?

    DB:2.69:Vivado Hls Co-Simulation Fail c3

    Use the latest 2014.2 HLS and also refer to the AR above which covers simulation mismatch.



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.69

    DB:2.69:Simulation In Edk ks



    Hello,

    I am new in EDK and I am trying to simulate a PPC440 design.

    I have simulation libraries compiled and after doing Simulation Generate simulation HDL files, I choose Simulation Launch HDL simulator.

    I type c in ModelSim PE prompt in order to compile. However, the following error appears: # Cannot open macro file: system.do;

    Any idea?

    Thanks

    DB:2.69:Simulation In Edk ks


    Hello,

    I am new in EDK and I am trying to simulate a PPC440 design.

    I have simulation libraries compiled and after doing Simulation Generate simulation HDL files, I choose Simulation Launch HDL simulator.

    I type c in ModelSim PE prompt in order to compile. However, the following error appears: # Cannot open macro file: system.do;

    Any idea?

    Thanks

  • RELEVANCY SCORE 2.69

    DB:2.69:Difficulties In Simulating Without The Hdl File fd



    Hello,(I'm using ISE 10.1)I'm having some problems trying to simulate my design. I can't even create the Test Bench.My Top-Level Source Type is an NGC, created from Verilog. I can't use the Verilog file to create the TB, I only have access to the NGC files, along with some others.When I try to Create a New Source, the TB option isn't even there. If I change the Top Level Source Type to HDL I can create the TB Waveform, but it doesn't appear in my sources tab.What can I do to create a TB to the NGC file?OrWhat can I do to simulate a design without having the Verilog file?Thanks in advance,-Luis

    DB:2.69:Difficulties In Simulating Without The Hdl File fd

    Additional Info on .ngc simulation:http://www.xilinx.com/support/answers/45668.htm



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.69

    DB:2.69:Cip - Peripheral With Multiple M_Axi Busses sx



    Hi everybody,I have built an AXI microblaze-based SoC with Xilinx XPS 13.4 and I want to add a new peripheral with one S_AXI (slave) and multiple M_AXI (master) busses.Is that possible with CIP wizard ?If not, what about a manual HDL edit approach ? Which HDL project files should be edited for mplementation and simulation ?

    DB:2.69:Cip - Peripheral With Multiple M_Axi Busses sx


    Hi everybody,I have built an AXI microblaze-based SoC with Xilinx XPS 13.4 and I want to add a new peripheral with one S_AXI (slave) and multiple M_AXI (master) busses.Is that possible with CIP wizard ?If not, what about a manual HDL edit approach ? Which HDL project files should be edited for mplementation and simulation ?

  • RELEVANCY SCORE 2.69

    DB:2.69:Co-Simulation Failed zm



    Hi, I have a design in system generator that works fine when simulated in simulink alone, but when I generate the JTAG co-sim block for HW in the loop cosimulation the simulation results from this block are wrong.

    doesn't it suppose to be bit and cycle accurate with the simulink design?

    what could be the problem?

    DB:2.69:Co-Simulation Failed zm


    Hi,

    I have been using this approach of 'MATLAB+ISE Co-Simulation' 'Hardware Co-Simulation using System Generator'.

    From whatever my learning is,i would like to mension about the following points,

    (1)Are you using Black Box in your Design?

    If YES,then -- define ce along with clk as input?This does not give clk as an input in Black Box.it gets automatically sync with Simulink.e.g. For Verilog define-Input clk,ce;

    I think this will resolve problem regarding clock synchonization.

    (2)Use Wavescope from (Simulink Library - Xilinx Blockset - Tools)insert in your dsign,it will generate Testbench waveform like Timing diagram,when you run the simulation.The waveforms we want to see,the options can be found from its Menu Panel go to Nets - it will give options of I/Os you have defined,

    e.g. Gateway in -Input/Output

    Gateway out -Input/Output

    Select the points from this of which you wish to see the waves.

    This will enable you to see

    the inputs and outputs - your logic being exicuted according to the design of the Architecture(Serial or Pipelined Architecture)How many clock cycle is taken to exicute your design.

    I thinks this 2 points will help you in resolving your question "doesn't it suppose to be bit and cycle accurate with the simulink design?".

    I would be happy to have some opinions on the same,will enhance the learning by discussion.

    Regards,




    Vihang Naik

  • RELEVANCY SCORE 2.69

    DB:2.69:Microblaze 3.00.A In Edk 10.1 -- Problems With Simulation Library a8



    Hello,

    i have to take an verrrrry old edk-project (EDK 7.1) to EDK 10.1. I still want to use the microblaze v3.00.a. I take the files from an edk 8.2 installation in my pcores directory. So far so good.

    Generating the netlists works fine, but when i want to generate the simualtion hdl files, i get an error:

    ERROR:MDT - Unable to locate precompiled library microblaze_v3_00_a ...

    How can I tell EDK, that for this Core no compiled libraries are in the precompiled libraries?

    Thank you for your help!

    Kind regards,

    mcattack

    DB:2.69:Microblaze 3.00.A In Edk 10.1 -- Problems With Simulation Library a8


    Hello,

    i have to take an verrrrry old edk-project (EDK 7.1) to EDK 10.1. I still want to use the microblaze v3.00.a. I take the files from an edk 8.2 installation in my pcores directory. So far so good.

    Generating the netlists works fine, but when i want to generate the simualtion hdl files, i get an error:

    ERROR:MDT - Unable to locate precompiled library microblaze_v3_00_a ...

    How can I tell EDK, that for this Core no compiled libraries are in the precompiled libraries?

    Thank you for your help!

    Kind regards,

    mcattack

  • RELEVANCY SCORE 2.69

    DB:2.69:Ug871 C/Rtl Cosimulation Fail 1c



    Hello,

    I am doing the lab based on UG871, when C/RTL Co-Simulation, if choosing VHDL or Verilog HDL in "C/RTL Co-Simulation" -- "RTL Selection" menu, both HDLs are failed except for SystemC.

    Is there any body can explain why HDLs fail and is there any influence to final pcores generation which is written in Verilog HDL.

    Many thanks

    Lin

    DB:2.69:Ug871 C/Rtl Cosimulation Fail 1c

    When selecting System C, no external HDL simulator is needs as the tool uses the inbuilt System C compiler for this purpose. If Verilog or VHDL is selected, a 3rd party HDL simulator must be in the search path and a license available. This can be checked in the drop-down menu in the RTL Co-sim box. If System C passes then pretty much you can export RTL and implement it.



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.69

    DB:2.69:Hardware Co-Simulation , Non-Memory Mapped Ports j1


    hi,

    there is a question about non-memory mapped ports.

    I do a Hardware co-simulation compilation type with my hardware platform,and creat a A/D non-memory mapped ports. But when I generate code,and hardware simulation, I can't get the correct data from external signal.

    So is there anyone help me with this problem? thanks.

    DB:2.69:Hardware Co-Simulation , Non-Memory Mapped Ports j1


    Hi

    I am expecting you are using Jtag based custom boardHardware Co Simulation,

    "Not getting correct data " means ?

    Are you comparing simulink simulation against HW CO SIM results , if so wthat is clocking type ?

    It depends onsingle stepped or free running.

    Free running results may not match as Hardware runs asynchronoulsy with software simulation.

    Snapshots may be useful for better understanding.




    ---------------------------------------------------------------------------------------------Please do google search before posting, you may find relavant information.Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

  • RELEVANCY SCORE 2.69

    DB:2.69:Problem With Generating Hdl Simulation Files 9z



    I am using EDK 10.1.03 and modelsim_pe_edu_6.5a. After compiling the simulation libraries i tried to generate the hdl simulation file doe my design. i get the following error:

    alid architectures are:ERROR:Portability:90 - Command line error: Unexpected argument[20] "Abdo/simlib/EDK10.1.03_mti_se_nt/EDK_Lib/" found. aspartan2e aspartan3 aspartan3a aspartan3adsp aspartan3e qrvirtex qrvirtex2 qrvirtex4 qvirtex qvirtex2 qvirtex2p qvirtex4 qvirtexe spartan2 spartan2e spartan3 spartan3a spartan3adsp spartan3e virtex virtex2 virtex2p virtex4 virtex5 virtexemake: *** [simulation/behavioral/system_setup.do] Error 1Done!

    Any responses will be much apreciated.

    Cheers,

    Omar







    Solved!
    Go to Solution.

    DB:2.69:Problem With Generating Hdl Simulation Files 9z

    Turns out folder names in the libraries path cannot contain space characters

  • RELEVANCY SCORE 2.69

    DB:2.69:Hardware Co-Simulation With Xilinx Vertex Ii Pro Xc2vp30 33



    Hello,

    Can somebody tell me how to do hardware co-simulation with Xilinx Vertex II Pro XC2VP30?

    The exact device I have is Xilinx Vertex II Pro XC2VP30 FFG896CGBO649.

    I cannot see this board under hardware co-simulation in XSG.

    The version of XSG is 10.1.03.

    DB:2.69:Hardware Co-Simulation With Xilinx Vertex Ii Pro Xc2vp30 33


    The SysGen User Guide should be able to help you out. Check out the "Using Hardware Co-Simulation" section.

    http://www.xilinx.com/support/documentation/sw_man​uals/sysgen_user.pdf

    -Chris