• RELEVANCY SCORE 4.09

    DB:4.09:Edk Compiling And Building Problem zs





    hi everyone,

    can any one tell me abt how to fix these errors as i click to build the project in edk or i try to generate libraries

    "There appears to be a conflict in the Cygwin DLLs loaded in memory. Please close all Cygwin-based programs, and launch EDK Shell again"

    urgent help required

    how to remove this error?

    which programs are cygwin-based programs and how to detect them

    Thanks in advance







    Solved!
    Go to Solution.

    DB:4.09:Edk Compiling And Building Problem zs


    thank god i have solved this problem.

    i just changed my antivirus bitdefender internet security to game mode and edk started to respond.

    Now i am happy and playing with edk.

  • RELEVANCY SCORE 3.54

    DB:3.54:Ise9.1 Invoked By Edk 9.1 To Compile Sim Lib Fail fk




    Hi, everyone,

    My ISE version is ISE9.1i and EDK version is EDK9.1.02

    when I compile sim lib in EDK, I found one bugs.

    Compiling ISE lib coundnt complete, the processing go to 100% within 1 minute, and report 1 error.

    then EDK compiling goon and reports lots of errors.

    This bug is also found in previous version ISE8.2.03 and EDK 8.2.02

    Counld someone help me solve out the problem or provide some clues?

    Thanks a lot !

    DB:3.54:Ise9.1 Invoked By Edk 9.1 To Compile Sim Lib Fail fk

    Thanks a lot to xiaofeip and gtze,

    My problem is solved with their help.

    I adopt the second method of

    Answer Record:
    24097

    and my ISE version is 8.2.03 and EDK version is 8.2.02

  • RELEVANCY SCORE 3.35

    DB:3.35:Problem With Edk 11.4 New System Builder Tutorial ....No System.Xms File Generated k8





    Hi,

    Has anybody tried the 11.4 EDK tutorial (Take a Test drive build a new Embedded Project!) for building a new

    Microblaze project ? After the ISE stage, going into the XPS i get an error message: "no system.xmp file found".

    Is this OK....? If not what is the problem and how to solve it ?

    Thanks, Barry

    DB:3.35:Problem With Edk 11.4 New System Builder Tutorial ....No System.Xms File Generated k8


    Hello.

    Are you able to run XPS EDK in standalone mode without any errors.

    Also check your environment variable settings for ISE and EDK.

    For environment variable settings search the forum and you will find it somewhere.




    Best of luck.--Unlimited in my Limits.

  • RELEVANCY SCORE 3.35

    DB:3.35:Creating A Software Library Using Edk Shell? 8d



    Hi,

    I am developing an application to run on the PPC405 in the XC4FX12. I have the main application built and working using the Platform Studio SDK, and it builds and runs fine.

    I want to use the libYAML library available from here:

    http://pyyaml.org/wiki/LibYAML

    Using the bash shell and cygwin, I can build a library that I can link in to win32 console applications built using gcc and cygwin, which I have used to build up a test app .exe file.

    I want to build a ppc library that I can link in to the app I'm building on the SDK.

    The library builds using the usual ./configure, make, make install.

    When I run ./configure from the EDK Shell, it uses the gcc in i686-pc-cygwin

    I tried to set it to use the cross compiler with the following commends:

    export ARCH=ppc export CROSS_COMPILE=ppc-4xx export CC=powerpc-eabi-gcc

    and I get:

    $ ./configure checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for gawk... gawk checking whether make sets $(MAKE)... yes checking for gcc... powerpc-eabi-gcc checking for C compiler default output file name... configure: error: C compiler cannot create executables See `config.log' for more details.

    Looking in config.log it APPEARS the problem is:

    configure:2804: checking for C compiler default output file name configure:2831: powerpc-eabi-gcc conftest.c 5 /cygdrive/c/Xilinx/10.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: cannot find boot.o collect2: ld returned 1 exit status

    I get the same error if I write a hello world app and try to compile it using

    powerpc-eabi-gcc main.c

    I tried just building an SDK project and compiling the source files for the library directly, but the configure script sets a whole bunch of defines that I don't think I can guarantee setting up the eclipse project the way the configure file is set up.

    So how do you set up the EDK Shell to cross compile libraries managed using ./configure?

    Thanks

    Glenn

    DB:3.35:Creating A Software Library Using Edk Shell? 8d


    And solved the linking. Need to specify libyaml, not libyaml.a, or just yaml as stated in AR #31256

    Thank you for your help!

    Glenn

  • RELEVANCY SCORE 3.31

    DB:3.31:Using Leon3 Inside Edk 9f



    Hello,

    I have a problem with EDK. I am trying to import a LEON3 processor to use it as a EDK core. It will be connected through two FSL buses bridging the AMBA bus.

    The problem is the way the LEON3 processor is described. It uses several VHDL libraries that I dont know how to map in the PAO file.

    Has anyone did something similar and can give me some tips?

    Thank you

    Javier

    DB:3.31:Using Leon3 Inside Edk 9f


    Hi Javier,

    The trick is to make all of those HDL libraires EDK pcores too. You just need to provide a PAO file for those libraries though.

    Use any libraries provided with EDK for a reference, such as "proc_common" library from EDK \hw directory.

    -Felix

  • RELEVANCY SCORE 3.19

    DB:3.19:Integration Of Edk And Ise ap


    DB:3.19:Integration Of Edk And Ise ap


    Hi,

    If your application is in external memory, you need to use XMD to download the elf.

    1,Once the bitstream is downloaded onto the FPGA, do Debug = XMD Debug Options.

    2,Click OK to accept the settings.

    3, Debug = Launch XMD. You should be able to see a window as shown in 32 of the tutorial.

    4, Navigate to folder using "cd" option in XMD console.

    5, Use "dow executable.elf" and then "run" in XMD console.

    If your hyperterminal settings are proper you should be able to run the application

    Thanks




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 3.16

    DB:3.16:Segmentation Fault When Compiling Design ad



    Hi, Im using EDK 10.1.03 (lin64) I added a periphal and deleted and old one from my design however when i try to generate bitstream now i get the following error

    make: *** [implementation/system.bmm] Segmentation faultDone!

    Ive been back through the messages and no other errors are shown. What could cause this to happen?

    Many Thanks

    Michael







    Solved!
    Go to Solution.

    DB:3.16:Segmentation Fault When Compiling Design ad


    Turns out it was purely a problem with my mpd file, the tristate outputs were not properly setup.

    Michael

  • RELEVANCY SCORE 3.12

    DB:3.12:Debug Mode Problem d8



    Hello Everyone

    I have a ml402 evaluation board. It was working fine in my older desktop pc, recently i changed my pc and installed edk and ise softwares. But now i have problem withrunning indebug mode. In sdk i m compiling my sw application, programming hardware. Everything is ok but when i try to run the sw application in debug mode sdk is freezing and doesnt answer. What could be the problem? Will be very thankfull to the one who will help me since i m trying to solve this problem for some days and couldnt succeed...

    DB:3.12:Debug Mode Problem d8


    Hello Everyone

    I have a ml402 evaluation board. It was working fine in my older desktop pc, recently i changed my pc and installed edk and ise softwares. But now i have problem withrunning indebug mode. In sdk i m compiling my sw application, programming hardware. Everything is ok but when i try to run the sw application in debug mode sdk is freezing and doesnt answer. What could be the problem? Will be very thankfull to the one who will help me since i m trying to solve this problem for some days and couldnt succeed...

  • RELEVANCY SCORE 3.12

    DB:3.12:Problem Building Project In Sdk 9p



    Hi,

    I am compiling Xilkernel program with SDK of ISE 14.4. When I build the project, it often happens that the compilation is stuck at some point and never goes on. I have to close SDK and reopen it to build the project again. Its kind of annoying at times. Anyone experiencing the same problem or any solutions to this problem ?

    regards,

    Paul

    DB:3.12:Problem Building Project In Sdk 9p


    p,

    Yes we have our own java in the release that SDK must have a variable set in order to go find (and use).




    Austin LeseaPrincipal EngineerXilinx San Jose

  • RELEVANCY SCORE 3.09

    DB:3.09:Sdk/Edk 14.3 Cannot Compile Bsp Package ds


    After successful went thought the design flow on XPS 14.3, I export the design to SDK 14.3. I created a BSP project for standalone_bsp_0. But it compiled with errors. Would anyone point me to how to fix the errors. I am working on ML510 board and PPC440. The Xilinx application version is 14.3.

    make -k all
    libgen -hw ../ml510_dual_vxworks_ppc440_14_hw_platform/system​.xml\
    \
    -pe ppc440_0 \
    -log libgen.log \
    system.mss
    libgen
    Xilinx EDK 14.3 Build EDK_P.40xd
    Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../ml510_dual_vxworks_ppc440_14_hw_platform/system​.xml
    -pe ppc440_0 -log libgen.log system.mss

    Staging source files.
    Running DRCs.
    Running generate.
    XPS_BRAM_IF_CNTLR_1 not connected

    DDR2_SDRAM_DIMM1 not connected

    Running post_generate.
    Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
    "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440 -O2 -c"
    "EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
    "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440 -O2 -c"
    "EXTRA_COMPILER_FLAGS=-g"'.
    "Compiling common"
    powerpc-eabi-ar: creating ../../../lib/libxil.a
    "Compiling llfifo"
    "Compiling lldma"
    "Compiling dma"
    "Compiling standalone"
    "Compiling lltemac"
    "Compiling llfifo"
    "Compiling iic"
    "Compiling gpio"
    "Compiling pci"
    "Compiling uartns550"
    "Compiling spi"
    "Compiling sysace"
    "Compiling bram"
    "Compiling intc"
    "Compiling tft"
    xtft.c: In function 'XTft_GetPixel':
    xtft.c:368: error: expected ')' before ';' token
    xtft.c:370: error: expected ';' before '}' token
    make[1]: *** [libs] Error 1
    "Compiling cpu_ppc440"
    ERROR:EDK:369 - make failed for target "libs"
    ERROR:EDK:3418 - Error(s) while running make.
    make: *** [ppc440_0/lib/libxil.a] Error 2
    make: Target `all' not remade because of errors.

    DB:3.09:Sdk/Edk 14.3 Cannot Compile Bsp Package ds


    I looked at the code. It is missing the ')". Xilinx did not test before shipped the product.

    Thanks,

  • RELEVANCY SCORE 3.05

    DB:3.05:Compile Simulation Libraries + Modelsim Pe 3k


    Hello,
    I’ve got two problems.
    1.) If I compile my Simulation Libraries (XPS = Simulation = Compile Simulation Libraries), the compiler will have an error in compiling EDK Simulation Files.
    Reinstall of ISE and EDK didn’t solve the problem.
    The LogFile shows:
    Compiling chipscope_plbv46_iba_v1_01_a
    ERROR:: Cannot locate library chipscope_plbv46_iba_v1_01_a
    ERROR:: File implied by chipscope_plbv46_iba.vhd in logical library chipscope_plbv46_iba_v1_01_a in PAO file C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores/​chipscope_plbv46_iba_v1_01_a/data/chipscope_plbv46​_iba_v2_1_0.pao not found.
    2.) In the past, the simulation with verilog worked. Now, there is the error in Modelsim:
    # ** Error: (vish-4014) No objects found matching 'system_tb/dut/ppc405_0/ppc405_0/PPC405_ADV_i/PPC4​05_ADV_i/IPPC405_SWIFT/I1/GPR0'.

    The simulation with vdhl never worked. There is always the error:
    # ** Error: invalid command name "lmcwin"
    # Error in macro ./ppc405_0_regstd_wave.do line 14
    # invalid command name "lmcwin"
    # while executing
    # "lmcwin enable /system_tb/dut/ppc405_0/ppc405_0/PPC405_ADV_i/PPC4​05_ADV_i/ppc405_adv_swift_bw_1/ppc405_adv_swift_in​st/GPR0"
    # ("eval" body line 1)
    # invoked from within
    # "eval lmcwin enable $tbpath${ps}ppc405_0${ps}ppc405_0${ps}PPC405_ADV_i​${ps}PPC405_ADV_i${ps}ppc405_adv_swift_bw_1${ps}pp​c405_adv_swift_inst${ps}GPR0"
    Best regards,
    Michi
    EDK 10.1.01
    ISE 10.1.01
    Modelsim PE 6.3g
    BFM 10.1.1
    WinXP

    DB:3.05:Compile Simulation Libraries + Modelsim Pe 3k


    Hi,

    Since the problem only occurs when using the test bench, I would suspect that the hierarchy of the register might not be correct.

    I would suggest you remove the do file for the ppc register from the system_wave.do file and have the simulation run successfully without loading the registers.

    Then check the hierarchy of the register with modelsim and see if it matches the path that was shown in the error message.

    -XF

  • RELEVANCY SCORE 3.02

    DB:3.02:Use Ise Generated Ip Cores In Edk a7



    I have generated a mahtematical IP core in ISE, now I want to use it in EDK, ( it is not available in EDK IP list ),

    I know how to use a custom IP core in EDK but I have problem with ISE generated IP CORE, because I dont know which file to use in EDK. how to use ngc file in EDK? there are also verilog and vhdl file in ISE generated IP directory but it is said that they are just for simulation so I did not used them in EDK.

    thanks

    DB:3.02:Use Ise Generated Ip Cores In Edk a7


    Problem solved!

    I did every thing step by step according to link which I mentioned above,

    I put ngc file in correct place and.....yesterday I had EXACTLY the same problem, it said that "Couldnot find module/primitiv....",

    just change the wrapper of ngc file from verilog to VHDL!!

    see edk library like C:\Xilinx\12.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\​pcores\apu_fpu_v3_10_a

    and make your file exactly like that, there are some "attribute" after component declaration, I guess they are mandatory.

    tell me your progress

  • RELEVANCY SCORE 3.02

    DB:3.02:Problem Compiling Code On Edk 11.4 am



    Hi,

    I got a new machine which has windows xp 32bit on it. Installed Xilinx ISE 11.4. When I try to compile my design in EDK it stops at one point and doesnt move forward (doesnt compile fully). It doesnt even show any error and the little blue wheel on the lower right corner keeps on rotating. Also, I compiled the same code on my old computer. It compiled successfully.

    Last few lines in the console where it got struck:

    *********************************************Running Xilinx Implementation tools..*********************************************xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngcRelease 11.4 - Xflow L.68 (nt)Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise../__xps/ise/system.ise system.ngc PMSPEC -- Overriding Xilinx file C:/Xilinx/11.1/EDK/virtex5/data/virtex5.acdwith local file c:/Xilinx/11.1/ISE/virtex5/data/virtex5.acd.... Copying flowfile c:/Xilinx/11.1/ISE/xilinx/data/fpga.flw into workingdirectoryC:/Development/IMS_TOF/IMSTOF_DataACQ_V2_NoChipsco​pe_long7_mry_monitor_1_1024/implementation Using Flow File:C:/Development/IMS_TOF/IMSTOF_DataACQ_V2_NoChipsco​pe_long7_mry_monitor_1_1024/implementation/fpga.flw Using Option File(s): C:/Development/IMS_TOF/IMSTOF_DataACQ_V2_NoChipsc​ope_long7_mry_monitor_1_1024/implementation/xflow.opt

    Dont know what to do. Please let me know if any one has any suggestion.

    Thanks,

    Bhuvan







    Solved!
    Go to Solution.

    DB:3.02:Problem Compiling Code On Edk 11.4 am


    Finally, found solution for this problem.

    http://www.xilinx.com/support/answers/35351.htm

    Bhuvan

  • RELEVANCY SCORE 3.01

    DB:3.01:Problems Building A Set Of Libraries jf


    Hello,I am trying to build a set of libraries for a 3D visualization package called vtk using VC++ 6.0. I am using a centrino duo xp system with swap space set to 2000 MB. The compiler seems to freeze in attempt to link and build the a library called vtkzlib. At this point the CPU utilization drops to zero. Below is a copy of the compiler output leading up to the freezing point. I am not sure whether this is a vtk or a vc 6.0 issue. Does anyone know what is causing this or can point me in the right direction into solving this problem?Thank you,Daina--------------------Configuration: vtkGraphics - Win32 Debug--------------------Compiling...vtkAppendFilter.cxxvtkAppendPolyData.cxxvtkApproximatingSubdivisionFilter.cxxvtkArrayCalculator.cxxvtkArrowSource.cxxvtkAssignAttribute.cxxvtkAttributeDataToFieldDataFilter.cxxvtkAxes.cxxvtkBandedPolyDataContourFilter.cxxvtkBlankStructuredGrid.cxxvtkBlankStructuredGridWithImage.cxxvtkBoxClipDataSet.cxxvtkBrownianPoints.cxxvtkButterflySubdivisionFilter.cxxvtkButtonSource.cxxvtkBSPCuts.cxxvtkBSPIntersections.cxxvtkCellCenterDepthSort.cxxvtkCellCenters.cxxvtkCellDataToPointData.cxxGenerating Code...Compiling...vtkCellDerivatives.cxxvtkCleanPolyData.cxxvtkClipDataSet.cxxvtkClipPolyData.cxxvtkClipVolume.cxxvtkConeSource.cxxvtkConnectivityFilter.cxxvtkContourFilter.cxxvtkContourGrid.cxxvtkCubeSource.cxxvtkCursor3D.cxxvtkCutter.cxxvtkCurvatures.cxxvtkCylinderSource.cxxvtkDashedStreamLine.cxxvtkDataObjectToDataSetFilter.cxxvtkDataSetSurfaceFilter.cxxvtkDataSetToDataObjectFilter.cxxvtkDataSetTriangleFilter.cxxvtkDecimatePro.cxxGenerating Code...Compiling...vtkDelaunay2D.cxxvtkDelaunay3D.cxxvtkDicer.cxxvtkDiscreteMarchingCubes.cxxvtkDiskSource.cxxvtkEdgePoints.cxxvtkElevationFilter.cxxvtkEllipticalButtonSource.cxxvtkExtractCells.cxxvtkExtractDataOverTime.cxxvtkExtractEdges.cxxvtkExtractGeometry.cxxvtkExtractGrid.cxxvtkExtractPolyDataGeometry.cxxvtkExtractRectilinearGrid.cxxvtkExtractTensorComponents.cxxvtkExtractUnstructuredGrid.cxxvtkExtractVectorComponents.cxxvtkFeatureEdges.cxxvtkFieldDataToAttributeDataFilter.cxxGenerating Code...Compiling...vtkGeometryFilter.cxxvtkGlyph2D.cxxvtkGlyph3D.cxxvtkGlyphSource2D.cxxvtkGraphLayoutFilter.cxxvtkGridSynchronizedTemplates3D.cxxvtkHierarchicalDataSetGeometryFilter.cxxvtkHedgeHog.cxxvtkHierarchicalDataExtractDataSets.cxxvtkHierarchicalDataExtractLevel.cxxvtkHierarchicalDataLevelFilter.cxxvtkHull.cxxvtkHyperStreamline.cxxvtkIdFilter.cxxvtkImageDataGeometryFilter.cxxvtkImageMarchingCubes.cxxvtkImplicitTextureCoords.cxxvtkInterpolateDataSetAttributes.cxxvtkInterpolatingSubdivisionFilter.cxxvtkKdNode.cxxGenerating Code...Compiling...vtkKdTree.cxxvtkLineSource.cxxvtkLinearExtrusionFilter.cxxvtkLinearSubdivisionFilter.cxxvtkLinkEdgels.cxxvtkLoopSubdivisionFilter.cxxvtkMarchingContourFilter.cxxvtkMarchingCubes.cxxvtkMarchingSquares.cxxvtkMaskFields.cxxvtkMaskPoints.cxxvtkMaskPolyData.cxxvtkMassProperties.cxxvtkMergeDataObjectFilter.cxxvtkMergeCells.cxxvtkMergeFields.cxxvtkMergeFilter.cxxvtkMeshQuality.cxxvtkModelMetadata.cxxvtkOBBDicer.cxxGenerating Code...Compiling...vtkOBBTree.cxxvtkOutlineCornerFilter.cxxvtkOutlineCornerSource.cxxvtkOutlineFilter.cxxvtkOutlineSource.cxxvtkParametricFunctionSource.cxxvtkPlaneSource.cxxvtkPlanesIntersection.cxxvtkPlatonicSolidSource.cxxvtkPointDataToCellData.cxxvtkPointsProjectedHull.cxxvtkPointSource.cxxvtkPolyDataConnectivityFilter.cxxvtkPolyDataNormals.cxxvtkPolyDataStreamer.cxxvtkProbeFilter.cxxvtkProgrammableAttributeDataFilter.cxxvtkProgrammableDataObjectSource.cxxvtkProgrammableFilter.cxxvtkProgrammableGlyphFilter.cxxGenerating Code...Compiling...vtkProgrammableSource.cxxvtkProjectedTexture.cxxvtkQuadricClustering.cxxvtkQuadricDecimation.cxxvtkQuantizePolyDataPoints.cxxvtkRearrangeFields.cxxvtkRectangularButtonSource.cxxvtkRectilinearGridClip.cxxvtkRectilinearGridGeometryFilter.cxxvtkRectilinearGridToTetrahedra.cxxvtkRectilinearSynchronizedTemplates.cxxvtkRecursiveDividingCubes.cxxvtkReflectionFilter.cxxvtkRegularPolygonSource.cxxvtkReverseSense.cxxvtkRibbonFilter.cxxvtkRotationalExtrusionFilter.cxxvtkRotationFilter.cxxvtkRuledSurfaceFilter.cxxvtkSelectPolyData.cxxGenerating Code...Compiling...vtkShrinkFilter.cxxvtkShrinkPolyData.cxxvtkSimpleElevationFilter.cxxvtkSliceCubes.cxxvtkSmoothPolyDataFilter.cxxvtkSortDataArray.cxxvtkSpatialRepresentationFilter.cxxvtkSpherePuzzle.cxxvtkSpherePuzzleArrows.cxxvtkSphereSource.cxxvtkSplineFilter.cxxvtkSplitField.cxxvtkStreamLine.cxxvtkStreamPoints.cxxvtkStreamTracer.cxxvtkStreamer.cxxvtkStripper.cxxvtkStructuredGridClip.cxxvtkStructuredGridGeometryFilter.cxxvtkStructuredGridOutlineFilter.cxxGenerating Code...Compiling...vtkStructuredPointsGeometryFilter.cxxvtkSubPixelPositionEdgels.cxxvtkSubdivideTetra.cxxvtkSuperquadricSource.cxxvtkSynchronizedTemplates2D.cxxvtkSynchronizedTemplates3D.cxxvtkSynchronizedTemplatesCutter3D.cxxvtkTensorGlyph.cxxvtkTextSource.cxxvtkTextureMapToCylinder.cxxvtkTextureMapToPlane.cxxvtkTextureMapToSphere.cxxvtkTexturedSphereSource.cxxvtkThreshold.cxxvtkThresholdPoints.cxxvtkThresholdTextureCoords.cxxvtkTransformFilter.cxxvtkTransformPolyDataFilter.cxxvtkTransformTextureCoords.cxxvtkTriangleFilter.cxxGenerating Code...Compiling...vtkTriangularTCoords.cxxvtkTubeFilter.cxxvtkVectorDot.cxxvtkVectorNorm.cxxvtkVisibilitySort.cxxvtkVoxelContoursToSurfaceFilter.cxxvtkWarpLens.cxxvtkWarpScalar.cxxvtkWarpTo.cxxvtkWarpVector.cxxvtkWindowedSincPolyDataFilter.cxxvtkGraphicsInstantiator.cxxGenerating Code...Linking...   Creating library D:\ITK\VTK_binary\bin\Debug/vtkGraphics.lib and object D:\ITK\VTK_binary\bin\Debug/vtkGraphics.exp--------------------Configuration: vtkGenericFiltering - Win32 Debug--------------------Compiling...vtkGenericContourFilter.cxxvtkGenericGeometryFilter.cxxvtkGenericClip.cxxvtkGenericProbeFilter.cxxvtkGenericDataSetTessellator.cxxvtkGenericCutter.cxxvtkGenericGlyph3DFilter.cxxvtkGenericStreamTracer.cxxvtkGenericOutlineFilter.cxxvtkGenericFilteringInstantiator.cxxGenerating Code...Linking...   Creating library D:\ITK\VTK_binary\bin\Debug/vtkGenericFiltering.lib and object D:\ITK\VTK_binary\bin\Debug/vtkGenericFiltering.exp--------------------Configuration: vtkDICOMParser - Win32 Debug--------------------Compiling...DICOMFile.cxxDICOMParser.cxxDICOMAppHelper.cxxGenerating Code...Linking...   Creating library D:\ITK\VTK_binary\bin\Debug/vtkDICOMParser.lib and object D:\ITK\VTK_binary\bin\Debug/vtkDICOMParser.exp--------------------Configuration: vtkzlib - Win32 Debug--------------------Compiling resources...Compiling...adler32.cgzio.cinftrees.cuncompr.ccompress.cinfblock.cinfutil.czutil.ccrc32.cinfcodes.cdeflate.cinffast.cinflate.ctrees.cGenerating Code...Linking...

    DB:3.01:Problems Building A Set Of Libraries jf

    I'm afraid VC6 isn't supported by these forums. For the best possible answers, you should visit the VC newsgroups at http://msdn.microsoft.com/newsgroups.
    Checking by the support forum (if there is such a thing) of the library in question would also be a good idea. Others may have experienced the same issue.

  • RELEVANCY SCORE 3.00

    DB:3.00:Edk 8.1i : Problem Of Generating .Bin File ,For Bpi Booting d9


    I use

    promgen -w -p bin -c FF -o ff1.bin -u 0 download.bit

    to generate the .bin file, and download it into NOR flash, but it can't boot up; the .bit is ok through JTAG download.And the EDK I re-setup, for some system reason; in the former EDK 8.1i,,I do it well,but now i can't.how to do with it?

    DB:3.00:Edk 8.1i : Problem Of Generating .Bin File ,For Bpi Booting d9

    Not sure what’s going on must be some settings or updates missing

    Worst case

    You could copy all the install files from the pc that works to the pc that does not. Meaning go get a crossover cable and copy the entireEDK/ISE directory this should fix your problem.

    Only do this if both machines run same processor. Meaning Intel or AMD but they must be the same.

    cheers,

    Bill




    Cheers,Bill Tomb

  • RELEVANCY SCORE 2.99

    DB:2.99:Sdram Mapping Pin Problem In Edk11.1 j9



    Hi all,

    I have designed a custom board for my embedded application it contains an SDRAM and some other peripherals and flash memories based on XC3S400-pq208 FPGA. Today, when I was trying to compile a simple project - created with EDK wizard - which uses MPMC of EDK for transactions with the SDRAM I received some placement errors in EDK and it couldn't compile the project anymore, as this error seems to be caused by placement and I have designed the PCB at the moment, I want to see if there is and way to bypass this error and force the EDK to keep on compiling the project?

    Below is the Error Message:

    "

    ERROR:Place:17 - The placement constraints of the IOBs fpga_0_DDR_SDRAM_DDR_DM_pin1 and fpga_0_DDR_SDRAM_DDR_Addr_pin3 makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing please remove the placement constraints or move one of these IOBs to a new location.

    "

    I would appreciate any help on this issue.

    Regards,







    Solved!
    Go to Solution.

    DB:2.99:Sdram Mapping Pin Problem In Edk11.1 j9


    Hi Gabor,

    Yes, I said that I have a SDRAM not DDR. I will check the DQMs again but I doubt if it has any problem.

    thank you,

    Hossein

  • RELEVANCY SCORE 2.98

    DB:2.98:Edk 13.3 On Linux + Spartan 3e 500 ds



    Hi,

    I tried to use evaluation EDK on Fedora 16. The environment works well while compiling base project for Virtex ML505 starter kit (Virtex 5). The same software fails while compiling default project for Spartan 3E starter kit - post_par_trce process gets signal 11. Looks weird as the same tools works well on Windows. Has anyone else experienced the same problem?

    Paul

    DB:2.98:Edk 13.3 On Linux + Spartan 3e 500 ds


    I have the same error on my Fedora 16 32-bit system.

    It seems "par" is causing the problem, for both ISE 12.4 and ISE 13.2.

    Below is the message I got back from gdb when I run the "par".

    Hope it will be useful.

    ##########################################################

    GNU gdb (GDB) Fedora (7.3.50.20110722-10.fc16)Copyright (C) 2011 Free Software Foundation, Inc.License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.htmlThis is free software: you are free to change and redistribute it.There is NO WARRANTY, to the extent permitted by law. Type "show copying"and "show warranty" for details.This GDB was configured as "i686-redhat-linux-gnu".For bug reporting instructions, please see:http://www.gnu.org/software/gdb/bugs/...Reading symbols from /media/sda2/Software/Xilinx/13.2/ISE_DS/ISE/bin/lin/par...(no debugging symbols found)...done.(gdb) runStarting program: /media/sda2/Software/Xilinx/13.2/ISE_DS/ISE/bin/lin/par [Thread debugging using libthread_db enabled]Using host libthread_db library "/lib/libthread_db.so.1".process 4168 is executing new program: /media/sda2/Software/Xilinx/13.2/ISE_DS/ISE/bin/lin/parMissing separate debuginfos, use: debuginfo-install glibc-2.14.90-21.i686 libgcc-4.6.2-1.fc16.i686 libusb-0.1.3-9.fc16.i686 libusb1-1.0.9-0.3.rc1.fc16.i686[Thread debugging using libthread_db enabled]Using host libthread_db library "/lib/libthread_db.so.1".process 4168 is executing new program: /media/sda2/Software/Xilinx/13.2/ISE_DS/ISE/bin/lin/unwrapped/parMissing separate debuginfos, use: debuginfo-install glibc-2.14.90-21.i686 libgcc-4.6.2-1.fc16.i686 libusb-0.1.3-9.fc16.i686 libusb1-1.0.9-0.3.rc1.fc16.i686 libuuid-2.20.1-2.1.fc16.i686[Thread debugging using libthread_db enabled]Using host libthread_db library "/lib/libthread_db.so.1".Release 13.2 - par O.61xd (lin)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.Usage: par [-ol std|high] [-pl std|high] [-rl std|high] [-xe n|c] [-mt on|off|1|2|3|4] [-t costtable:1,100] [-p] [-k][-r] [-w] [-smartguide guidefile[.ncd]] [-x] [-nopad] [-power on|off|xe] [-activityfile activityfile[.vcd|.saif]][-ntd] [-intstyle ise|xflow|silent|pa] [-ise projectrepositoryfile] [-filter filter_file[.filter]] infile[.ncd]outfile [constraintsfile[.pcf]]Program received signal SIGSEGV, Segmentation fault.0x450078ce in _IO_getwline_info () from /lib/libc.so.6Missing separate debuginfos, use: debuginfo-install glibc-2.14.90-21.i686 libgcc-4.6.2-1.fc16.i686 libusb-0.1.3-9.fc16.i686 libusb1-1.0.9-0.3.rc1.fc16.i686 libuuid-2.20.1-2.1.fc16.i686

  • RELEVANCY SCORE 2.91

    DB:2.91:Help Me About Edk 98


    Please help me ,thank youThere are "opb_tsd_ref_v1_00_a" and opb_pci_ref_v1_00_b in pcores directory ,and there are "touchscreen_ref_v1_00_a" and "pci_ref_v1_00_b" in drivers directorymy project in XPS ADDRESScompleted code C for project----build project---------------------------------------------------------​--------------------------------------------------​-----------------------Running
    CopyFiles ...

    Copying
    files for os standalone_v1_00_a fromC:\EDK\sw\lib\bsp\standalone_v1_00_a\src\
    to

    C:\thanh\ppc405_0\libsrc\standalone_v1_00_a\
    ...

    Copying
    files for driver uartlite_v1_00_b fromC:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1​_00_b\src\
    to

    C:\thanh\ppc405_0\libsrc\uartlite_v1_00_b\
    ...

    Copying
    files for driver gpio_v2_00_a from

    C:\EDK\sw\XilinxProcessorIPLib\drivers\gpio_v2_00_​a\src\
    to

    C:\thanh\ppc405_0\libsrc\gpio_v2_00_a\
    ...

    Copying
    files for driver sysace_v1_00_a from

    C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_0​0_a\src\
    to

    C:\thanh\ppc405_0\libsrc\sysace_v1_00_a\
    ...

    Copying
    files for driver intc_v1_00_c from

    C:\EDK\sw\XilinxProcessorIPLib\drivers\intc_v1_00_​c\src\
    to

    C:\thanh\ppc405_0\libsrc\intc_v1_00_c\
    ...Copying
    files for driver ddr_v1_00_b from

    C:\EDK\sw\XilinxProcessorIPLib\drivers\ddr_v1_00_b​\src\
    to

    C:\thanh\ppc405_0\libsrc\ddr_v1_00_b\
    ...

    Copying
    files for driver cpu_ppc405_v1_00_a from

    C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_​v1_00_a\src\
    to

    C:\thanh\ppc405_0\libsrc\cpu_ppc405_v1_00_a\
    ...Running
    DRCs for OSes, Drivers and Libraries ...

    Running generate for OS'es, Drivers and Libraries
    .

    --------------------------------------------------​--------------------------------------------------​----------------------YOU CAN TELL ME WHY XPS DON'T COPY DRIVER "touchscreen_ref_v1_00_a" from DRIVERS DIRECTORY to C:\thanh\ppc405_0\libsrc\cpu_ppc405_v1_00_a\
    ...AND MY PROJECT APPEAR ERROR BECAUSE XPS DON'T COPY "touchscreen_ref_v1_00_a" ...--------------------------------------------------​-----------------------------------------------touchscreen_int/src/touchscreen_int.c:34:26:
    xtouchscreen.h: No such file or directory

    touchscreen_int/src/touchscreen_int.c:
    In function `main':

    touchscreen_int/src/touchscreen_int.c:103:
    error: `XPAR_OPB_UART16550_0_BASEADDR' undeclared (first use in this function)

    touchscreen_int/src/touchscreen_int.c:103:
    error: (Each undeclared identifier is reported only once

    touchscreen_int/src/touchscreen_int.c:103:
    error: for each function it appears in.)

    ...........................--------------------------------------------------​--------------------------------------------------​-----I SEE THIS WARNING WHEN COMPILING

    --------------------------------------------------​--------------------------------------------------​-----------------WARNING:MDT - Peripheral opb_tsd_ref_0 is not connected
    to any of the processors

    in
    the system. Check for the following reasons.

    1.
    opb_tsd_ref_0 is not connected to any of the buses connected to a

    processor.

    2.
    opb_tsd_ref_0 does not have adresses set correctly.

    3.
    opb_tsd_ref_0's address is not within any of the bridge windows connected

    to a processor.

    --------------------------------------------------​-------------------------

    PLEASE SHOW ME HOW SOLVE THIS PROBLEM .THANK YOU

    DB:2.91:Help Me About Edk 98

    Update your tool or goto IP catalog click on Communications Low-SPEED then add the OPB UART (LITE) and your done



    Cheers,Bill Tomb

  • RELEVANCY SCORE 2.90

    DB:2.90:How To Use Edk's Vhdl Files p9



    I made a project using EDK 12.1 and I want to use ISE 12.1 to generate the BIT file using VHDL codes generated in EDK.

    But I dont know how to include all the libraries which were used in EDK.

    Please help me to sort out this problem.

    DB:2.90:How To Use Edk's Vhdl Files p9


    hi Gary,

    Actually I am trying to implement microblaze on Alpha Data Card.

    It is easy to do it on digilant board as we have uart there, but how to implement it on ADC as there we have to take care of the protocols of PCI bus. Also we cant view the the microblaze codes as they are in encrypted form, so please guide me how to implement it on ADC.

    thnks.

  • RELEVANCY SCORE 2.90

    DB:2.90:Mpmc Par Face Problem In Edk 11.2 Board Xupv5-Lx110t zx


    I've already posted this problem in the topic " MPMC Par phase fails:- with EDk 10.1 ML505 board with xcvlx110t FPGA", but I chose to post a new message as well in order to draw attention to the problem.

    Even with the use of the EDK BSB files for the xupv5-lx110t board it is impossible to generate the bitstream for a microblaze with an mpmc ddr2 implementation in edk 11.2. However, using the exact same process there is no problem in EDK 10.1 ... I've tried all possible solutions in edk 11.2 including producing a new ucf file for the mpmc from MIG, but the results were the same. So in order to complete my project I have to return to the use of the older version 10.1.

    Could the failure to generate the bitstream for the xupv5-lx110t board be due to an algorithmic glitch in EDK 11.2?

    Has someone in this forum succesfully produced bitstream for microblaze-mpmc-ddr2 for this board in EDK 11.2 and how was the problem solved?

    I would appreciate any suggestions for a solution to this problem!

    DB:2.90:Mpmc Par Face Problem In Edk 11.2 Board Xupv5-Lx110t zx

    I've already posted this problem in the topic " MPMC Par phase fails:- with EDk 10.1 ML505 board with xcvlx110t FPGA", but I chose to post a new message as well in order to draw attention to the problem.

    Even with the use of the EDK BSB files for the xupv5-lx110t board it is impossible to generate the bitstream for a microblaze with an mpmc ddr2 implementation in edk 11.2. However, using the exact same process there is no problem in EDK 10.1 ... I've tried all possible solutions in edk 11.2 including producing a new ucf file for the mpmc from MIG, but the results were the same. So in order to complete my project I have to return to the use of the older version 10.1.

    Could the failure to generate the bitstream for the xupv5-lx110t board be due to an algorithmic glitch in EDK 11.2?

    Has someone in this forum succesfully produced bitstream for microblaze-mpmc-ddr2 for this board in EDK 11.2 and how was the problem solved?

    I would appreciate any suggestions for a solution to this problem!

  • RELEVANCY SCORE 2.88

    DB:2.88:Error:Edk - Generic () - Expected Integer But Got "" - Edk 11.5 Compile Software Platform Fails Quietly j1



    Hi,

    I am compiling my software platform, I have lots of custom IP and drivers.

    One of the drivers fails, I can disable the driver (set to none) and the compile process passes.

    EDK only returns the error:

    ERROR:EDK - generic () - expected integer but got ""
    ERROR:EDK:1188 - Error(s) while running "generate" for process ppc405_0

    I have run libgen from the command line with the verbose option on, and I get no further information as to where the error exists.

    The process simply fails quietly.

    Can anyone please help, this is mega urgent!!

    Thanks

    Lachlan.







    Solved!
    Go to Solution.

    DB:2.88:Error:Edk - Generic () - Expected Integer But Got "" - Edk 11.5 Compile Software Platform Fails Quietly j1


    Hi,

    (Replying to own post).

    If anyone gets this problem, follow this procedure:

    1. Read http://china.xilinx.com/support/answers/32309.htm

    2. Set your software repositories

    3. Make sure under software platform settings - drivers that you do not select "none" or "generic", but select the driver for your hardware.

    Its seems that some custom IP does not support the "generic" driver model, and this causes the libgen process to fail.

    Lachlan.

  • RELEVANCY SCORE 2.88

    DB:2.88:Genarate Saif/Vcd File In Edk 7m


    1st of all im begging sory for my multiple post. This problem has been posted in edk thread, but i did not get any response from the members side. My problem is..

    I am using edk11.1. I want to measure my system power with saif/vcd file using Xpower. How I would generate saif/vcd file in edk platform.

    DB:2.88:Genarate Saif/Vcd File In Edk 7m

    1st of all im begging sory for my multiple post. This problem has been posted in edk thread, but i did not get any response from the members side. My problem is..

    I am using edk11.1. I want to measure my system power with saif/vcd file using Xpower. How I would generate saif/vcd file in edk platform.

  • RELEVANCY SCORE 2.88

    DB:2.88:Import Microblaze To Simulink As A Blackbox zc



    I wonder if it is possible to import Microblaze processor to Simulink environment as a Xilinx BlackBox?

    My team is using MATLAB2006a and EDK 8.2i. I have problems when importing Microblaze Processor into the MATLAB Simulink Environment. When compiling the processor, it causes the MATLAB to hang and crash. From what i heard, this problem has been fixed in EDK 10.1.

    however due to limitation, my team can't update the EDK into 10.1 version.

    therefore, I wonder if there's a way to import Microblaze processor into Simulink environment using Xilinx Blackbox.

    Thanks very much.
    Message Edited by maldinilq on 07-29-2008 09:41 AM

    DB:2.88:Import Microblaze To Simulink As A Blackbox zc


    I wonder if it is possible to import Microblaze processor to Simulink environment as a Xilinx BlackBox?

    My team is using MATLAB2006a and EDK 8.2i. I have problems when importing Microblaze Processor into the MATLAB Simulink Environment. When compiling the processor, it causes the MATLAB to hang and crash. From what i heard, this problem has been fixed in EDK 10.1.

    however due to limitation, my team can't update the EDK into 10.1 version.

    therefore, I wonder if there's a way to import Microblaze processor into Simulink environment using Xilinx Blackbox.

    Thanks very much.
    Message Edited by maldinilq on 07-29-2008 09:41 AM

  • RELEVANCY SCORE 2.87

    DB:2.87:Edk 13.4 Idelayctrl Problem While Building After Upgrading md



    Hi,I installed ISE Design Suite 13.4 and opened up an old project I had been using in 12.1. EDK asked if I would like to upgrade and I answered "yes." With respect to the hardware, EDK informed me that following peripherals will be modified:The following changes will be made:Core microblaze 7.30.a will be replaced by 7.30.bCore mpmc 6.00.a will be replaced by 6.05.aCore plb_v46 1.04.a will be replaced by 1.05.aCore xps_uartlite 1.01.a will be replaced by 1.02.aCore clock_generator 4.00.a will be replaced by 4.03.aCore xps_timebase_wdt 1.01.a will be replaced by 1.02.aCore chipscope_icon 1.04.a will be replaced by 1.06.aCore chipscope_ila 1.03.a will be replaced by 1.05.a--------------------------------------You must manually make the following changes:Core microblaze 7.30.a needs to be replaced by 8.20.bCore lmb_v10 1.00.a needs to be replaced by 2.00.bCore lmb_bram_if_cntlr 2.10.b needs to be replaced by 3.00.bCore mdm 1.00.g needs to be replaced by 2.00.bCore proc_sys_reset 2.00.a needs to be replaced by 3.00.aAfter this I tried to "Generate Bitsream", but now I received following errors while building:

    ERROR:PhysDesignRules:1860 - The delay controller
    IDELAYCTRL_inst is placed at site IDELAYCTRL_X0Y4 but none of the IODELAYs calibrated by this IDELAYCTRL are being used. The IDELAYCTRL should be removed from the design and the idelayctrl_site.rdy net should be connected to GLOBAL_LOGIC_1. A script is available to automate this process. For more details, please search the Xilinx Answers Database for IDELAYCTRL.

    ERROR:Pack:1642 - Errors in physical DRC.
    Mapping completed.
    See MAP report file "map.mrp" for details.
    Problem encountered during the packing phase.

    Design Summary
    --------------
    Number of errors : 2
    Number of warnings : 102

    Before this I got following warnings:

    WARNING:Place:851 - The delay controller
    "IDELAYCTRL_inst" has been locked with the following location constraint:
    COMP "IDELAYCTRL_inst" LOCATE = SITE "IDELAYCTRL_X0Y3" LEVEL 1
    However, none of the delay elements calibrated by this controller are being used. The controller will still use up a global clock resource from the clock region and consume power. Please refer to the usage document to use the controller efficiently.

    WARNING:Place:851 - The delay controller
    "IDELAYCTRL_inst" has been locked with the following location constraint:
    COMP "IDELAYCTRL_inst" LOCATE = SITE"IDELAYCTRL_X0Y4" LEVEL 1
    However, none of the delay elements calibrated by this controller are being used. The controller will still use up a global clock resource from the clock region and consume power. Please refer to the usage document to use the controller efficiently.

    Everything worked fine on EDK 12.1. Any ideas what I could try to fix this?

    DB:2.87:Edk 13.4 Idelayctrl Problem While Building After Upgrading md


    Solved this by removing IDELAYCTRL_X0Y4 from .ucf file, then cleaned netlist and generated all again. Not sure thou will it actually work like it should, but atleast I can generate bitstream now.

  • RELEVANCY SCORE 2.87

    DB:2.87:Tft Issue With Edk 14.2 14.3 7d



    Hi,

    I used EDK 14.1 and added the TFT ip in microblaze project and it worked well but in EDK 14.2 and 14.3 did the same steps and added same tft ip, exported to SDK and then tried to make the new BSP but gives an error as followingsenescenceshows:
    ==========================

    "Compiling standalone";
    "Compiling common"
    mb-ar: creating ./libsyscall.a
    mb-ar: creating ./libxilkernel.a
    "Compiling xilkernel"
    "Compiling bram"
    "Compiling gpio"
    "Compiling uartlite"
    "Compiling intc"
    "Compiling ps2"
    "Compiling tft"
    xtft.c: In function 'XTft_GetPixel':
    xtft.c:1082:0: error: unterminated argument list invoking macro "Xil_In32"
    xtft.c:367:14: error: 'Xil_In32' undeclared (first use in this function)
    xtft.c:367:14: note: each undeclared identifier is reported only once for each function it appears in
    xtft.c:367:2: error: expected ';' at end of input
    xtft.c:367:2: error: expecteddeclaration or statement at end of input
    make[1]: *** [libs] Error 1

    ======================================

    If i remove the tft again from microblaze project then works fine. Could you please tell me about the problem asap.

    Thank you in advance.

    DB:2.87:Tft Issue With Edk 14.2 14.3 7d


    I use the 14.2 version .and i found a bug in the tft driver....

    In xtft.c line 367.a right bracket is lost ...

    I added it(In the installation dir ) ,so it works.

    *PixelVal = Xil_In32(InstancePtr-TftConfig.VideoMemBaseAddr +(4 * (RowVal * XTFT_DISPLAY_BUFFER_WIDTH + ColVal)));

  • RELEVANCY SCORE 2.86

    DB:2.86:Microblaze Project Is Not Compiling In Sdk (Execvp: Permission Denied) j8



    Hi,

    I am using ISE/EDK 10.1.03 and I am running on Vista.

    In ISE I created an embedded processor project, in EDK I configured the system adding a microblaze. In SDK I wanted to write some code. But I can't even compile. This is what I get:

    Building target: TestApp_Peripheral.elf
    mb-gcc -o TestApp_Peripheral.elf TestApp_Peripheral.o xgpio_tapp_example.o -mxl-soft-mul -mxl-pattern-compare -mcpu=v7.10.d -L../../microblaze_0_sw_platform/microblaze_0/lib -xl-mode-executable -T../../../TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld
    collect2: error trying to exec '/cygdrive/c/Xilinx/10.1/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.1/../../../../microblaze-xilinx-elf/bin/ld': execvp: Permission denied
    collect2: ld returned 255 exit status
    mb-gcc: TestApp_Peripheral.o: No such file or directory
    mb-gcc: xgpio_tapp_example.o: No such file or directory
    mb-gcc: no input files

    I tried to figure out if something is wrong with my cygwin, but I don't think so. I am a bit lost, because I couldn't even find a topic where anyone had a similar problem.

    If anyone knows why I got the permission denied, please let me know.

    Thanks a lot.

    Jens







    Solved!
    Go to Solution.

    DB:2.86:Microblaze Project Is Not Compiling In Sdk (Execvp: Permission Denied) j8


    Sorry, for being impatient :)

    The problem I had is described in the Embedded System Tools Reference Manual under the EDK Shell chapter.

    On Vista one has to install cygwin with administrator rights. If not, the problem described above occurs.

  • RELEVANCY SCORE 2.86

    DB:2.86:Problem With Compiling With The Edk cp



    I have the following errors after compiling the EDK libraries

    ** Error: ./hdl/src/vhdl/rx_if.vhd(209): (vcom-1915) Cannot load design unit "xilinxcorelib.async_fifo_v4_0".** Error: ./hdl/src/vhdl/rx_if.vhd(209): (vcom-1195) Cannot find expanded name "xilinxcorelib.async_fifo_v4_0".** Error: ./hdl/src/vhdl/rx_if.vhd(210): (vcom-1105) Name (indexed name) does not denote an entity name.** Error: ./hdl/src/vhdl/rx_if.vhd(209): Unknown expanded name.** Error: ./hdl/src/vhdl/rx_if.vhd(568): VHDL Compiler exiting

    and

    ** Error: ./hdl/src/vhdl/rx_intrfce.vhd(163): (vcom-1915) Cannot load design unit "xilinxcorelib.async_fifo_v5_1".** Error: ./hdl/src/vhdl/rx_intrfce.vhd(163): (vcom-1195) Cannot find expanded name "xilinxcorelib.async_fifo_v5_1".** Error: ./hdl/src/vhdl/rx_intrfce.vhd(164): (vcom-1105) Name (indexed name) does not denote an entity name.** Error: ./hdl/src/vhdl/rx_intrfce.vhd(163): Unknown expanded name.** Error: ./hdl/src/vhdl/rx_intrfce.vhd(237): (vcom-1915) Cannot load design unit "xilinxcorelib.async_fifo_v5_1".** Error: ./hdl/src/vhdl/rx_intrfce.vhd(237): (vcom-1195) Cannot find expanded name "xilinxcorelib.async_fifo_v5_1".** Error: ./hdl/src/vhdl/rx_intrfce.vhd(238): (vcom-1105) Name (indexed name) does not denote an entity name.** Error: ./hdl/src/vhdl/rx_intrfce.vhd(237): Unknown expanded name.** Error: ./hdl/src/vhdl/rx_intrfce.vhd(304): VHDL Compiler exiting
    Does anyone know how to fix this?

    Thanks

    DB:2.86:Problem With Compiling With The Edk cp


    Please clarify when these message appears. What commands you have entered?

    From the error message, I suspect you're compiling the EDK libraries. rx_if.vhd is a file from opb_hdlc core. It needs the support of XilinxCoreLib.

    Please make sure your have fully compiled the XilinxCoreLib during compxlib.

  • RELEVANCY SCORE 2.85

    DB:2.85:Does Anyone Has Problem When Install Edk 10.1 With Ise 10.1? sc



    I tried to install EDK 10.1with the ISE 10.1 on window xp professional sp3.

    However, it keeps showing a error message " drop0142_EDK_10.1_120292330.zip.xz zipfile not found" through the whole installation processes.

    Until it installed to 60%, it stoped and stated that setup.exe has problem.

    Then setup is aborted.

    Ido not knowif my ISE has problem or EDK has problems.

    Does anyone have the same problem happened before ?

    thank you very much~

    Xilinxgirl







    Solved!
    Go to Solution.

    DB:2.85:Does Anyone Has Problem When Install Edk 10.1 With Ise 10.1? sc


    Hello,

    I've got no problem (ISE+EDK+Chipscope+...). May you can try to dowload again the install file (corrupt ?).

    Best regards

  • RELEVANCY SCORE 2.85

    DB:2.85:Edk 10.1 Full Version 89



    Hi,

    I have installed ISE 10.1 Webpack. and now i am trying to install EDK. Gives erros fileset.txt not found. So i the forum i found its an update.. But i am facing problem to download

    the full version EDK 10.1 if i go to download page.. it shows 11.1 is ISE10.1 and EDK11.1 compatible?

    Please waiting for an answer as soon as possible..

    thanks,

    DB:2.85:Edk 10.1 Full Version 89

    EDK 11.1 needs to be used with ISE 11.1 and similarly EDK 10.1 needs to be used with ISE 10.1.

  • RELEVANCY SCORE 2.85

    DB:2.85:Problem On Working With Edk ap



    hi,

    i have xilinx ISE 9.2i and EDK 9.1i software. i installed both in my system in different location i.e for ISE(C:\program files\Xilinx ISE9.2i) and for EDK(C:\program files\EDK). i successfully installed both. I can create the "system.xmp" file using ISE. then the EDK console will be opened. but whenever i am trying to work with EDK . It shows the following error. The error msg is
    "ERROR:PersonalityModule:7- Unable to open xilinx data file for vendor/device Module "qrvirtex2". Please make sure that it has been correctly installed before continuing."
    and automatically closed the EDK console.

    i cant solve this problem and alsocant use the EDK softyware. if anyone know the solution for this pls help me..

    ​ thankyou.
    with regards,
    albin viju.

    DB:2.85:Problem On Working With Edk ap

    I've been told by a few sources that we're not supposed to mix ISE and EDK revisions.

  • RELEVANCY SCORE 2.85

    DB:2.85:Faulting Application Name Xmd.Exe sk


    Hi all,

    I was using Xilinx 12.4 EDK and while compiling my computer went extremely slow to the point of hanging before I had to do a cold reset. My system is Windows 7 Professional 32 bit, 2GB memory. I had a look in the windows event logs and found this error (see attached). I know the system is not the most powerful.

    I was wondering if anyone had this problem?!

    Thanks in advanced










    Attachments:




    DB:2.85:Faulting Application Name Xmd.Exe sk

    itsupport@isgfire.co.uk wrote:

    Hi all,

    I was using Xilinx 12.4 EDK and while compiling my computer went extremely slow to the point of hanging before I had to do a cold reset. My system is Windows 7 Professional 32 bit, 2GB memory.

    2 GB is barely enough to run Windows 7!




    ----------------------------------------------------------------Yes, I do this for a living.

  • RELEVANCY SCORE 2.84

    DB:2.84:Xupv5 Xbd Support Problem For Edk 10.1 Sp3 mc



    I download EDK-XUPV5-LX110T design and set the projects ,but the EDK get the error ,not support the speed -1 ; and for customer board building there is no v5LX110t;and I tried to change the xbd file speed to -2 or -3,but same error not support the speed -2 or -3.

    how to do with it?

    DB:2.84:Xupv5 Xbd Support Problem For Edk 10.1 Sp3 mc

    Also make sure you are using Foundation. WebPACK does not support the 5VLX110T.

    bt

  • RELEVANCY SCORE 2.83

    DB:2.83:Edk 10.0.3 Can't Use Xup Vii-Pro Board Correctly s1



    all..

    I use previous 9.1 version V-II board libs files on 10.0.3,when use XPS's bsb,it could find the board ,butsomeoftheboard's IO devices are missing ,How can I sovled the problem ,Is there new version libs for 10.0.3

    well, I finally find the EDK XUPV2P Pack for 10 EDK 10.1 SP3 ,but it only takes 8kbs ,the pcores and drivers are missing for EDK 10.1. I update the files of board information and use the previous verion ofpcores and driversfiles ,It seems still wrong..

    Is the EDK XUPV2P Pack for 10 EDK 10.1 SP3 is still developing ???

    Message Edited by jorsong on 06-05-2009 02:12 AMMessage Edited by jorsong on 06-05-2009 02:15 AM

    DB:2.83:Edk 10.0.3 Can't Use Xup Vii-Pro Board Correctly s1


    You will really be pleased to know this board is discontinued, so you can forget any support on it.

    Also under 10.1SP3, the DDR external memory is very unstable. go back to 9.x and have a happy life.

  • RELEVANCY SCORE 2.82

    DB:2.82:Error Compiling Vivado Bsp cm



    Hi all,

    I am using a XC7Z020CLG484-1 Zedboard and am trying to instance a fairly basic distance_squared function. The C++ source that is synthesised is attached (distance.cpp). I have tried using AutoESL and Vivado for synthesis, both with the same result.

    I am using AutoESL 2012.1, Vivado 14.3, EDK 14.3, SDK 14.3. I am having a problem compiling the board support package for my project. It seems that the DATA_SYNC macro is not defined... and I am unsure of where it should be defined and why it is not defined.

    The steps that I have followed are as follows:

    Synthesis distance.cpp in AutoESL/Vivado
    Export pcores from AutoESL/Vivado.
    In PlanAhead, create a new project and then add a new embedded source with the name "system".
    Import pcore into a new EDK project (through PlanAhead).
    Create the appropriate connections in EDK.
    Create a top level HDL for the "system" embedded source.
    Generate the bitstream for my project.
    Export the bitstream to SDK.
    Create a new "Xilinx Application" project in SDK, with a new board support package (named "standalone_bsp").
    When I attempt to compile the newly generated BSP, the compilation fails. The error is as follows.

    make -k all

    libgen -hw ../system_hw_platform/system.xml\ \ -pe ps7_cortexa9_0 \ -log libgen.log \ system.msslibgenXilinx EDK 14.3 Build EDK_P.40xdCopyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

    Command Line: libgen -hw ../system_hw_platform/system.xml -pe ps7_cortexa9_0-log libgen.log system.mss

    Staging source files.Running DRCs.Running generate.Running post_generate.Running include - 'make -s include "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.

    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'.Compiling commonC:\Xilinx\14.3\ISE_DS\EDK\gnu\arm\nt64\bin\arm-xilinx-eabi-ar.exe: creating ../../../lib/libxil.aCompiling xadcCompiling standaloneCompiling axidmaxaxidma_bdring.c: In function 'XAxiDma_BdRingToHw':xaxidma_bdring.c:1068:2: error: 'DATA_SYNC' undeclared (first use in this function)xaxidma_bdring.c:1068:2: note: each undeclared identifier is reported only once for each function it appears inmake[1]: *** [libs] Error 1Compiling canpsCompiling devcfgCompiling dmapsCompiling emacpsCompiling gpiopsCompiling iicpsCompiling qspipsCompiling scugicCompiling scutimerCompiling scuwdtCompiling ttcpsCompiling uartpsCompiling usbpsCompiling wdtps...

    **** Build of configuration Debug for project distance ****

    make all Building file: ../src/helloworld.cInvoking: ARM gcc compilerarm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.d" -o"src/helloworld.o" "../src/helloworld.c"cygwin warning: MS-DOS style path detected: C:\Users\Joshua\Desktop\xilinx\sw_update\distance_planahead2\distance_planahead2.sdk\SDK\SDK_Export\distance\Debug Preferred POSIX equivalent is: /cygdrive/c/Users/Joshua/Desktop/xilinx/sw_update/distance_planahead2/distance_planahead2.sdk/SDK/SDK_Export/distance/Debug CYGWIN environment variable option "nodosfilewarning" turns off this warning. Consult the user's guide for more details about POSIX paths: http://cygwin.com/cygwin-ug-net/using.html#using-pathnamesFinished building: ../src/helloworld.c Building file: ../src/platform.cInvoking: ARM gcc compilerarm-xilinx-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/platform.d" -MT"src/platform.d" -o"src/platform.o" "../src/platform.c"cygwin warning: MS-DOS style path detected: C:\Users\Joshua\Desktop\xilinx\sw_update\distance_planahead2\distance_planahead2.sdk\SDK\SDK_Export\distance\Debug Preferred POSIX equivalent is: /cygdrive/c/Users/Joshua/Desktop/xilinx/sw_update/distance_planahead2/distance_planahead2.sdk/SDK/SDK_Export/distance/Debug CYGWIN environment variable option "nodosfilewarning" turns off this warning. Consult the user's guide for more details about POSIX paths: http://cygwin.com/cygwin-ug-net/using.html#using-pathnamesFinished building: ../src/platform.c Building target: distance.elfInvoking: ARM gcc linkerarm-xilinx-eabi-gcc -Wl,-T -Wl,../src/lscript.ld -L../../standalone_bsp/ps7_cortexa9_0/lib -o"distance.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-groupcygwin warning: MS-DOS style path detected: C:\Users\Joshua\Desktop\xilinx\sw_update\distance_planahead2\distance_planahead2.sdk\SDK\SDK_Export\distance\Debug Preferred POSIX equivalent is: /cygdrive/c/Users/Joshua/Desktop/xilinx/sw_update/distance_planahead2/distance_planahead2.sdk/SDK/SDK_Export/distance/Debug CYGWIN environment variable option "nodosfilewarning" turns off this warning. Consult the user's guide for more details about POSIX paths: http://cygwin.com/cygwin-ug-net/using.html#using-pathnamesc:/xilinx/14.3/ise_ds/edk/gnu/arm/nt64/bin/../lib/gcc/arm-xilinx-eabi/4.6.1/../../../../arm-xilinx-eabi/bin/ld.exe: cannot find -lxilcollect2: ld returned 1 exit statusmake: *** [distance.elf] Error 1

    Any help would be greatly appreciated as I have been trying to get this working for weeks now. I was using 14.2 before and had different results, but ultimately it still wouldn't work for me.










    Attachments:







    distance.cpp ‏1 KB

    DB:2.82:Error Compiling Vivado Bsp cm


    I had a similar problem with ISE 14.4, with compile errors when trying to create the BSP from the HW Platform, like others here:

    http://www.zedboard.org/content/zedboard-tutorial-problem-lab2#comment-2160

    I finally found the solution byfrom Kevin (zedhed) here: http://www.zedboard.org/content/problems-creating-board-support-files-zed-144-version-sdk

    The solution was Kevin's suggestion 1: 1Launch PlanAhead from a command line, then launch SDK from PlanAhead. Specifically, I launched PlanAhead from the “ISE Design Suite 64-bit Command Prompt” by typing “planahead”. Then I created and exported the HW_Platform to SDK and the BSP was created without errors finally.

    But I found that Kevin's solution 2 from, starting SDK from Start menu did NOT work for me.

  • RELEVANCY SCORE 2.82

    DB:2.82:Ml402 Problem With Edk And Linear Flash ... ka



    Hi,

    I have a ML402 Board and one problem with EDK and Linear Flash. I have created a new project with EDK with "Test Memory" initialize BRAM. If I upload "bitstream" with JTAG, on serial port I verify everything works fine. Now I want this bitstream being loaded from Flash.
    I followed the guide "ML40x Getting Started Tutorial" on page 28 "ML40x Demonstrations in Linear Flash". I have replaced the file "hello_char_lcd_hw.bit" with my EDK "bitstream", but the "DONE" LED does not turn ever. I did another test using a "bitstream" generated with ISE that works perfectly on ML402. I following the same procedure. The file is loaded safely.Why bitstream generated by EDK not work if loaded by "Linear Flash" ? Someone had the same problem ? I can help someone and maybe check ? Regards.Kappa.







    Solved!
    Go to Solution.

    DB:2.82:Ml402 Problem With Edk And Linear Flash ... ka


    Hi boris,

    Thanks for your replay. I have changed te "startclk" in a "bitgen.ut" from "JtagClk" to "Cclk" and now work fine. I have not added "ConfigRate" the default is 4.

    Another question:

    I have generate a Default Project, the Flash Address is 0x88800000.

    If I use "Device Configuration - Flash Program Memory" to generate the bootloader, I can't program the flash. I obtain "The flash block erase operation errored out !"

    I can not understand where lies the problem.

    I fixed it was wrong to include "offset".

    Regards.

    Kappa.

    Message Edited by secureasm on 01-04-2009 01:40 AM

  • RELEVANCY SCORE 2.82

    DB:2.82:Edk Installation Problem z3



    I had EDK running fine but when I removed ISE 9.1 to get more room on my HD EDK no longer runs. I've uninstalled ISE and EDK and reloaded them and ISE is running but EDK starts up, locks up andthen Windows gives me theerror of death.

    Thanks,

    DeWayne

    DB:2.82:Edk Installation Problem z3


    I had EDK running fine but when I removed ISE 9.1 to get more room on my HD EDK no longer runs. I've uninstalled ISE and EDK and reloaded them and ISE is running but EDK starts up, locks up andthen Windows gives me theerror of death.

    Thanks,

    DeWayne

  • RELEVANCY SCORE 2.80

    DB:2.80:Using Edk Builds Vxworks6.3 Os Problem 3a



    general in the edk,we use it build project for standone mode but when i change os to vxworks6.3 then build show below error message:

    Compiling bspCompiling cpu_ppc405Libraries generated in C:\XilinxTest\14\ppc405_1\lib\ directoryRunning execs_generate for OS'es, Drivers and Libraries ... LibGen Done. powerpc-eabi-gcc -O2 TestApp_Peripheral/src/TestApp_Peripheral.c TestApp_Peripheral/src/xgpio_tapp_example.c -o TestApp_Peripheral/executable.elf \ -Wl,-T -Wl,TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld -g -I./ppc405_0/include/ -ITestApp_Peripheral/src/ -Ippc405_0/libsrc/gpio_v2_01_a/src/ -Ippc405_0/libsrc/common_v1_00_a/src/ -Ippc405_0/libsrc/cpu_ppc405_v1_00_a/src/ -L./ppc405_0/lib/ \ /cygdrive/c/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: cannot find boot.ocollect2: ld returned 1 exit statusmake: *** [TestApp_Peripheral/executable.elf] Error 1Done!someone can help me,thank you very much

    DB:2.80:Using Edk Builds Vxworks6.3 Os Problem 3a


    Hi ,

    me also facing same problem , if u solved ?

    Could u explain 2me...

    Regards,

    Sowji...

  • RELEVANCY SCORE 2.80

    DB:2.80:Error When Resynthesize Microblaze System In Ise. 78



    Hi,

    When I tried to re-synthesize a MicroBlaze system in IS, I've already add all the source files necessary into the project, there are always these errors coming to me:

    Compiling vhdl file "C:/Xilinx/9.2i/EDK/hw/XilinxProcessorIPLib/pcores​/microblaze_v7_00_b/hdl/vhdl/carry_and.vhd" in Library work.ERROR:HDLParsers:3317 - "C:/Xilinx/9.2i/EDK/hw/XilinxProcessorIPLib/pcores​/microblaze_v7_00_b/hdl/vhdl/carry_and.vhd" Line 74. Library Microblaze_v7_00_b cannot be found.ERROR:HDLParsers:3013 - "C:/Xilinx/9.2i/EDK/hw/XilinxProcessorIPLib/pcores​/microblaze_v7_00_b/hdl/vhdl/carry_and.vhd" Line 75. Library Microblaze_v7_00_b is not declared.WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it.

    I use ISE 9.2.04 EDK 9.2.02

    Thank you for telling me how to do to overcome this problem.
    Message Edited by manh_et2 on 10-07-2008 07:42 AM

    DB:2.80:Error When Resynthesize Microblaze System In Ise. 78


    Unless someone knows a faster way (like use EDK) you have some hard work in front of you.

    The specific problem here is that ISE doesn't just need the carry_and.vhd file in the project; it needs it associated with

    the specific VHDL library "Microblaze_v7_00_b".

    So before you compile it, you have to create an empty VHDL library by that name.

    (e.g. "New Source", select "VHDL Library" for source type, and type "Microblaze_v7_00_b" for its name, then "Finish".

    Then select the VHDL file in the "Work" library, right click, and "Move to library", and select "Microblaze_v7_00_b".

    Repeat for all files in project.

    This can be scripted in TCL. I forget the TCL command to create a library, but you should be able to

    find documentation on "xfile add" to add a VHDL file directly to the correct library.

  • RELEVANCY SCORE 2.80

    DB:2.80:I Can't Install Edk And Planahead In Debian 6.0 64bit. 9a


    I've installed ISE 10.1 in a Virtual Machine using Linux debian 6.0 64 bit. After I tried to install EDK and PlanAhed with no sucess. During the instalation setup, I couldn't check Embedded Development Kit (EDK) as show the window bellow.

    How can I solve this problem?

    Thanks!







    Solved!
    Go to Solution.

    DB:2.80:I Can't Install Edk And Planahead In Debian 6.0 64bit. 9a


    Its runningLinux Debian 6.0 64 bits on my VM.

  • RELEVANCY SCORE 2.79

    DB:2.79:Sdk Compiling Error! 17



    Hi all!

    I have build a project with EDK ,and press "export hard design to SDK" , when I pressed "build all" in SDK ,compiler report a error ,the compling options include :... -MF "src/impro.d" -MT "src/impro.d" -o "src/impro.o" "../src/impro.c"

    then the error information :

    ../src/impro.c:in function 'impro_lock_Register':

    ../src/impro.c:error 'XPAR_IMPRO_ALL_HARD_RAM_PLBW_0_MEMMAP_REGLOCK' undeclared.

    ....many similar macro has no definition.

    could you help me fixing the problem?thanks!

    DB:2.79:Sdk Compiling Error! 17


    That's good news. The error as i mentioned was to check if your xparameters.h search for hte variable.

    --HS




    ----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.79

    DB:2.79:Problem With Compilation Of My C Project ( Leds.C) In Sdk pd


    HI,

    I have created my custom IPpwm_lights with CIP wizard. I have used the tests drives of the guideEDK Concepts, Tools, and Techniquesin theedk_ctt.pdf.In SDK i have createda new Xilinx C project and i have used theleds.c file from the Zip (edk_ctt.zip)file that accompanies this guide in the stage ofExporting the Design and Generating a New Bitstream.

    When i compile the project leds.c,the compile fails and i have this in the console:

    **** Build of configuration Debug for project hello_world_0 ****

    make all

    Building file: ../src/leds.c

    Invoking: MicroBlaze gcc compiler

    mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../hello_world_bsp_0/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.00.a -mno-xl-soft-mul -MMD -MP -MF"src/leds.d" -MT"src/leds.d" -o"src/leds.o" "../src/leds.c"

    cygwin warning:

    MS-DOS style path detected: C:\Users\ridha\Desktop\test_ISE_10_05\SDK_New_Work​space\hello_world_0\Debug

    Preferred POSIX equivalent is: /cygdrive/c/Users/ridha/Desktop/test_ISE_10_05/SDK​_New_Workspace/hello_world_0/Debug

    CYGWIN environment variable option "nodosfilewarning" turns off this warning.

    Consult the user's guide for more details about POSIX paths:

    http://cygwin.com/cygwin-ug-net/using.html#using-p​athnames

    ../src/leds.c: In function ‘main’:

    ../src/leds.c:47: warning: implicit declaration of function ‘XUartLite_RecvByte’

    ../src/leds.c:54: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:68: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:73: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:78: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:83: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:88: warning: assignment makes pointer from integer without a cast

    ../src/leds.c:101: warning: assignment makes pointer from integer without a cast

    Finished building: ../src/leds.c

    Building target: hello_world_0.elf

    Invoking: MicroBlaze gcc linker

    mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../hello_world_bsp_0/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.00.a -mno-xl-soft-mul -o"hello_world_0.elf" ./src/leds.o

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: region dlmb_cntlr_ilmb_cntlr is full (hello_world_0.elf section .text)

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .init [00000050 - 00000077] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .fini [00000078 - 00000097] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .rodata [00000098 - 0000121b] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .sdata2 [0000121c - 0000121f] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .data [00001220 - 0000176b] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .ctors [0000176c - 00001773] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .dtors [00001774 - 0000177b] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .eh_frame [0000177c - 0000177f] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .jcr [00001780 - 00001783] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .bss [00001788 - 000017f3] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .heap [000017f4 - 00001bf7] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: section .stack [00001bf8 - 00001ff7] overlaps section .text [00000050 - 00010cd3]

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: region dlmb_cntlr_ilmb_cntlr is full (hello_world_0.elf section .text)

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: hello_world_0.elf: section .text lma 0x50 overlaps previous sections

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: hello_world_0.elf: section .fini lma 0x78 overlaps previous sections

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/../.​./../../microblaze-xilinx-elf/bin/ld: hello_world_0.elf: section .rodata lma 0x98 overlaps previous sections

    /cygdrive/c/Xilinx/12.3/ISE_DS/EDK/gnu/microblaze/​nt/bin/../lib/gcc/microblaze-xilinx-elf/4.1.2/bs/m​/crtend.o.init+0x0): relocation truncated to fit: R_MICROBLAZE_32_PCREL_LO against `.text'

    collect2: ld returned 1 exit status

    make: *** [hello_world_0.elf] Error 1

    I don't find where are the error .

    Can anyone help please?

    DB:2.79:Problem With Compilation Of My C Project ( Leds.C) In Sdk pd


    Hi,
    thank you for allthatreplayfor mymessageand itworked wellbut nowi have other problem, i have connected my custom IP to the MicroBlaze using the Fast Simplex Link (FSL) channel and in SDK i have created a new Xilinx C projecttest_fsl.c :
    /** test_fsl.c** Created on: 1 juil. 2011* Author: ridha*//*************************************************​***************************** Filename: C:\Users\ridha\Desktop\test_fsl_0107\test_fsl\test​_fsl_ridha\drivers/ridha0107_v1_00_a/examples/ridh​a0107_v2_1_0_app.c* Version: 1.00.a* Description: ridha0107 (new FSL core) Driver Example File* Date: Fri Jul 01 11:59:33 2011 (by Create and Import Peripheral Wizard)**************************************************​***************************/#include "xutil.h"#include "stdlib.h"#include "ridha0107.h"#include "xparameters.h"#include "stdio.h"/** Follwing is an example driver function* that is called in the main function.** This example driver writes all the data in the input arguments* into the input FSL bus through blocking writes. FSL peripheral will* automatically read from the FSL bus. Once all the inputs* have been written, the output from the FSL peripheral is read* into output arguments through blocking reads.** CAUTION:** The sequence of writes and reads in this function should be consistent* with the sequence of reads or writes in the HDL implementation of this* coprocessor.**/// Instance name specific MACROs. Defined for each instance of the peripheral.#define WRITE_RIDHA0107_0(val) write_into_fsl(val, XPAR_FSL_RIDHA0107_0_INPUT_SLOT_ID)#define READ_RIDHA0107_0(val) read_from_fsl(val, XPAR_FSL_RIDHA0107_0_OUTPUT_SLOT_ID)void ridha0107_app( unsigned int* input_0, /* Array size = 1 */ unsigned int* output_0 /* Array size = 1 */ ){ int i; //Start writing into the FSL bus for (i=0; i1; i++) { WRITE_RIDHA0107_0(input_0[i]); } //Start reading from the FSL bus for (i=0; i1; i++) { READ_RIDHA0107_0(output_0[i]); }}main(){ unsigned int input_0[1]; unsigned int output_0[1];#ifdef __PPC__ // Enable APU for PowerPC. unsigned int msr_i; msr_i = mfmsr(); msr_i = (msr_i | XREG_MSR_APU_AVAILABLE | XREG_MSR_APU_ENABLE) ~XREG_MSR_USER_MODE; mtmsr(msr_i);#endif //Initialize your input data over here: input_0[0] = 12345; //Call the macro with instance specific slot IDs ridha0107( XPAR_FSL_RIDHA0107_0_INPUT_SLOT_ID, XPAR_FSL_RIDHA0107_0_OUTPUT_SLOT_ID, input_0, output_0 ); // You can also define your own function to access the peripheral // Here you are calling the example function defined above // Note the slot ID can not be passed over as function parameters ridha0107_app( input_0, output_0 );}

    When i compile the project test_fsl.c,the compile fails and i have this in the console:

    **** Build of configuration Debug for project hello_world_0 ****make all Building file: ../test_fsl.cInvoking: MicroBlaze gcc compilermb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../hello_world_bsp_0/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.00.a -mno-xl-soft-mul -MMD -MP -MF"test_fsl.d" -MT"test_fsl.d" -o"test_fsl.o" "../test_fsl.c"../test_fsl.c:67: warning: return type defaults to ‘int’../test_fsl.c: In function ‘main’:../test_fsl.c:99: warning: control reaches end of non-void function/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s: Assembler messages:/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3427: Error: register expected, but saw 'rfslXP'/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3427: Warning: ignoring operands: rfslXPAR_FSL_RIDHA0107_0_INPUT_SLOT_ID /cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3447: Error: register expected, but saw 'rfslXP'/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3447: Warning: ignoring operands: rfslXPAR_FSL_RIDHA0107_0_OUTPUT_SLOT_ID /cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3500: Error: register expected, but saw 'rfslXP'/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3500: Warning: ignoring operands: rfslXPAR_FSL_RIDHA0107_0_INPUT_SLOT_ID /cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3513: Error: register expected, but saw 'rfslXP'/cygdrive/c/Users/ridha/AppData/Local/Temp/ccnwczx​B.s:3513: Warning: ignoring operands: rfslXPAR_FSL_RIDHA0107_0_OUTPUT_SLOT_ID make: *** [test_fsl.o] Error 1

    I don't find where are the error .

    Can anyone help please?

    

    

    

  • RELEVANCY SCORE 2.79

    DB:2.79:Problem With Using Edk In System Generator js



    Hello,

    I have imported an XPS project to EDK processor in system generator. System generator sucessfully generates the bitstream. It includes all the blocks I have put in my SysGen design and runs properly on my Virtex II Pro board. The only problem is that itdoes not execute my C-code from the XPS project!

    Any idea on this, please?

    DB:2.79:Problem With Using Edk In System Generator js


    I recommend that you walk through the EDK import tutorial. This may help you find why your code isn't being include.




    ChrisVideo Solutions Center: http://www.xilinx.com/support/answers/56851.htm

  • RELEVANCY SCORE 2.79

    DB:2.79:How To Do Incremental Compiling In Edk/Xps To Meet Timing Closure ? 37



    Hello,

    I have a design that uses MPMC to interface with DDR2 chips. It has been working fine. When I added more IP in the system (I am using EDK11.4), I notice sometimes by changing the IP pin assignment (not related to DDR2 at all), the compiler (generate bitstream in EDK) gave error (PAR could not meet all timing constraints) . The error is from MPMC core:

    NET "mpmc_0/mpmc_0/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]..u_dqs_delay_col0/delay4" MAXDELAY = 0.19 ns" and the "Best Case Achievable is 0.282ns".

    If I change the IP pin assignment, this timing closure problem goes away. This is no error.

    My questions is, in EDK/XPS, is there a way to "lock" the MPMC core constrain by incremental compiling so that the timing closure will be meet no matter what else IP added later on ?

    Thank you,

    Tom

    DB:2.79:How To Do Incremental Compiling In Edk/Xps To Meet Timing Closure ? 37


    Hello,

    I have a design that uses MPMC to interface with DDR2 chips. It has been working fine. When I added more IP in the system (I am using EDK11.4), I notice sometimes by changing the IP pin assignment (not related to DDR2 at all), the compiler (generate bitstream in EDK) gave error (PAR could not meet all timing constraints) . The error is from MPMC core:

    NET "mpmc_0/mpmc_0/mpmc_core_0/gen_s3_ddr2_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]..u_dqs_delay_col0/delay4" MAXDELAY = 0.19 ns" and the "Best Case Achievable is 0.282ns".

    If I change the IP pin assignment, this timing closure problem goes away. This is no error.

    My questions is, in EDK/XPS, is there a way to "lock" the MPMC core constrain by incremental compiling so that the timing closure will be meet no matter what else IP added later on ?

    Thank you,

    Tom

  • RELEVANCY SCORE 2.78

    DB:2.78:Problem In Building S/W Appln With Edk 10.1 And Bluecat Linux 7x



    Hi

    when i tried to build the software application in EDK with bluecat linux sp3e BSP i found following error and the application has not built properly

    ERROR:MDT - linux_bc54 () - Error: No target directory specified. while executing "error "Error: No target directory specified."" (procedure "::sw_linux_bc54_v1_00_a::linux_drc" line 15) invoked from within "::sw_linux_bc54_v1_00_a::linux_drc 196377408" Done! can anyone answer my question?

    Regards,

    Narsimha Rao T







    Solved!
    Go to Solution.

    DB:2.78:Problem In Building S/W Appln With Edk 10.1 And Bluecat Linux 7x


    Hi Narsimha,

    Are you sure that you can develop a Blue Cat application with XPS? I don't have much experience withBlue Cat, but I suppose that there should be an IDE provied by LynuxWorks.

    -XF

  • RELEVANCY SCORE 2.78

    DB:2.78:Building My Own Ace File From The Ml505 Getting Started Guide Without The Edk cz



    Hi,

    I'm trying to build an ACE file for button_led_test_hw.bit as specified in the Getting Started Guide.

    I can build it with xmd genace in the EDK, but I cannot build it correctly with impact.

    The sizes of the ACE files are different.

    xmd - 1,786 KB

    impact - 2,129 KB

    Is there something I'm missing? Is it possible to make the ACE file without the EDK?

    Thanks!







    Solved!
    Go to Solution.

    DB:2.78:Building My Own Ace File From The Ml505 Getting Started Guide Without The Edk cz


    Hi,

    I made a bad assumption that the files needed to be the same size.

    The ACE files built from impact are just fine.

  • RELEVANCY SCORE 2.78

    DB:2.78:Ise Or Edk 33



    Please what is the difference between ISE and EDK?

    second how can I get and install EDK 6.2?

    DB:2.78:Ise Or Edk 33


    You can see a description of the current differences between ISE and EDK here: http://www.xilinx.com/tools/designtools.htm

    As a VERY rough description, ISE is used for programming logic on your device, either via HDL code or schematic entry.

    EDK tools allow for either soft (logic-using)or hard processors (embedded PPCor soon-to-be ARM) to be put ontoor activated on your device, complex peripherals like DDR, PCI-e, etc., and embedded operating systems like XILKERNEL in an easy-to-use fashion. This mainly uses C-code

    I can work on getting you a copy of 6.1 EDK, but you would need to ensure you have a valid registration code for it. Do you?

  • RELEVANCY SCORE 2.78

    DB:2.78:There's No Shortcut Of Ise And Edk After Installing Ise12.1 And Ise12.4 Under Red Hat El As 5 da



    As the title said, I couldn't startup ISE or EDK. Also the shortcuts were unavailable. What's the problem? Linux version? decompression under window? C Shell? Please help me. Thanks.







    Solved!
    Go to Solution.

  • RELEVANCY SCORE 2.77

    DB:2.77:Edk And Sdk p8



    Hi every one, I am using a spartan 3e fpga board from xilinx, it's not a starter board so I use also an expansion board. I downloaded a tutorial from xilinx for EDK but I have an error message indicating that the microblaze is under reset. I don't know how to solve this problem, if anyone of you have already met this kind of problem? Does somebody give a good and simple tutorial for EDK it will be very very helpful.

    Thank you

    DB:2.77:Edk And Sdk p8


    Hello

    Once I finish programming the bitstream in the FPGA and when I want to debug on hardware I receive this error message

    "Failed to run the ELF executable file on target.Error Initializing : XMD failed to connect to remote target. Error: : ERROR: Microblaze is under Reset. Check if the reset input to Microblaze and its bus interfaces are connceted proprely UNABLE to stop microblaze. "

  • RELEVANCY SCORE 2.77

    DB:2.77:Expoting Pcore To Edk Project p1



    Hi There :-)

    I am using Sysgen v9.1.01.

    I am trying to export sysgen module as a pcore to xilinx-edk using EDK EXPORT TOOL.

    In the compilation settings i couldn't find the "pcore under construction" and the "bus interface" caption...

    i'm reffering to sysgen v10.1.1. user guide... which has the feature of "port bus mapping"...

    While trying to compile i found the following error details,

    **************************************************​**************************************************​******************

    Begin generation Checking model status Checking simulation times Performing compilation and generation Compilation and generation completed in 11.0749 secondsExporting design as a pcoreRunning wrapper to join shared memoryRunning wrapper to create EDK filesCreating PCore files ...Writing PAO file and populating hdl directory.Writing BBD file and populating netlist directory.Writing MPD file.psfutil version Xilinx EDK 9.1.02 Build EDK_J_SP2.4Copyright (c) Xilinx Inc. 2002.Parsing HDL and Creating MPD ...Compiling vhdl file "C:/asdf.txt/New Folder/sys1.vhd" in Library work.Entity adder_subtracter_virtex2p_7_0_86b74f94e13d0e01 compiled.Entity adder_subtracter_virtex2p_7_0_86b74f94e13d0e01 (Architectureadder_subtracter_virtex2p_7_0_86b74f94e13d0e01_a​) compiled.Package conv_pkg compiled.Package body conv_pkg compiled.Package clock_pkg compiled.Entity srl17e compiled.Entity srl17e (Architecture structural) compiled.Entity synth_reg compiled.Entity synth_reg (Architecture structural) compiled.Entity synth_reg_reg compiled.Entity synth_reg_reg (Architecture behav) compiled.Entity single_reg_w_init compiled.Entity single_reg_w_init (Architecture structural) compiled.Entity synth_reg_w_init compiled.Entity synth_reg_w_init (Architecture structural) compiled.Entity constant_5126a97a6e compiled.Entity constant_5126a97a6e (Architecture behavior) compiled.Entity constant1_c17f8d4684 compiled.Entity constant1_c17f8d4684 (Architecture behavior) compiled.Entity constant3_6080ed84a4 compiled.Entity constant3_6080ed84a4 (Architecture behavior) compiled.Entity constant7_e868161805 compiled.Entity constant7_e868161805 (Architecture behavior) compiled.Entity xladdsub compiled.Entity xladdsub (Architecture behavior) compiled.Entity constant_bd838e99a4 compiled.Entity constant_bd838e99a4 (Architecture behavior) compiled.Entity edk_processor_entity_16644e7885 compiled.Entity edk_processor_entity_16644e7885 (Architecture structural) compiled.Entity sys1 compiled.Entity sys1 (Architecture structural) compiled.Entity xland2 compiled.Entity xland2 (Architecture behavior) compiled.Entity xlclkprobe compiled.Entity xlclkprobe (Architecture behavior) compiled.Entity xlclockdriver compiled.Entity xlclockdriver (Architecture behavior) compiled.Entity sys1_clock_driver compiled.Entity sys1_clock_driver (Architecture structural) compiled.Entity sys1_cw compiled.Entity sys1_cw (Architecture structural) compiled.Compiling vhdl file "C:/asdf.txt/New Folder/sys1_sm.vhd" in Library work.Entity sys1_sm compiled.Entity sys1_sm (Architecture structural) compiled.Analyzing HDL attributes ...Done.Inferring MPD Signal Attributes and Bus Interfaces ...Done.Verifying MPD Bus Interface Specifications ...Done.Printing MPD ...INFO:MDT - IPTYPE set to value : PERIPHERALINFO:MDT - IMP_NETLIST set to value : TRUEINFO:MDT - HDL set to value : VHDL*** ERROR ***Java exception occurred: com.xilinx.sysgen.netlist.NetlistException: Unable to copy C:\Program Files\MATLAB\R2006a\work\private\sys1_EDK_Processo​r.templatecto D:\softwares\fsl interface\pcores\sys1_sm_v1_00_a\data\..\src\proc.​templatec at com.xilinx.sysgen.netlister.EDKPCoreBuilder.makeMD​DandTCL(Unknown Source) at com.xilinx.sysgen.netlister.EDKPCoreBuilder.makeED​KFiles(Unknown Source).

    **************************************************​**************************************************​****

    could you please help me to solve the problem ?

    thank you

    DB:2.77:Expoting Pcore To Edk Project p1


    Hi There :-)

    I am using Sysgen v9.1.01.

    I am trying to export sysgen module as a pcore to xilinx-edk using EDK EXPORT TOOL.

    In the compilation settings i couldn't find the "pcore under construction" and the "bus interface" caption...

    i'm reffering to sysgen v10.1.1. user guide... which has the feature of "port bus mapping"...

    While trying to compile i found the following error details,

    **************************************************​**************************************************​******************

    Begin generation Checking model status Checking simulation times Performing compilation and generation Compilation and generation completed in 11.0749 secondsExporting design as a pcoreRunning wrapper to join shared memoryRunning wrapper to create EDK filesCreating PCore files ...Writing PAO file and populating hdl directory.Writing BBD file and populating netlist directory.Writing MPD file.psfutil version Xilinx EDK 9.1.02 Build EDK_J_SP2.4Copyright (c) Xilinx Inc. 2002.Parsing HDL and Creating MPD ...Compiling vhdl file "C:/asdf.txt/New Folder/sys1.vhd" in Library work.Entity adder_subtracter_virtex2p_7_0_86b74f94e13d0e01 compiled.Entity adder_subtracter_virtex2p_7_0_86b74f94e13d0e01 (Architectureadder_subtracter_virtex2p_7_0_86b74f94e13d0e01_a​) compiled.Package conv_pkg compiled.Package body conv_pkg compiled.Package clock_pkg compiled.Entity srl17e compiled.Entity srl17e (Architecture structural) compiled.Entity synth_reg compiled.Entity synth_reg (Architecture structural) compiled.Entity synth_reg_reg compiled.Entity synth_reg_reg (Architecture behav) compiled.Entity single_reg_w_init compiled.Entity single_reg_w_init (Architecture structural) compiled.Entity synth_reg_w_init compiled.Entity synth_reg_w_init (Architecture structural) compiled.Entity constant_5126a97a6e compiled.Entity constant_5126a97a6e (Architecture behavior) compiled.Entity constant1_c17f8d4684 compiled.Entity constant1_c17f8d4684 (Architecture behavior) compiled.Entity constant3_6080ed84a4 compiled.Entity constant3_6080ed84a4 (Architecture behavior) compiled.Entity constant7_e868161805 compiled.Entity constant7_e868161805 (Architecture behavior) compiled.Entity xladdsub compiled.Entity xladdsub (Architecture behavior) compiled.Entity constant_bd838e99a4 compiled.Entity constant_bd838e99a4 (Architecture behavior) compiled.Entity edk_processor_entity_16644e7885 compiled.Entity edk_processor_entity_16644e7885 (Architecture structural) compiled.Entity sys1 compiled.Entity sys1 (Architecture structural) compiled.Entity xland2 compiled.Entity xland2 (Architecture behavior) compiled.Entity xlclkprobe compiled.Entity xlclkprobe (Architecture behavior) compiled.Entity xlclockdriver compiled.Entity xlclockdriver (Architecture behavior) compiled.Entity sys1_clock_driver compiled.Entity sys1_clock_driver (Architecture structural) compiled.Entity sys1_cw compiled.Entity sys1_cw (Architecture structural) compiled.Compiling vhdl file "C:/asdf.txt/New Folder/sys1_sm.vhd" in Library work.Entity sys1_sm compiled.Entity sys1_sm (Architecture structural) compiled.Analyzing HDL attributes ...Done.Inferring MPD Signal Attributes and Bus Interfaces ...Done.Verifying MPD Bus Interface Specifications ...Done.Printing MPD ...INFO:MDT - IPTYPE set to value : PERIPHERALINFO:MDT - IMP_NETLIST set to value : TRUEINFO:MDT - HDL set to value : VHDL*** ERROR ***Java exception occurred: com.xilinx.sysgen.netlist.NetlistException: Unable to copy C:\Program Files\MATLAB\R2006a\work\private\sys1_EDK_Processo​r.templatecto D:\softwares\fsl interface\pcores\sys1_sm_v1_00_a\data\..\src\proc.​templatec at com.xilinx.sysgen.netlister.EDKPCoreBuilder.makeMD​DandTCL(Unknown Source) at com.xilinx.sysgen.netlister.EDKPCoreBuilder.makeED​KFiles(Unknown Source).

    **************************************************​**************************************************​****

    could you please help me to solve the problem ?

    thank you

  • RELEVANCY SCORE 2.77

    DB:2.77:Edk 12.1, Cygwin 1.7 And Make 3.81 kd



    I've been using EDK and cygwin over many versions. I am familiar with the old make incompatabilities and the bash line-ending issues. I see that EDK 12.1 is using the latest version of cygwin, which is better suited to this sort of embedding, and I see that it also is shipping make 3.81. As I recall, the problem with make 3.81 was that it did not like colons in paths (e.g. C:/Xilinx/...)

    Now I am getting errors when building in the SDK, and these are due to DOS pathnames in the auto-generated *.d files which mb-gcc generates to list dependencies. I can work around this by deleting the *.d files everytime I want to build. Does Xilinx have an earlier version of make that is compatable with cygwin 1.7? Or alternately, is there a version of *-gcc that does not create dos-style paths for dependencies?







    Solved!
    Go to Solution.

    DB:2.77:Edk 12.1, Cygwin 1.7 And Make 3.81 kd


    Yeah, I'm familiar with that problem. Good luck!

  • RELEVANCY SCORE 2.77

    DB:2.77:Compiling Source Code In Linux Mode k3



    Hi all,

    I have a problem in compiling my source code in EDK,

    when I select linux as OS and set variables, I can just run libgen, and when I run bulid application, it occures one error which explains

    no boot.o file in $EDK\gnu\powerpc-eabi\nt\powerpc-eabi\lib.

    I test it in EDK 7.1 and 10.1, but result is same.

    how can I compile my source code in mvl3.1 OS mode?

    DB:2.77:Compiling Source Code In Linux Mode k3


    correct you must use the MontaVista SW suite to build a kernel.

    When Linux is selected as the OS, EDK is only used to build the BSP, it is not used to compile source code.

  • RELEVANCY SCORE 2.77

    DB:2.77:Edk 10.1 Windows 7 License Issue 1k



    Does anyone know of a problem with trying to enter the license code for EDK 10.1 under Windows 7? When I try and load my license code with 10.1 in Windows 7 it won't check EDK for installation. I know that 10.1 has issues with Win 7 but a problem with licensing seems rather strange. The license is good since I was successful inloading EDK on an XP machine.

    If Win 7 is an issue does anyone have any suggestions on loading EDK under Win 7. I'd rather not have to buy another copy of XP.

    DB:2.77:Edk 10.1 Windows 7 License Issue 1k


    Hello,

    I have windows vista and I was thinking of upgrading to windows 7. Im currently using ISE design sute 10.1 as well and I saw this thread.

    I was wondering if the library issues have been resolved? I would really rather have windows 7 as opposed to vista and I want to make sure that the transition will be worth it

    Thank you,

    J Will

  • RELEVANCY SCORE 2.77

    DB:2.77:Ho To Obtain Edk 10.1 License Via Lgeacy Licensing? cf



    Dear community,

    I have a problem regarding obtaining an EDK 10.1 license. I know this version is legacy but I need that for working with a Virtex II-based (XC2V1500) development platform. Problem is that I am able to obtain Webpack 10.1 licenses that do not cover EDK. EDK licensing is not available at all. The Webpack Reg ID is not working when I try to install EDK.

    How can I obtain a license for EDK 10.1?

    Greetz

    holy

    DB:2.77:Ho To Obtain Edk 10.1 License Via Lgeacy Licensing? cf


    Hello All,

    Check this link:http://www.xilinx.com/support/licensing_solution_c​enter.htm

    Thanks,

    Vinay




    --------------------------------------------------------------------------------------------Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

  • RELEVANCY SCORE 2.77

    DB:2.77:About Edk Update km



    Hi,

    I update my EDK from 10.1 to 11.1. I met problem with the previous project to use in the new EDK version.

    My project was based on VirtexII pro and it is not support in 11.1 anymore. Lots of error report for not compatible when EDK start.

    I try to change the device in the project option(Now I use Spartan3-E), but it generate serious error and it said to contact Xilinx support.

    Can anyone tell me how to change to new device and make the design work?

    DB:2.77:About Edk Update km

    I tried it. The design already update to 11.1 version and it can not run in 10.1 anymore....Message Edited by squaremeng on 03-08-2010 07:57 AM

  • RELEVANCY SCORE 2.77

    DB:2.77:Edk 10.1 + Modelsim Se 6.4 Simulation Problem k3



    I use ML403, EDK 10.1 and Modelsim 6.4,I want to simulate the processor and APU-FCM signals.

    Iread http://forums.xilinx.com/xlnx/board/message?board.​id=EDKthread.id=2676, and setupsmartModels.

    The problem is when compiling simulation libraries. I have 4 errors compiling EDK simulation libraries as the following:

    Modifying C:\edkprojects\ise_sim\modelsim.ini
    Executing: vcom -93 -novopt -quiet -work ddr2_v1_03_c -f C:/edkprojects/ise_sim/CompileListFiles/ddr2_v1_03​_c_compile_order

    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​ddr2_v1_03_c/hdl/vhdl/ipic_if.vhd(920): Internal error: ../../../src/vcom/genexpr.c(6444)
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​ddr2_v1_03_c/hdl/vhdl/ipic_if.vhd(920): VHDL Compiler exiting
    ERROR:: Failed to execute vcom -93 -novopt -quiet -work ddr2_v1_03_c -f C:/edkprojects/ise_sim/CompileListFiles/ddr2_v1_03​_c_compile_order :
    Compiling ddr_v2_00_c
    Executing: vlib C:/edkprojects/ise_sim/ddr_v2_00_c

    ..
    Modifying C:\edkprojects\ise_sim\modelsim.ini
    Executing: vcom -93 -novopt -quiet -work ddr2_v1_02_b -f C:/edkprojects/ise_sim/CompileListFiles/ddr2_v1_02​_b_compile_order

    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​ddr2_v1_02_b/hdl/vhdl/ipic_if.vhd(912): Internal error: ../../../src/vcom/genexpr.c(6444)
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​ddr2_v1_02_b/hdl/vhdl/ipic_if.vhd(912): VHDL Compiler exiting
    ERROR:: Failed to execute vcom -93 -novopt -quiet -work ddr2_v1_02_b -f C:/edkprojects/ise_sim/CompileListFiles/ddr2_v1_02​_b_compile_order :
    Compiling ddr2_v1_02_a
    Executing: vlib C:/edkprojects/ise_sim/ddr2_v1_02_a
    ..
    ** Error: (vcom-13) Recompile ddr2_v1_02_b.ddr2_controller because proc_common_v2_00_a.proc_common_pkg has changed.
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_01_a/hdl/vhdl/mch_opb_ddr2.vhd(177​): (vcom-1195) Cannot find expanded name "ddr2_v1_02_b.ddr2_controller".
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_01_a/hdl/vhdl/mch_opb_ddr2.vhd(360​): VHDL Compiler exiting
    ERROR:: Failed to execute vcom -93 -novopt -quiet -work mch_opb_ddr2_v1_01_a -f C:/edkprojects/ise_sim/CompileListFiles/mch_opb_dd​r2_v1_01_a_compile_order :
    Compiling mch_opb_ipif_v1_00_c
    Executing: vlib C:/edkprojects/ise_sim/mch_opb_ipif_v1_00_c
    ..
    ..
    ** Error: (vcom-13) Recompile ddr2_v1_03_c.ddr2_controller because proc_common_v2_00_a.proc_common_pkg has changed.
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_02_a/hdl/vhdl/mch_opb_ddr2.vhd(161​7): (vcom-1195) Cannot find expanded name "ddr2_v1_03_c.ddr2_controller".
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_02_a/hdl/vhdl/mch_opb_ddr2.vhd(161​7): Unknown expanded name.
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_02_a/hdl/vhdl/mch_opb_ddr2.vhd(211​2): (vcom-1195) Cannot find expanded name "ddr2_v1_03_c.ddr2_controller".
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_02_a/hdl/vhdl/mch_opb_ddr2.vhd(211​2): Unknown expanded name.
    ** Error: C:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/​mch_opb_ddr2_v1_02_a/hdl/vhdl/mch_opb_ddr2.vhd(224​3): VHDL Compiler exiting
    ERROR:: Failed to execute vcom -93 -novopt -quiet -work mch_opb_ddr2_v1_02_a -f C:/edkprojects/ise_sim/CompileListFiles/mch_opb_dd​r2_v1_02_a_compile_order :
    Compiling opb_ddr_v2_00_c
    Executing: vlib C:/edkprojects/ise_sim/opb_ddr_v2_00_c
    ..
    ..

    Modifying C:\edkprojects\ise_sim\modelsim.ini
    Executing: vcom -93 -novopt -quiet -work ddr_v2_01_b -f C:/edkprojects/ise_sim/CompileListFiles/ddr_v2_01_​b_compile_order

    Compilation completed, 4 errors.

    DB:2.77:Edk 10.1 + Modelsim Se 6.4 Simulation Problem k3

    Did you ever figure this out? Seems like most simulation questions go unanswered. Does anyone actually do this, or is it that simulation people are just keeping their secrets close to the vest???

  • RELEVANCY SCORE 2.76

    DB:2.76:Edk Simulation Problems / Error In 12.1 ! fp


    Hello all,

    DO NOT simulate MB EDK designs in 12.1 !!!

    Just for the record:

    When simulating a MB EDK design in 12.1 (with the program stored in local BRAM) it will simply not work.

    The problem is known and explained in AR# 36026 -- and the patch provided works.

    It is also supposedly solved in 12.2.

    Regards,

    Cristian







    Solved!
    Go to Solution.

    DB:2.76:Edk Simulation Problems / Error In 12.1 ! fp


    I checked the CR associated with the AR and this is fixed in 12.2 which is now available from the download page.

  • RELEVANCY SCORE 2.76

    DB:2.76:Stop Recompilation Of Edk When Moving Project To Lab Computer 17



    Hi,

    Whenever I move a EDK Project from my desk computer to a Lab Computer EDK will not accept my compiled EDK project as is.

    It will recompile the project when I select download bitfile in EDK Gui. Is there a way to stop automatically compiling the bitstream again.

    Thank You,

    Gary Olson

    DB:2.76:Stop Recompilation Of Edk When Moving Project To Lab Computer 17


    Hi andrew,

    Thank you for the reply. I will look into the make file approach.

    I work in Windows environment.

    Gary

  • RELEVANCY SCORE 2.76

    DB:2.76:Hdl Parser Errors In User_Logic File ps



    I am trying to create IP named scheduler. I modified user_logic.vhdl file to make it top level module and to interface it with bus.I added sub modules like infer_bram.vhdl and parallel.vhdl in .pao file.And it look like this

    ib proc_common_v1_00_b ld_arith_reg vhdllib proc_common_v1_00_b ld_arith_reg2 vhdllib proc_common_v1_00_b down_counter vhdllib proc_common_v1_00_b inferred_lut4 vhdllib proc_common_v1_00_b or_muxcy vhdllib proc_common_v1_00_b or_gate v

    .

    .

    .

    .

    .

    lib opb_ipif_v2_00_h master_attachment vhdllib opb_ipif_v2_00_h opb_ipif vhdllib scheduler_v1_00_a parallel vhdllib scheduler_v1_00_a infer_bram vhdllib scheduler_v1_00_a user_logic vhdllib scheduler_v1_00_a scheduler vhdl

    ----------------

    So while importing this IP as existing peripheral ,this report comes

    -------------------

    Parsing PAO project file successfully ...Analyzing HDL source files ...Analyzing HDL source files successfully ...HDL language for the peripheral (top level) design unit scheduler is vhdl ...WARNING:MDT - Project file C:\demo2\pcores/scheduler.prj already exists, will be overwrite and removed afterward ...INFO:MDT - Create temparary xst project file: C:\demo2\pcores/scheduler.prjCompiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v1_00_b.Entity or_muxcy compiled.Entity or_muxcy (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v1_00_b.Package proc_common_pkg compiled.WARNING:HDLParsers:3534 - "D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hd l/vhdl/proc_common_pkg.vhd" Line 364. In the function Get_RLOC_Name, not all control paths contain a return statement.WARNING:HDLParsers:3534 - "D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hd l/vhdl/proc_common_pkg.vhd" Line 379. In the function Get_Reg_File_Area, not all control paths contain a return statement.Package body proc_common_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/direct_path_cntr.vhd" in Library proc_common_v1_00_b.Entity direct_path_cntr compiled.Entity direct_path_cntr (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo.vhd" in Library proc_common_v1_00_b.Entity SRL_FIFO compiled.Entity SRL_FIFO (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v1_00_b.Entity srl_fifo2 compiled.Entity srl_fifo2 (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v1_00_b.Entity srl_fifo_rbu compiled.Entity srl_fifo_rbu (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd" in Library proc_common_v1_00_b.Entity pselect compiled.Entity pselect (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v1_00_b.Entity ld_arith_reg compiled.Entity ld_arith_reg (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg2.vhd" in Library proc_common_v1_00_b.Entity ld_arith_reg2 compiled.Entity ld_arith_reg2 (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/down_counter.vhd" in Library proc_common_v1_00_b.Entity down_counter compiled.Entity down_counter (Architecture simulation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd" in Library proc_common_v1_00_b.Entity or_gate compiled.Entity or_gate (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/family.vhd" in Library proc_common_v1_00_b.Package family compiled.Package body family compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/proc_common_v1_00_b/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v1_00_b.Entity inferred_lut4 compiled.Entity inferred_lut4 (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_bit.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter_bit compiled.Entity pf_counter_bit (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder_bit.vhd" in Library opb_ipif_v2_00_h.Entity pf_adder_bit compiled.Entity pf_adder_bit (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter compiled.Entity pf_counter (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter.vhd" in Library opb_ipif_v2_00_h.Entity pf_occ_counter compiled.Entity pf_occ_counter (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ipif_pkg.vhd" in Library ipif_common_v1_00_d.Package ipif_pkg compiled.Package body ipif_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter_top.vhd" in Library opb_ipif_v2_00_h.Entity pf_occ_counter_top compiled.Entity pf_occ_counter_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_top.vhd" in Library opb_ipif_v2_00_h.Entity pf_counter_top compiled.Entity pf_counter_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder.vhd" in Library opb_ipif_v2_00_h.Entity pf_adder compiled.Entity pf_adder (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_dly1_mux.vhd" in Library opb_ipif_v2_00_h.Entity pf_dly1_mux compiled.Entity pf_dly1_mux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg.vhd" in Library ipif_common_v1_00_d.Entity dma_sg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ctrl_reg.vhd" in Library ipif_common_v1_00_d.Entity ctrl_reg compiled.Entity ctrl_reg (Architecture sim) compiled.Entity ctrl_reg_0_to_6 compiled.Entity ctrl_reg_0_to_6 (Architecture sim) compiled.Entity ctrl_reg_0_to_0 compiled.Entity ctrl_reg_0_to_0 (Architecture sim) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/burst_size_calc.vhd" in Library ipif_common_v1_00_d.Entity burst_size_calc compiled.Entity burst_size_calc (Architecture imp) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_cmp.vhd" in Library ipif_common_v1_00_d.Package dma_sg_cmp compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_pkg.vhd" in Library ipif_common_v1_00_d.Package dma_sg_pkg compiled.Package body dma_sg_pkg compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_wr.vhd" in Library opb_ipif_v2_00_h.Entity ipif_control_wr compiled.Entity ipif_control_wr (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_dp_cntl.vhd" in Library opb_ipif_v2_00_h.Entity wrpfifo_dp_cntl compiled.Entity wrpfifo_dp_cntl (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/pf_dpram_select.vhd" in Library opb_ipif_v2_00_h.Entity pf_dpram_select compiled.Entity pf_dpram_select (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/srl16_fifo.vhd" in Library opb_ipif_v2_00_h.Entity srl16_fifo compiled.Entity srl16_fifo (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_rd.vhd" in Library opb_ipif_v2_00_h.Entity ipif_control_rd compiled.Entity ipif_control_rd (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_dp_cntl.vhd" in Library opb_ipif_v2_00_h.Entity rdpfifo_dp_cntl compiled.Entity rdpfifo_dp_cntl (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ipif_reset.vhd" in Library opb_ipif_v2_00_h.Entity ipif_reset compiled.Entity ipif_reset (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/interrupt_control.vhd" in Library ipif_common_v1_00_d.Entity interrupt_control compiled.Entity interrupt_control (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/ipif_steer.vhd" in Library ipif_common_v1_00_d.Entity IPIF_Steer compiled.Entity IPIF_Steer (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_sim.vhd" in Library ipif_common_v1_00_d.Entity dma_sg (Architecture sim) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_dmux.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_dmux compiled.Entity ip2bus_dmux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_srmux compiled.Entity ip2bus_srmux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/addr_load_and_incr.vhd" in Library opb_ipif_v2_00_h.Entity addr_load_and_incr compiled.Entity addr_load_and_incr (Architecture implementation) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/parall​el.vhd" inLibrary scheduler_v1_00_a.Entity parallel compiled.Entity parallel (Architecture imp) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/infer_​bram.vhd"in Library scheduler_v1_00_a.Entity infer_bram compiled.Entity infer_bram (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/master_attachment.vhd" in Library opb_ipif_v2_00_h.Entity master_attachment compiled.Entity master_attachment (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/address_decoder.vhd" in Library opb_ipif_v2_00_h.Entity address_decoder compiled.Entity address_decoder (Architecture IMP) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux_blk.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_srmux_blk compiled.Entity ip2bus_srmux_blk (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/bus2ip_amux.vhd" in Library opb_ipif_v2_00_h.Entity bus2ip_amux compiled.Entity bus2ip_amux (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_dmux_blk.vhd" in Library opb_ipif_v2_00_h.Entity ip2bus_dmux_blk compiled.Entity ip2bus_dmux_blk (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/slave_attachment.vhd" in Library opb_ipif_v2_00_h.Entity slave_attachment compiled.Entity slave_attachment (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/reset_control.vhd" in Library opb_ipif_v2_00_h.Entity reset_control compiled.Entity reset_control (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_top.vhd" in Library opb_ipif_v2_00_h.Entity rdpfifo_top compiled.Entity rdpfifo_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/wrpfifo_top.vhd" in Library opb_ipif_v2_00_h.Entity wrpfifo_top compiled.Entity wrpfifo_top (Architecture implementation) compiled.Compiling vhdl file"D:/Xilinx/10.1/EDK/EDK/hw/XilinxProcessorIPLib/pc​ores/opb_ipif_v2_00_h/hdl/vhdl/opb_ipif.vhd" in Library opb_ipif_v2_00_h.Entity opb_ipif compiled.Entity opb_ipif (Architecture implementation) compiled.Compiling vhdl file "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd"in Library scheduler_v1_00_a.Entity user_logic compiled.ERROR:HDLParsers:164 - "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd" Line 431. parse error, unexpected FUNCTIONERROR:HDLParsers:164 - "C:/demo2/pcores/scheduler_v1_00_a/hdl/vhdl/user_l​ogic.vhd" Line 431. parse error, unexpected CLOSEPAR, expecting OPENPAR or TICK or LSQBRACKERROR:MDT - Parse Errors encountered in HDL source WARNING:MDT - Unable to delete temparary project file C:\demo2\pcores\scheduler.prj : 13

    ------------

    where the 431 line in my user_logic file starts from here "function"

    -------------

    function is_encoder_bit_zero(pri_index: integer; e_entry: std_logic_vector(0 to INPUT_BITS-1)) return boolean isbegin if (e_entry(pri_index) = '0') then return true; else return false; end if;end function is_encoder_bit_zero;

    --------------

    what's wrong with it????? can anybody tell me a solution to this problem???

    nasim







    Solved!
    Go to Solution.

    DB:2.76:Hdl Parser Errors In User_Logic File ps

    thanx it worked.I was actually using semiclon instead of comma in port map.

  • RELEVANCY SCORE 2.74

    DB:2.74:Problem With Edk And Bluecat mj


    Hi,

    I get following error while trying to generate libraries and
    BSPs in EDK

    #--------------------------------------
    ERROR:MDT - linux_bc54 () - Error: Target directory does not
    exist.

    while executing

    "error
    "Error: Target directory does not exist.""

    (procedure
    "::sw_linux_bc54_v1_00_a::linux_drc" line 30)

    invoked from
    within

    "::sw_linux_bc54_v1_00_a::linux_drc 66343224"

    ERROR:MDT - Error while running DRC for processor
    microblaze_0...

    make: *** [microblaze_0/lib/libxil.a] Error 2

    #--------------------------------------

    Is there something I forget when I configured the environment?

    I am using EDK 10.1.03 in windows and BlueCat ME 5.4.3.

    Thanks

    DB:2.74:Problem With Edk And Bluecat mj


    Hi,

    1. the directory path may be incorrect. should be this slash / not \

    or

    2. you need to change the default linux path to linux.ml405 or linux.ml507 in the tcl under the bsp directory

    Regards

    TOM

  • RELEVANCY SCORE 2.74

    DB:2.74:Problem With Edk - Variable Missing Value 7d


    Hi, I was compiling the following code and worked fine :

    inline UINT8Set_register_en (UINT8 value){

    UINT16 reg_value;

    UINT16 mask;

    i2c_rd_16_16 (0x22, 0x0000, reg_value, 1);

    xil_printf("READ VALUE%d\r\n", reg_value);

    mask = ~(( (1 1) - 1 ) 1 );

    reg_value = reg_value mask;

    mask = (value) 1;

    reg_value = reg_value | mask;

    xil_printf("READ VALUE%d\r\n", reg_value);

    i2c_wr_16_16 (0x22, 0x0000, reg_value, 1);

    }

    But when I delete the xil_printf lines, reg_value gets 0 instead of the expected read value,

    makes no sense to me cause it's only a printf what I'm deleting ...

    Actually, if I print mask instead of reg_value, works fine as well, And just one xil_print

    is needed ... any suggestion?

    Thanks.

    DB:2.74:Problem With Edk - Variable Missing Value 7d

    Hi, I was compiling the following code and worked fine :

    inline UINT8Set_register_en (UINT8 value){

    UINT16 reg_value;

    UINT16 mask;

    i2c_rd_16_16 (0x22, 0x0000, reg_value, 1);

    xil_printf("READ VALUE%d\r\n", reg_value);

    mask = ~(( (1 1) - 1 ) 1 );

    reg_value = reg_value mask;

    mask = (value) 1;

    reg_value = reg_value | mask;

    xil_printf("READ VALUE%d\r\n", reg_value);

    i2c_wr_16_16 (0x22, 0x0000, reg_value, 1);

    }

    But when I delete the xil_printf lines, reg_value gets 0 instead of the expected read value,

    makes no sense to me cause it's only a printf what I'm deleting ...

    Actually, if I print mask instead of reg_value, works fine as well, And just one xil_print

    is needed ... any suggestion?

    Thanks.

  • RELEVANCY SCORE 2.74

    DB:2.74:Edk 97



    Hi, I am a learner in EDK. I started designing a simple microblaze processor based design, in which i had added 5 leds, and now i am facing a problem to write the source code for it to ON the leds. Can any one please help me out to solve this.

    DB:2.74:Edk 97


    I would recommend running throughBase System Builder, and adding the LEDs that way. When you export to SDK, (of if you don't earlier than 12.x), there is an example Xilinx C Project titled "Peripheral Test". In there, if you have the LEDs, it will have an example C code showing you how to access the registers to write high and low signals to them.

    If you have a custom board, and are using GPIO, you might want to look at the datasheet for GPIO (under the EDK/hw/XilinxProcessorIPLib/pcores/[xps/axi]_gpio_​vx_xx_[a/b] to see where the registers are, and how to write to them with XMD, or you can try using the GPIO drivers found under EDK/sw/XilinxProcessorIPLib/drivers/gpio_vx_xx_[a/​b]

  • RELEVANCY SCORE 2.74

    DB:2.74:Problem On Installing Edk ap


    hi,

    i have xilinx ISE 9.2i and EDK 9.1i software. i installed both in my system in different location i.e for ISE(C:\program files\Xilinx ISE9.2i) and for EDK(C:\program files\EDK). i successfully installed both. but whenever i am trying to open EDK it shows "you doesnot point to xilinx ISE9.1i installation.. press any key to exit"

    i cant solve this problem and alsocant use the EDK softyware. if anyone know the solution for this pls help me..

    thankyou.
    with regards,
    albin viju.

    DB:2.74:Problem On Installing Edk ap


    George is correct.

    Here are the official respective version requirements for EDK:
    http://www.xilinx.com/ise/embedded/edk_download.htm

    If you do not have a 9.1i boxed set, you can login into Electronic Fulfillment Center:
    http://www.xilinx.com/ise/esd/
    You can send an email to Xilinx Customer Support (not Xilinx Technical Support, there is a correct link here once you login) and request access to ISE 9.1i and provide your ISE 9.2i product ID. Ask to be "entitled" to the older version because of EDK requirements. You should then receive download access to ISE 9.1i once this has been approved.

    To answer a logical follow-on question, I can't speak to the planned release dateof EDK 9.2.

    I also generally recommend not installing the tools or projects into directories with spaces in the path - including "Program Files", a user profile or desktop locations. I don't know the current official stance of "spaces in the path" support, but historically this has caused issues because spaces are a separator between command line arguments (which is still important even if you are using the GUIs). I think this is handled better now, but I still try to avoid it.

    Cheers,
    bt

    == minor fixMessage Edited by timpe on 10-16-2007 09:57 AM

  • RELEVANCY SCORE 2.73

    DB:2.73:What Is The Meaning To Combine The Edk Processor And System Generator?? fa



    I am new to the edk processor and I just finished the RGB2Gray example provided by System Generator User Guide. After doing it, one problem came out and confused mea lot: why do we add the EDK Processor into System Generator Design?

    During the RGB2GRAY process, after generating the pcores from System Generator and connecting it to MicroBlaze project, what we do is to send a serial number to the pcores and read the result to test byrunning theC code we run on the MicroBlaze. Do I understand it correstly?We build EDK project and connect the pcores we generated from System Generator is just for Testing whether it is correctly designed in System Generator?? If that is true, why not we test it in System Generator withmanykinds of choices and scope??

    Building EDK projectmay cost a lot of trouble and is quite time-consuming. If it is just for testing result in EDK, I don't think it is a wise method.

    Another problem I want to ask for help is that after generating the pcores from System Generator and connecting with the MicroBlaze, can we change the parameters in our System Generator Design only by using the C code??? I mean can we write some control operations to change the design rather than writing send data and read data. If possible, how to write?

    Many Thanks for guys answer my post.

    DB:2.73:What Is The Meaning To Combine The Edk Processor And System Generator?? fa


    I am new to the edk processor and I just finished the RGB2Gray example provided by System Generator User Guide. After doing it, one problem came out and confused mea lot: why do we add the EDK Processor into System Generator Design?

    During the RGB2GRAY process, after generating the pcores from System Generator and connecting it to MicroBlaze project, what we do is to send a serial number to the pcores and read the result to test byrunning theC code we run on the MicroBlaze. Do I understand it correstly?We build EDK project and connect the pcores we generated from System Generator is just for Testing whether it is correctly designed in System Generator?? If that is true, why not we test it in System Generator withmanykinds of choices and scope??

    Building EDK projectmay cost a lot of trouble and is quite time-consuming. If it is just for testing result in EDK, I don't think it is a wise method.

    Another problem I want to ask for help is that after generating the pcores from System Generator and connecting with the MicroBlaze, can we change the parameters in our System Generator Design only by using the C code??? I mean can we write some control operations to change the design rather than writing send data and read data. If possible, how to write?

    Many Thanks for guys answer my post.

  • RELEVANCY SCORE 2.73

    DB:2.73:Edk And Cache Coherency c1



    Does EDK support Cache Coherency?

    DB:2.73:Edk And Cache Coherency c1


    i,

    Cache coherence has to do with multiple processors using their own caches, and communication to a common memory.

    No, MicroBlaze(tm), and the 4XX PPC do not have cache coherence.

    The ARM dual A9 Cortex, does. So in Zynq, it is supported.

    If you build a dual proceessor, dual cache, shared main memory, from two MB, or PPC, then you have to build the cache coherence (controller) yourself.

    If you use Zynq, Xilinx and ARM have done it for you.




    Austin LeseaPrincipal EngineerXilinx San Jose

  • RELEVANCY SCORE 2.73

    DB:2.73:Isim With Edk x8



    Can anybody school me on the proper way to run a simulation under ISIM when using EDK? Here's my situation:

    I have an EDK project in which I've created a custom IP core, "mycore". I instantiated a MicroBlaze system and customized it in XPS. (I'm using ISE/EDK 13.4, Win7, 64bit, Virtex6 custom board). I want to simulate just the core, so I've written a test bench, "mytest_t.v". If I make a separate ISE project with just the mycore HDL sources, I can simulate it in ISIM no problem. But if I copy mycore_t.v into my main project, Project Navigator cannot find the mycore.v sources. If I try to add them, PN says they are already there and won't let me add them again.

    I work around this by using a separate project, but I've confused myself a couple of times and wasted a 4-hour compile by compiling different code than I simulated... Seems like there must be a proper way to do this that makes it more idiot-proof.

    Thanks for any help.

    Rick

    DB:2.73:Isim With Edk x8


    Already tried that, no help.

  • RELEVANCY SCORE 2.72

    DB:2.72:Edk License Problem a3



    My old computer is dying so I've got a new one and I'mtrying to install 10.1 but when I enter the license number EDK is not selected. This is the number off my documentation and is what is on the old computer. Any ideas?

    DB:2.72:Edk License Problem a3

    The number on the DVD box is likely the Product ID. This was registered by you via the web and they likely sent you a registration ID by email . For 10.1 this is a 25 digit alpha numeric number and was the same for the unified installer (past versions like 9.2i used a 16 digit numerical reg ID for ISE, a different one for EDK, etc.)

    You may have an email from then with the number still archived.

    If your old computer is still working, you should be able to see this reg ID in the Help - About box of ProjNav, XPS. Also in xinfo (under the ISE accessories menu)

    You can also likely check with Development Software Customer Service, isscs@xilinx.com, if you still have issues.

    bt

  • RELEVANCY SCORE 2.72

    DB:2.72:Regression On Hardware Error 97


    hi ,
    when i tried to run the regression
    xtclsh rundiags.tcl -edk /home/netuser/m070269ec/open_sparc/design/sys/edk -d diags -list thread1_mini.list -model core1 -suite thread1_mini xbash -override
    I got the error
    ############New Run##############

    Date : 03/25/09

    *#### Start processing diag : bypass_win*
    *#### Memory image mbfw_diag_memimage.c Found*
    *#### Path: diags/core1/thread1_mini/bypass_win/mbfw_diag_memimage.c*
    *#### Previous executable not found ####*
    *#### Error in compiling new firmware source files -- couldn't execute "xbash": no such file or directory*
    Warning: bypass_win not processed
    *#### Start processing diag : chase_l1hit*
    *#### Memory image mbfw_diag_memimage.c Found*
    for all the files....
    I am able to run sims and got diags directory and mbfw_diag_memimage.c in each folder...
    is it the problem with xtclsh???

    please help me to solve the problem

    DB:2.72:Regression On Hardware Error 97

    Hi,

    I've solved the problem by doing two little modifications on the script file "rundiags.tcl". If you're not working on a windows os, you'll not need the two calls to xbash. You can modify your rundiags.tcl to skip these calls. Add also '21' where 'impact' is used. It'll perform a simple redirection as discussed on the topic 'regression on hardware' :

    Do that

    *if { [catch { exec impact -batch etc/download.cmd 21 } msg] } {*

    instead of

    *if { [catch { exec xbash -q -c "cd $parentdir; \*
    *impact -batch etc/download.cmd; exit;" } msg] } {*

    Proceed the same way for the other calls of 'xbash' and 'impact' in this file.

  • RELEVANCY SCORE 2.71

    DB:2.71:Workshop Not Compiling Web-Inf/Src 87


    How can I get Workshop to compile .java source in WEB-INF/src to WEB-INF/classes? I've tried building project and building application.

    Thanks.

    DB:2.71:Workshop Not Compiling Web-Inf/Src 87

    How can I get Workshop to compile .java source in
    WEB-INF/src to WEB-INF/classes? I've tried building
    project and building application.

    Thanks.This has to do with split directory development structure: http://e-docs.bea.com/wls/docs81/programming/environment.html#1097239

    Check out .beabuild.txt file in your application directory.

  • RELEVANCY SCORE 2.71

    DB:2.71:Problem Of Compling Simulation Libraries With Nc-Sim jf



    I try to compile the ise and edk library using ncsim, but the compxlib fails, it gives the following error message

    -- Compiling verilog unisim libraryERROR:CAEInterfaces:315 - COMPXLIB[lib]: unable to find 'tools' directory under /homeToolTip: create a link named 'tools' under /home pointing to the path containing 'inca' sub-directory.

    The compedklib give a lot of error messages like:

    ncvhdl_p: *E,ERRIPR: error within protected source code.

    The ise and edk version is 9.1i and the ncsim version is 6.1.

    All softwares are running on a linux server, so I don't have the permission to change anything at /home

    Anyone has a clue about this ?
    Thanks in advance.

    DB:2.71:Problem Of Compling Simulation Libraries With Nc-Sim jf


    I try to compile the ise and edk library using ncsim, but the compxlib fails, it gives the following error message

    -- Compiling verilog unisim libraryERROR:CAEInterfaces:315 - COMPXLIB[lib]: unable to find 'tools' directory under /homeToolTip: create a link named 'tools' under /home pointing to the path containing 'inca' sub-directory.

    The compedklib give a lot of error messages like:

    ncvhdl_p: *E,ERRIPR: error within protected source code.

    The ise and edk version is 9.1i and the ncsim version is 6.1.

    All softwares are running on a linux server, so I don't have the permission to change anything at /home

    Anyone has a clue about this ?
    Thanks in advance.

  • RELEVANCY SCORE 2.71

    DB:2.71:Cygwin Problem In Edk 9.2i mz


    Hey all,I am running EDK 9.2i on windows vista and when I download the bitstream to a board this is what I get:At Local date and time: Thu Feb 07 19:47:22 2008xbash -q -c "cd /cygdrive/c/IMAGE_PROCESSOR/; /usr/bin/make -f IMAGE_PROCESSOR.make download; exit;" started...mount: /usr/bin: Permission deniedmount: /usr/lib: Permission deniedmount: /: Permission deniedmount: /cygdrive: Permission deniedbash.exe: warning: could not find /tmp, please create!Installing Cygwin from EDK installation area...Added registry entries for C:\EDK\cygwin/cygdrive/c/EDK/cygwin/bin/bash: /usr/bin/make: No such file or directoryDone!Anyone else have this problem or know of a solution? Thanks!Paul

    DB:2.71:Cygwin Problem In Edk 9.2i mz

    Paul,Try this answer record:http://www.xilinx.com/support/answers/25492.htmHowever, Vista is not a supported OS so your mileage may vary.SteveMessage Edited by elzinga on 02-11-2008 08:01 AM

  • RELEVANCY SCORE 2.71

    DB:2.71:Problem In Using Modelsim 6.5b Student Edition With Edk 11 fp



    Hi

    I am using EDK and xilkernel for my project.

    I am trying to "compile simulation libraries" from simulation menu in EDK for Modelsim 6.5 student edition. But it is giving errors in "Compiling Simulation Libraries wizard".

    Dowe have to install Modelsim in some particular directory of EDK?

    Dowe have to provide Path of modelsim.exe in "Edit-Preferences-simulation"? (I did this but still not working)

    It shows 7 errors. ISE libraries compile but EDK libraries are not compiling.

    Are there any steps that are to be taken while installing Modelsim?

    Basically, How do we use modelsim with EDK for simulation? Is there any good document??







    Solved!
    Go to Solution.

    DB:2.71:Problem In Using Modelsim 6.5b Student Edition With Edk 11 fp


    Hi,

    i have this problem with the Simulation libraries compilation

    ____ ____

    / /\/ /

    /___/ \ / VENDOR : Xilinx Inc.

    \ \ \/ VERSION : 11.1 (L.33)

    \ \ APPLICATION : C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe

    / / CONTENTS : Compilation Log

    /___/ /\ FILENAME : compxlib.log

    \ \ / \

    \___\/\___\

    Release 11.1 - C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe L.33 (nt)

    Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

    Processing command line ...

    Reading the compxlib configuration file - 'compxlib.cfg' ...

    Library Source Paths = 'C:/Xilinx/11.1/ISE'

    Current Working Directory = 'C:\Documents and Settings\ruizmartinez\My Documents\RuizMartinez\ISE projects\Prueba1'

    Compilation Mode = FAST

    Execute Mode = ON

    Scheduling library installation compilation for architectures: virtex5

    Scheduling library installation compilation for libraries: simprim unisim xilinxcorelib edk

    Signature:-

    --------------------------------------------------​----------------------------

    C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe -s mti_se -l vhdl -p C:/ModelSimSE65/win32 -arch virtex5 -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise

    --------------------------------------------------​----------------------------

    Setting up the simulator 'mti_se' for compilation ...

    Setting up the source libraries for simulator 'mti_se' ...

    Retrieving the .pao files for EDK library ...

    Building the library hierarchies from the .pao files for EDK library ...

    Assigning the netlist files to the hierarchies for EDK library ...

    Compiling Xilinx HDL Libraries for 'mti_se' simulator

    Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22 2009

    Language = 'vhdl,verilog'

    Output directory = 'C:\Xilinx\11.1\ISE'

    Library verilog.secureip will not be compiled, because precompiled info is up to date.

    compxlib[verilog.secureip]: 0 error(s), 0 warning(s), 12.50 % complete

    Library vhdl.unisim will be compiled, because precompiled info is outdated.

    -- Compiling vhdl.unisim library ...

    vhdl.unisim library compiled from C:/Xilinx/11.1/ISE/vhdl/src/unisims

    vhdl.unisim library compiled to C:\Xilinx\11.1\ISE\vhdl\mti_se/unisim

    ==================================================​============================

    Modifying modelsim.ini

    p, li { white-space: pre-wrap; }

    ==================================================​============================

    Log file 'C:\Xilinx\11.1\ISE\vhdl\mti_se/unisim/.cxl.vhdl.u​nisim.unisim.nt.log' generated

    Library vhdl.unisim:vhdl.unimacro will be compiled, because precompiled info is outdated.

    -- Compiling vhdl.unisim:vhdl.unimacro library ...

    vhdl.unisim:vhdl.unimacro library compiled from C:/Xilinx/11.1/ISE/vhdl/src/unimacro

    vhdl.unisim:vhdl.unimacro library compiled to C:\Xilinx\11.1\ISE\vhdl\mti_se/unimacro

    ==================================================​============================

    Modifying modelsim.ini

    Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22 2009

    -- Loading package standard

    -- Loading package std_logic_1164

    -- Loading package numeric_std

    -- Loading package std_logic_arith

    -- Loading package std_logic_unsigned

    -- Loading package vcomponents

    -- Loading package textio

    -- Compiling entity addmacc_macro

    -- Compiling architecture addmacc of addmacc_macro

    ###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(296): DSP48E_1: DSP48E1

    ** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(296): (vcom-1141) Identifier "dsp48e1" does not identify a component declaration.

    ###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(361): DSP48E_2: DSP48A1

    ** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(361): (vcom-1141) Identifier "dsp48a1" does not identify a component declaration.

    ###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(405): end addmacc;

    ** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO​.vhd(405): VHDL Compiler exiting

    I don't know if the spaces in the directory is the problem ....

    Thank you very much in advance for your help ...

    Emilio

  • RELEVANCY SCORE 2.71

    DB:2.71:Problems Compiling Simulation Libraries In Xps m8



    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

    DB:2.71:Problems Compiling Simulation Libraries In Xps m8


    I'm trying to reproduce the test drives in "EDK Concepts, Tools, and Techniques", but when it comes to simulation, when I try to compile the simulation libraries i get the following errors:

    - Compiling the ISE libraries shows 1 error, but the log file just ends with a "Compiling verilog unisim library ..." and nothing more.

    - Compiling EDK libraries I get lots or errors similar to: "
    Modifying C:\complibe\modelsim.iniExecuting: vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(76): Library unisim not found.** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(77): (vcom-1136) Unknown identifier "unisim".** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/util_flipflo​p_v1_10_a/hdl/vhdl/util_flipflop.vhd(79): VHDL Compiler exitingERROR:: Failed to execute vcom -93 -quiet -work util_flipflop_v1_10_a -f C:/complibe/CompileListFiles/util_flipflop_v1_10_a​_compile_order : Compiling microblaze_v5_00_cExecuting: unzip -q -o C:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v​5_00_c/simmodels/mti_vhdl.zip -d C:/complibe

    But I still can generate Simulation HDL files succesfully. Then I run ModelSim and type "c" and everything seems to run OK until I get "

    # -- Loading package std_logic_1164# ** Error: (vcom-11) Could not find proc_common_v2_00_a.inferred_lut4.# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(96): (vcom-1195) Cannot find expanded name "proc_common_v2_00_a.inferred_lut4".# -- Loading package vcomponents# ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_0​1_b/hdl/vhdl/pf_dly1_mux.vhd(107): VHDL Compiler exiting# ** Error: D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed.# Error in macro ./system.do line 70# D:/Modeltech_pe_edu_6.4b/win32pe_edu/vcom failed."

    I use ISE and EDK 9.1 updated to the latest SPs, and ModelSim PE Student Edition 6.4b.

    Any kind of help would be appreciated.

  • RELEVANCY SCORE 2.70

    DB:2.70:Platgen Error x7



    hi

    I am new to EDK10.1 Version. I am facing problem when I am building my project in EDK

    I used base system builder as my start, I select ML402 board and i select some peripherals after compliting base system builder, I tryed to build the hardware, the platgen giving error with message error in speed grade -10 but ML402 contain the device with speed grade -10

    Please any one tell what the problem and the solution

    thanx

    DB:2.70:Platgen Error x7

    What is the speed grade thatPlatgen defaults to. Perhaps it really does notmatter what speed grade Platgen uses.Message Edited by golson on 06-16-2008 12:24 PM

  • RELEVANCY SCORE 2.70

    DB:2.70:Compiling Errors After Upgrading From Edk9.1 To Edk9.2 kd


    Hi,

    After upgrading from EDK9.1 to EDK 9.2, I get compilation warnings which eventualy are responsible for the failure of the .elf creation.
    The warnings are on the call to the function "sprintf" with a warning" incompatible implicit declaration of built-in function 'sprintf' "

    After marking the calles to the function, the project compiled OK, and the .elf was created.
    I should mention that all the drivers and BSP has been rebuild automaticaly (and I did it again even after that - just to be sure).

    Has any one encountered this problem? any help appreciated.

    Thanks,
    Eli

    DB:2.70:Compiling Errors After Upgrading From Edk9.1 To Edk9.2 kd

    Hi,

    After upgrading from EDK9.1 to EDK 9.2, I get compilation warnings which eventualy are responsible for the failure of the .elf creation.
    The warnings are on the call to the function "sprintf" with a warning" incompatible implicit declaration of built-in function 'sprintf' "

    After marking the calles to the function, the project compiled OK, and the .elf was created.
    I should mention that all the drivers and BSP has been rebuild automaticaly (and I did it again even after that - just to be sure).

    Has any one encountered this problem? any help appreciated.

    Thanks,
    Eli

  • RELEVANCY SCORE 2.69

    DB:2.69:Edk 10.1 Sp1, Uart Lite Does Not Work At All!!!! ( Ml403 ) s7



    Hi

    again another streng problem with new EDK 10.1

    I make a simple base system including XPS UART LITE module,

    After implementation, and building the software ( which is the sample generated by EDK itself )

    I make an ACE file and copy the file into compact flash.

    When I turn the ML403 board on, nothing happens in the terminal program

    -- FPGA Done pin goes high

    -- I'm sure that serial connection to PC is working

    -- The same design works easily in EDK 9.2

    -- I have enabled the "Mark to initialize BRAM" for the sample application generated by EDK

    -- I checked the results of implementation, there were no timing errors

    The same happens when i build a Linux kernel image and a base system usig EDK 10.1

    previous designs on 9.2 were working correctly.

    :) it seems that the release 10.1 has more bugs than expected, even with SP1.

    DB:2.69:Edk 10.1 Sp1, Uart Lite Does Not Work At All!!!! ( Ml403 ) s7


    Investigate your UART Parameters see if you can adjust them. By decreasing your clock you likely changed the baud rate of the UART.

    See if you can change the divider value or whatever they call it to get your baud rate the way it was before.

  • RELEVANCY SCORE 2.69

    DB:2.69:Xilinx Spartan Video Kit And Edk 10.1 8z



    Hi,

    when I try to build the Camera Frame Buffer application on the Spartan Video Kit (spartan3adsp, xc3sd3400a, fg676) with Platform Studio (10.1.03), I get the error "Invalid target package 'fg676'". So, what's the problem? Doesn't EDK 10.1 accept this board? That's the version of EDK that I received together with the kit and the XilinxUpdate has no available updates. Should i try EDK 11?

    Thanks.

    DB:2.69:Xilinx Spartan Video Kit And Edk 10.1 8z

    Thanks for the reply. Now you really scared me. I bought this board exactly because I need something already working and don't want to write my own cores, drivers etc for the camera. I guess this is just another fine example of Xilinx's exceptional talent at making a mess out of seemingly simple things.

  • RELEVANCY SCORE 2.69

    DB:2.69:Error Building For The Ml507 With Edk 10.1 k8


    i’m using edk 10.1.02(nt) – edk_k_sp2.5+0 version and i’m trying to go through the online tutorial (http://www.xilinx.com/products/boards/ml507/files/ml507_bsb_design_ppc440.zip) and i keep getting the following error when trying to “generate libraries and bsps”:At Local date and time: Fri Aug 15 12:19:29 2008 make -f ml507_bsb_system.make libs started...*********************************************Creating software libraries...*********************************************libgen -mhs ml507_bsb_system.mhs -p xc5vfx70tff1136-1 ml507_bsb_system.mss libgen Xilinx EDK 10.1.02 Build EDK_K_SP2.5 Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.ERROR: MDT - Invalid target speed '-1'make: *** [ppc440_0/lib/libxil.a] Error 2 Done!any ideas what could be wrong?

    DB:2.69:Error Building For The Ml507 With Edk 10.1 k8

    I'm having the same error after a reinstall. I am using EDK 10.1 SP3 and ISE Foundation 10.1 SP3

  • RELEVANCY SCORE 2.69

    DB:2.69:Quick Question: Compiling .F And .F90 cm



    is there any problem in compiling .f and .f90 files into the same program?

    DB:2.69:Quick Question: Compiling .F And .F90 cm


    Yes good point, or reverse the order of the source files to see if the lack of fixed-form indentation in main.f90 triggered errors.

  • RELEVANCY SCORE 2.69

    DB:2.69:Problem While Building A Solution ma


     
    After writing the program I build the solution by pressing F7 button.. if i am lucky and the power doesnt go when it is compiling, linking and building the solution, I will be able to get the executable... But incase the power goes when it is building the solution, when i restart the system i get a document filled with ***. How can i prevent this corruption of program when building or even debugging.... I have had to re write my program many times...because of this problem....
    I am using visual C++ express edition 2005

    DB:2.69:Problem While Building A Solution ma


    Hi,
     
    To prevent loss of information (due to inadvertently closing unsaved file changes, for example), the Visual Studio 2005/2008 auto saves your work on a regular basis. Should the IDE crash, it will prompt you to recover your work when you restart.
     
    You can set the auto save interval under “Tools Options Environment AutoRecover”.
     
    As another option, you can write an add-in to automatically save all changed project items at a user specified time interval, for detail information, you can refer to this article
    http://www.knowdotnet.com/articles/autosave.html
     

  • RELEVANCY SCORE 2.68

    DB:2.68:Problem With Edk 13.1 jp



    Hi

    I am use EDK 13.1 and i program in XPS and SDK but i have problem . i genrate bit file i can download to my fpga board but my board not work , this program worked in XPS 11.1 but When i worte in XPS 13.1 and SDK everything are OK and i had not any error code but my fpga bpard not work

    best regard

    DB:2.68:Problem With Edk 13.1 jp


    Hi

    I am use EDK 13.1 and i program in XPS and SDK but i have problem . i genrate bit file i can download to my fpga board but my board not work , this program worked in XPS 11.1 but When i worte in XPS 13.1 and SDK everything are OK and i had not any error code but my fpga bpard not work

    best regard

  • RELEVANCY SCORE 2.68

    DB:2.68:Regarding Edk 13.2., Not Showing Spartan 3e In Device Summary 3j



    hi.,

    I have installed xilinx13.2 EDk.,

    But it was not showing the Spartan 3E kit in the device summary., only spartan 6 and virtex was there in that list...

    What may be the problem.,

    Please help me

    DB:2.68:Regarding Edk 13.2., Not Showing Spartan 3e In Device Summary 3j

    Are you referring to Design Properties Evaluation Development Board tab? In starter kits only Spartan-3A and Spartan-3AN can be seen. If your kit is not present in that list, check for the full name of your device as per your kit and then you can set it by using the drop-down Family, Device, Package, Speed. It would be same. For example it would look as : XC3S1600E-4FG320. This can be set as Family : Spartan-3EDevice: XC3S1600EPackage: FG320Speed : -4Regards,Debraj



    Regards,Debraj----------------------------------------------------------------------------------------------Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.Give Kudos to a post which you think is helpful and reply oriented.----------------------------------------------------------------------------------------------

  • RELEVANCY SCORE 2.68

    DB:2.68:How To Use Digital Clock Manager Or Clock Generator In Edk x7



    I have a projekt where I have a 32MHz clock input and i am currently using the clock generator to generate a 64MHz clock from this clock. This 64Mhz clock is used as input to both the MicroBlaze and the plb bus.

    What I need now is a 44.8MHz clock, which I need to drive the baud generator in my uart, connected to Xin. So the first problem I encounter is that i think that the clock input (Xin) must be less than half the plb bus clock. Is that correct? As this is 64MHz this is no good. So I wanted to rise the plb bus clock to 96MHz. But trying this give me an timing constraint error when compiling the whole projekt in EDK. Is there anything I am doing wrong? Is it not possible to rise the clock to 96MHz for the plb bus?

    But further more. I also tried to generate a 22.4MHz clock for the uart. I tried that bus adding a Digital Clock Manager and using the CLKFX output I wanted 22.4MHz. But adding this DCM simply made both the clock generator output and the DCM output fail so I got 2 timing constraint errors when compiling. Why does me adding another DCM affect the other clock generator already working?

    Regards Rolf

    DB:2.68:How To Use Digital Clock Manager Or Clock Generator In Edk x7


    I have a projekt where I have a 32MHz clock input and i am currently using the clock generator to generate a 64MHz clock from this clock. This 64Mhz clock is used as input to both the MicroBlaze and the plb bus.

    What I need now is a 44.8MHz clock, which I need to drive the baud generator in my uart, connected to Xin. So the first problem I encounter is that i think that the clock input (Xin) must be less than half the plb bus clock. Is that correct? As this is 64MHz this is no good. So I wanted to rise the plb bus clock to 96MHz. But trying this give me an timing constraint error when compiling the whole projekt in EDK. Is there anything I am doing wrong? Is it not possible to rise the clock to 96MHz for the plb bus?

    But further more. I also tried to generate a 22.4MHz clock for the uart. I tried that bus adding a Digital Clock Manager and using the CLKFX output I wanted 22.4MHz. But adding this DCM simply made both the clock generator output and the DCM output fail so I got 2 timing constraint errors when compiling. Why does me adding another DCM affect the other clock generator already working?

    Regards Rolf

  • RELEVANCY SCORE 2.68

    DB:2.68:Cygwin Problem In Edk 9.1i xz



    I am running EDK 9.2i on windows7 (SEVEN) and when I download the bitstream
    to a board this is what I get:At Local date and time: Thu Feb
    07 19:47:22 2008xbash -q -c "cd /cygdrive/c/IMAGE_PROCESSOR/;
    /usr/bin/make -f IMAGE_PROCESSOR.make download; exit;" started...mount:
    /usr/bin: Permission deniedmount: /usr/lib: Permission denied

    mount:
    /: Permission deniedmount: /cygdrive: Permission deniedbash.exe:
    warning: could not find /tmp, please create!Installing Cygwin from
    EDK installation area...Added registry entries for C:\EDK\cygwin/cygdrive/c/EDK/cygwin/bin/bash:
    /usr/bin/make: No such file or directoryDone!
    Anyone
    else have this problem or know of a solution? Thanks!

    PS: I tried this answer http://www.xilinx.com/support/answers/25492.htm but nothing changed

    DB:2.68:Cygwin Problem In Edk 9.1i xz


    Hi,

    I had the same issue today with Windows 7.

    I solved the problem by launching the EDK as Administrator and with the XP Compatibility mode :

    - right click on the icon of Xilinx Platform Studio - Properties

    - tab Compatibility

    - check box Run this programm in compatibility mode for : Windows XP (SP3)

    - check box Run this program as an administrator

    - click OK

    Et hop !

  • RELEVANCY SCORE 2.68

    DB:2.68:Problem With Version Edition In Edk fs



    Hi ,

    I am using the XUPV5-LX110T Evaluation Platform for the OpenSparc implementation on FPGA. The entire project file given is generated using EDK 10.3 version SP3. But my lab has 12.2 version installed. No doubt, EDK updates the version of most IPs, but many of the older IPs are unavailable. I am stuck as I cannot generate the bit file or program the FPGA. My effort to install EDK 10.1 was futile as I was requested to give the registration ID for which I have been contacting the Xilinx service and they are not replying. Can anybody develop the project in 12.2 version of EDK so that it is possible to actually use the XUPV5 meaningfully?

    Thanks.

    DB:2.68:Problem With Version Edition In Edk fs


    Maybe you should post this in the EDK/Platform Studio forum? You might see more action there...

    - Bob Elkind




    SIGNATURE:README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369Summary:1. Read the manual or user guide. Have you read the manual? Can you find the manual?2. Search the forums (and search the web) for similar topics.3. Do not post the same question on multiple forums.4. Do not post a new topic or question on someone else's thread, start a new thread!5. Students: Copying code is not the same as learning to design.6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).7. You are not charged extra fees for comments in your code.8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

  • RELEVANCY SCORE 2.67

    DB:2.67:Really Urgent: Problem With Edk Software Platform pf



    i use EDK 9.1i. i want to add a default interrupt handler for plb EMAC, but in the Software Platform Settings, i cannot find any option to configure interruipt handlers... only drivers, OS and libraries and processor software platform.... i use ML300.. PLEASE help me out asap

    thanks

    v

  • RELEVANCY SCORE 2.67

    DB:2.67:14.2 Edk Bsp Unexpected Error zm



    Hi;

    I am using 14.2 EDK with 14.2 board support package and atlys board. When i create project wit BSP , i see "encountered an unexpected error" at board and system selection level. Could you help for this problem ?

    Thank you










    Attachments:




    DB:2.67:14.2 Edk Bsp Unexpected Error zm

    Hai, It is Better to reinstall the Software.

  • RELEVANCY SCORE 2.67

    DB:2.67:"Device Configuration" Missing In The Toolbars Of Edk 8x



    Hi all,

    I have a project developped with EDK 12.1

    Now i'm trying to open it in EDK 13.4 but i can't find "device configuration" in toolbars and in the view list so i can't generate and download my bitstream.

    Is it a problem of tools migration ?

    Any one can help me?

    Thanks in advance

    DB:2.67:"Device Configuration" Missing In The Toolbars Of Edk 8x


    Hi all,

    I have a project developped with EDK 12.1

    Now i'm trying to open it in EDK 13.4 but i can't find "device configuration" in toolbars and in the view list so i can't generate and download my bitstream.

    Is it a problem of tools migration ?

    Any one can help me?

    Thanks in advance

  • RELEVANCY SCORE 2.67

    DB:2.67:Fastest System For Edk Building ms



    EDK build performance seems to be a serious bottleneck in my debugging/development process. I'm hoping I can get some insight from the community about speeding it up. I am using a fairly fast machine, a 2.4Ghz Core2 Quad, but the EDK build uses only a single thread so it effectively only uses one of the core's. Can anyone recommend the fastest setup for EDK building? It doesn't seem like the build is disk performance limited at all. Does L2 cache size improve the performance of these algorithm's significantly? The newer Xeon's and high end Core2's have 12MB L2. Do Opteron's perform better than Core2's? (wouldn't think so since they are generally not as fast these days in general benchmarks)

    James

    DB:2.67:Fastest System For Edk Building ms


    Have folks found that 4GB of ram is a limitation for EDK? Unfortunately it currently takes a bit of work to setup a top end system with more than 4GB of ram (using gaming gear... which I believe will yield the fastest single thread performance). My project has occasionally consumed over 8GB of RAM, but this seems to happen fairly infrequently (memory leak?).

    James

  • RELEVANCY SCORE 2.66

    DB:2.66:Xilinx Ise Design Suite 11.1 Problem License c7



    Hi,

    I have ISE 11.1 (including DSP Tools 11.1) and Matalb 2008b installed on my PC (Win XP 32bit). But i get a "Xilinx License Error" when i start 'Manage Xilinx licenses'.

    It says''

    --------------------------------- Version Log ----------------------------------Version PathSystem Generator 11.1.1666 C:/Xilinx/11.1/DSP_Tools/nt/sysgenAccelDSP 11.1.1666 C:/Xilinx/11.1/DSP_Tools/nt/AccelDSPMatlab 7.7.0.471 (R2008b) C:/Programme/MATLAB/R2008bISE 11.1.i C:/Xilinx/11.1/ISE--------------------------------------------------​------------------------------Summary of Errors:Error 0001: ERROR: A license check out has failed for product: System... Block: Unspecified--------------------------------------------------​------------------------------Error 0001:Reported by: UnspecifiedDetails:ERROR: A license check out has failed for product: SystemGenerator for DSP (SysGen) ------------------- A message from the license manager --------------INFO:Security:61 - The XILINXD_LICENSE_FILE environment variableis not set.INFO:Security:63 - The LM_LICENSE_FILE environment variable isnot set.INFO:Security:68 - Please run the Xilinx License Configuration Manager (xlcm or "Manage Xilinx Licenses") to assist in obtaining a license.ERROR:Security:14 - No feature was available for 'SysGen'.--------------------------------------------------​------------------Cannot connect to license server system.The license server manager (lmgrd) has not been started yet,the wrong port@host or license file is being used, or theport or hostname in the license file has been changed.Feature: SysGenServer name: 141.24.121.196License path: C:/.Xilinx\license.lic;C:/.Xilinx\Xilinx.lic;C:\Xi​linx\11.1\ISE/data\*.lic;C:\Xilinx\11.1\EDK/data/c​ore_licenses\apu_fpu_v2_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\apu_fpu_virtex5_v1_flexlm.l​ic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_atmc_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_atmc_v2_00_a_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\opb_can_v1_flexlm.lic;C:\Xi​linx\11.1\EDK/data/core_licenses\opb_ethernetlite_​v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_ethernetlite_v1_flexlm.lic;C:\Xilinx\11​.1\EDK/data/core_licenses\opb_ethernet_v1_00_j_fle​xlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_​ethernet_v1_00_k_flexlm.lic;C:\Xilinx\11.1\EDK/dat​a/core_licenses\opb_ethernet_v1_00_l_flexlm.lic;C:​\Xilinx\11.1\EDK/data/core_licenses\opb_ethernet_v​1_00_m_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_lic​enses\opb_ethernet_v1_01_a_flexlm.lic;C:\Xilinx\11​.1\EDK/data/core_licenses\opb_ethernet_v1_flexlm.l​ic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_hdlc_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\opb_hdlc_v1_flexlm.lic;C:\Xilinx\11.1\EDK/d​ata/core_licenses\opb_hdlc_v2_00_a_flexlm.lic;C:\X​ilinx\11.1\EDK/data/core_licenses\opb_hdlc_v2_flex​lm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\opb_i​ic_v1_01_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core​_licenses\opb_iic_v1_01_b_flexlm.lic;C:\Xilinx\11.​1\EDK/data/core_licenses\opb_iic_v1_flexlm.lic;C:\​Xilinx\11.1\EDK/data/core_licenses\opb_pci_v1_00_a​_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\​opb_pci_v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data​/core_licenses\opb_pci_v1_00_c_flexlm.lic;C:\Xilin​x\11.1\EDK/data/core_licenses\opb_pci_v1_flexlm.li​c;C:\Xilinx\11.1\EDK/data/core_licenses\opb_uart16​550_v1_00_c_flexlm.lic;C:\Xilinx\11.1\EDK/data/cor​e_licenses\opb_uart16550_v1_flexlm.lic;C:\Xilinx\1​1.1\EDK/data/core_licenses\opb_usb2_device_v1_flex​lm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\plbv4​6_pcie_v3_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_​licenses\plbv46_pci_v1_flexlm.lic;C:\Xilinx\11.1\E​DK/data/core_licenses\plb_atmc_v1_00_a_flexlm.lic;​C:\Xilinx\11.1\EDK/data/core_licenses\plb_ethernet​_v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_l​icenses\plb_ethernet_v1_flexlm.lic;C:\Xilinx\11.1\​EDK/data/core_licenses\plb_gemac_v1_00_a_flexlm.li​c;C:\Xilinx\11.1\EDK/data/core_licenses\plb_gemac_​v1_00_b_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_li​censes\plb_gemac_v1_01_a_flexlm.lic;C:\Xilinx\11.1​\EDK/data/core_licenses\plb_gemac_v2_flexlm.lic;C:​\Xilinx\11.1\EDK/data/core_licenses\plb_pci_v1_fle​xlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses\plb_​rapidio_lvds_v1_00_a_flexlm.lic;C:\Xilinx\11.1\EDK​/data/core_licenses\plb_rapidio_lvds_v1_flexlm.lic​;C:\Xilinx\11.1\EDK/data/core_licenses\plb_temac_v​1_flexlm.lic;C:\Xilinx\11.1\EDK/data/core_licenses​\plb_uart16550_v1_00_b_flexlm.lic;[...]FLEXnet Licensing error:-15,10. System Error: 10061 "WinSock:Connection refused"For further information, refer to the FLEXnet Licensing documentation,available at "www.acresso.com". ''

    Any ideas what might be the problem ?

    thanks in advance

    DB:2.66:Xilinx Ise Design Suite 11.1 Problem License c7


    Hi Enigmaice,

    Try running "xlcm" from command line and then click over to the Manage Xilinx Licenses tab after the GUI opens. This will get you to the place that "Manage Xilinx Licenses" is trying to get you to.

    Do you have a license already?

  • RELEVANCY SCORE 2.66

    DB:2.66:Problem About Building A Bsb Project By Newer Version Xps / Sdk cd



    hi

    sorry for my silly question

    I wanna build the Test_Peripheral project from the following link

    http://www.xilinx.com/univ/xupv5-lx110t/design_files/BSB_CREATE/xupv5-lx110t_bsb_design.zip

    and this tutorialhttp://www.xilinx.com/univ/xupv5-lx110t/design_files/BSB_CREATE/xupv5-lx110t_bsb_design_creation.pdf

    I use Xilinx XUPV5 board , EDK / SDK 13.4 , and win7 64-bit

    After finishing the steps of the tutorial ,I generated my system ACE file by XMD tool

    but it does not work while ACE is loaded from CF card

    then , I try to generate ACE file again , by using download.bit and executable.elf from original zip file

    (not be compiled by my tool)

    , thesystem ACE file is generated successfully again , but still does not work

    do someone have any suggestions ?

    or I need to use an older version EDK for building / running Test_Peripheralproject ?

    thank you

    DB:2.66:Problem About Building A Bsb Project By Newer Version Xps / Sdk cd


    m,

    You need an older version. See your professor.




    Austin LeseaPrincipal EngineerXilinx San Jose

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk's Problem! Help k1



    hello,everyone,this is my first time in xilinx forum. I get a problem when I use edk platform.When I open the edk project file system.xmp, the console window appears a message,see as follows:WARNING:UtilitiesC:159 - Message file "MDT.msg" wasn't found.

    so,please tell me why it appears,and how to get rid of it warning?thanks a lot!

    best wishes!


    DB:2.66:Edk's Problem! Help k1

    Must uninstall EDK 9.1i prior to uninstalling ISE 9.1iThe installation of EDK and ISE can be done in any order.EDK 9.1i uninstall requires a valid ISE 9.1i installation. If ISE9.1i is uninstalled before EDK 9.1i, the Windows™Add/Remove Programs utility will not able to uninstall EDK9.1i. In this situation, you must manually delete the files,environment variables, and registry entries.Additional known issues and solution records correspondingto the EDK 9.1i release can be found at:http://www.xilinx.com/techdocs/24445.htm.

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk Service Pack #3 Can Not Read Ucf File. Poblem With Service Pack #3 Installation? k1



    The EDK of ISE Design Suite 10.1 works just fine after it was installed. But after I installed ISE service pack #3(file name: 10_1_03_win.exe) and EDK service pack #3 ( file name: 10.1_03_edk_nt.exe), the [Hardware--Generate Bitstream] process always reports "ERROR: ConstraintSystem:8

    - The file 'system.ucf'
    could not be opened for reading." What is the possilbe problem with my EDK service pack #3 installation? The UCF file did not cause any problem in plain 10.1 version.

    Is there any one there succeeding in installing the EDK service packe #3 and making it up and run?

    Edwin

    DB:2.66:Edk Service Pack #3 Can Not Read Ucf File. Poblem With Service Pack #3 Installation? k1


    Many thanks. In addition to data (directory) and system.ucf (file), I had to change the permission mode to 777 for etc (directory) and bitgen.ut (file) as well.

    Otherwise, so far so good.

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk 10.1 Install Error p1



    Hi guys,

    I have Windows 7 64-bit and before 3 months I installed ISE and EDK 13.4. So now i want to use the ISE and EDK 10.1 for my thesis. So I installed Oracle Virtual Box and put the Windows XP Prof 32-bit. Now i have problem to install the EDK 10.1 because i have not the right Registration ID for this system. How can i register now for this version?Has anybody one registration ID for this?

    Please help me...

    DB:2.66:Edk 10.1 Install Error p1


    Same problem.. did you find a solution please??

  • RELEVANCY SCORE 2.66

    DB:2.66:Problem Downloading Edk 11.1 9s



    Hi!

    I am trying to download EDK 11.1 from the Xilinx website...but the download stops at 1 or 2 percent everytime for some reason...I am using free download manager...and I downloaded ISE WebPack 11.1 with it just a few hours ago...please help

    DB:2.66:Problem Downloading Edk 11.1 9s


    Not sure why you're having trouble downloading.

    About using 9.2 projects in 11.1: Good luck. Many things have changed, including lots of IP from them. Depending on what exactly is in your 9.2 design, you will have varying levels of (un)success migrating to 11.1

  • RELEVANCY SCORE 2.66

    DB:2.66:Edk 9.2 / 9.1 Always Crashing xj


    Is anyone else experiencing EDK in Win XP 32bitcrashing for no apparent reason? Its no better than previous versions! It will crash when building a project. Re-open EDK and re-run the project and its fine. If it still crashes making a new project from scratch is the only cure. I have severalcontacts in other companies and they get exactly the same - Are we all doing something wrong...?

    I've noticed that if you try to implement a design and it has to synthesize and layout etc - ie, run the processes in one go, it has more of a tendancy to crash. If you run the steps one at a time it seemsbetter. I suspect that EDK is leaking memory like a sieve, so running a step one at a time frees up the memory.

    Any comments welcome.

    Thanks
    DMC

    DB:2.66:Edk 9.2 / 9.1 Always Crashing xj

    Hmmm, only 4GB. You think I need more??

  • RELEVANCY SCORE 2.66

    DB:2.66:Ise 13.1 Via Command Line pc



    Hello,

    I've been trying to write a batch file to run everything through command line.

    I got ISE working but I am getting errors dealing with EDK and SDK.

    Here is lines that used for EDK

    %EDK%\make.exe -f %DEEPSAS%\lanFPGA\synthesis\lanFPGA.make clean
    %EDK%\make.exe -f %DEEPSAS%\lanFPGA\synthesis\lanFPGA.make netlist
    %EDK%\make.exe -f %DEEPSAS%\lanFPGA\synthesis\lanFPGA.make exporttosdk
    It seems like clean and exporttosdk work just fine but I am getting following error while building netlist:
    process_begin: CreateProcess(NULL, platgen -p xc5vsx50tff665-1 -lang verilog -to plevel no -ti lanFPGA_i -msg _xps/ise/xmsgrops.lst lanFPGA.mhs, ...) failed.
    make (e=2): The system cannot find the file specified.
    make: *** [implementation/mb_plb_wrapper.ngc] Error 2
    Not quite sure what kind of file it is looking for, its pretty cleat that it is not lanFPGA.make file.
    I was wondering if someone might know solution to this problem or at least a hint.
    Thank you very much
    I also get problems with SDK but I am going to post it to a different thread.







    Solved!
    Go to Solution.

    DB:2.66:Ise 13.1 Via Command Line pc


    If you open a DOS command window using Start - Xilinx Design Suite 13.1- Accessories-ISE Design Suite Command Prompt, it will automatically set up all the environment variables for all IDS tools.

    barmaley wrote:

    Alright, its fixed for sure!!!!

    Here is what I have done:

    A. Set the environment variable XILINX

    Windows XP Professional

    Globally:
    1. Right-click My Computer, and select Properties.
    (NOTE: "My Computer" will be located under the "Start" menu if it is not on the desktop.)
    2. Click the Advanced tab.
    3. Click Environment Variables, and add the desired variable.

    Variable: XILINX
    Value: C:\Xilinx\13.1\ISE_DS\ISE

    B. Included bunch of different pathes tosearch path for executable files (I think %LIB% one is crucial)

    if "%SYNTH%" == "" setSYNTH=C:\path\to\your\synthesis\

    if "%ISE%" == "" set ISE=C:\Xilinx\13.1\ISE_DS\ISE\bin\nt
    if "%EDK%" == "" set EDK=C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin
    if "%XPS%" == "" set XPS=C:\Xilinx\13.1\ISE_DS\EDK\bin\nt

    if "%LIB%" == "" set LIB=C:\Xilinx\13.1\ISE_DS\ISE\lib\nt

    path=%ISE%;%XPS%;%EDK%;%LIB%;%SYNTH%

    Took only couple days to figure out, I wish make.exe error handler would give more info than just "the system cannot find the file specified"




    Cheers,Jim

  • RELEVANCY SCORE 2.66

    DB:2.66:Urgent Edk Update For Xc3sd3400a-4fgg676c Chip 9z



    i am building a project in edk and this error occured

    ERROR:MDT - Invalid target package 'fg676'

    i have edk service pack3 but this ic is not supported XC3SD3400A-4FGG676C can any one help me please

    DB:2.66:Urgent Edk Update For Xc3sd3400a-4fgg676c Chip 9z


    i am building a project in edk and this error occured

    ERROR:MDT - Invalid target package 'fg676'

    i have edk service pack3 but this ic is not supported XC3SD3400A-4FGG676C can any one help me please

  • RELEVANCY SCORE 2.66

    DB:2.66:Problem With Fsl, Dual Microblaze And Xilkernel 3c



    Hi to all,

    I don't understand what is wrong with my design. Can someone give me an idea ?

    I design a dual microbleze with BSB ( EDK 11.5) :

    Microblaze_0 + RS232_UART_1 + XPS_timer,

    Microblaze_1 + XPS_timer,

    Shared resources: Mutex, Shared_bram and DDR2_SDRAM.

    After that, I exported hw design to SDK.

    This it work ok with Xilkernel in SDK, but when I add a FSL conection between the two microblaze, and I try to install Xilkernel in SDK on Microblaze_0, I receive a strange error :

    Compiling standalone
    Compiling common
    Compiling lldma
    mb-hw.c: In function 'int_system_init':
    mb-hw.c:143: error: 'XPAR_XPS_INTC_2_DEVICE_ID' undeclared (first use in this function)
    mb-hw.c:143: error: (Each undeclared identifier is reported only once
    mb-hw.c:143: error: for each function it appears in.)
    mb-hw.c:150: error: 'XPAR_XPS_INTC_2_BASEADDR' undeclared (first use in this function)

    Compiling standalone

    Compiling common

    Compiling lldma

    mb-hw.c: In function 'int_system_init':

    mb-hw.c:143: error: 'XPAR_XPS_INTC_2_DEVICE_ID' undeclared (first use in this function)

    mb-hw.c:143: error: (Each undeclared identifier is reported only once

    mb-hw.c:143: error: for each function it appears in.)

    mb-hw.c:150: error: 'XPAR_XPS_INTC_2_BASEADDR' undeclared (first use in this function)

    The XPS_intc2 is attached to Microblaze_1, but it gives me this error when I compile Xilkernel for Microblaze_1.

    I attached the mhs file.

    Can someone give me an idea what is wrong?

    Many thanks,

    Iulian










    Attachments:







    system.mhs ‏12 KB

    DB:2.66:Problem With Fsl, Dual Microblaze And Xilkernel 3c


    i am implementing dual microblaze processor for shared peripheral access to uart., using xilinx 13.1 EDK tool, on xc5vlx110t.

    in sdk, two xilkernel bsp were created for shared access to uart .

    handling of mutex shows an error as

    "error: conflicting types for 'XMutex_LookupConfig'"

    the c code program is as follows......

    #include "xmk.h"#include "sys/init.h"#include "platform.h"

    #include "xmutex.h"#include "xparameters.h"

    #include stdio.h

    void *hello_world(void *arg){ XMutex mutex1; XMutex_Config mutex_config1; int i;

    XMutex_Config *XMutex_LookupConfig(XPAR_MUTEX_0_IF_1_DEVICE_ID);

    XMutex_CfgInitialize(mutex1, mutex_config1, 0x00000000);

    while(1) { XMutex_Lock(mutex1, 0x01); for(i=0;i=5;i++) {print("Hello embedded World\n\r"); } XMutex_Unlock(mutex1, 0x01); }}

    int main(){

    init_platform();

    /* Initialize xilkernel */ xilkernel_init();

    /* add a thread to be launched once xilkernel starts */ xmk_add_static_thread(hello_world, 0);

    /* start xilkernel - does not return control */ xilkernel_start();

    /* Never reached */ cleanup_platform();

    return 0;}

    it shows an error in this red highlighted line.................

  • RELEVANCY SCORE 2.65

    DB:2.65:Tft-Display With Edk Xps_Tft Ip-Core? 3s



    Hi together,

    I have a Virtex 5 ML509 Board with included Chrontel CH7301C Controller Chip for the DVI Interface.

    I'm building a system with EDK with a Microblaze and 1MB of SRAM with the Base Ssystem Builder.

    Then I'm adding the IP-Core XPS_TFT out of the IP-Catalog and i connect it to the PLB-Bus.

    Afterwards i made most of the tft-ports external and added the corresponding lines in the UCF-file to connect them to the FPGA-Pins.

    I used as well the clock generator to generate a 25 MHz clock and connected it to SYS_TFT_CLK since the dataseet mentioned a 25 Mhz clock for this module.

    Afterwards I'm configuring the IP Core and i write in the base-address of the SRAM because in the datasheet of the XPS_TFT is mentioned a Video memory.

    After synthesising i open the Software Platform Studio and I create a new projekt and I Import all the files from edk\sw\XilinxProcessorLib\tft_v1_00_a

    In this folder there is also an example C-Code for using this IP-Core. Now what i want to do is: Getting this example work!!!

    I imported the example as well in my software projekt and loaded it on the Virtex5.

    I inserted in the main-funtion some Words which are send over UART to the hyper Terminal. I can see this words so I know that there was no problem compiling the projekt. But my TFT-Screen keeps dark :-(

    Now I'm trying to get this example work for nearly a week and I can't think of any other idea to try. So does anybody have experience with TFT-Controll or does anybody know how to get this example work?

    I'm thankful for every respons!

    Regards

    Uli

    DB:2.65:Tft-Display With Edk Xps_Tft Ip-Core? 3s


    HeyNo, A clock is required definitely. And no, u dont need a second instance of the clock generator..1 clock generator for the entire system does it.. u just need extra clock signals from within the clock generator..its all a black box sadly..u just generate separate clock signals for ip's u add from a ip catalog..the ones from the bsb gen are handled by the bsb entirely..so within the same clock generator..make a new signal..set it to 25 Mhz and give it to the sys_tft_clk port. U will see the corresponding change in the ports tab in the system assembly view.

    Im not too sure about what ur saying about the __pin..if anything they should be same because iic signals help configure chrontel dac and the other data and sync signals are also going into the dac only

    Hope this helps

    Regards,Shashwat.

  • RELEVANCY SCORE 2.65

    DB:2.65:Error:Edk:369 - Make Failed For Target "Libs" d9



    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling common"arm-xilinx-eabi-ar: creating ../../../lib/libxil.a"Compiling xadc""Compiling standalone""Compiling axidma"xaxidma_bdring.c: In function 'XAxiDma_BdRingToHw':xaxidma_bdring.c:1068:2: error: 'DATA_SYNC' undeclared (first use in this function)xaxidma_bdring.c:1068:2: note: each undeclared identifier is reported only once for each function it appears inmake[1]: *** [libs]"Compiling iic""Compiling axivdma""Compiling devcfg""Compiling dmaps""Compiling emacps""Compiling gpiops""Compiling iicps""Compiling qspips""Compiling scugic""Compiling scutimer""Compiling scuwdt""Compiling ttcps""Compiling uartps""Compiling usbps""Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a]

    I build a Planhead project using ISE14.3, and export the .bit file to SDK, so comes there two errors.

    The reason of the first error may be the 'DATA_SYNC',it is automatically generated, but I donot know why this error happened.Maybe inxaxidma_bdring.c: In function 'XAxiDma_BdRingToHw', there is something wrong.

    How about the second error?

    I found

    in the directory 'lib' filefolder, i cannot find 'libxil.a'.

    So thank you for your help.

    DB:2.65:Error:Edk:369 - Make Failed For Target "Libs" d9


    Running libs - 'make -s libs "COMPILER=arm-xilinx-eabi-gcc""ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c""EXTRA_COMPILER_FLAGS=-g"'."Compiling common"arm-xilinx-eabi-ar: creating ../../../lib/libxil.a"Compiling xadc""Compiling standalone""Compiling axidma"xaxidma_bdring.c: In function 'XAxiDma_BdRingToHw':xaxidma_bdring.c:1068:2: error: 'DATA_SYNC' undeclared (first use in this function)xaxidma_bdring.c:1068:2: note: each undeclared identifier is reported only once for each function it appears inmake[1]: *** [libs]"Compiling iic""Compiling axivdma""Compiling devcfg""Compiling dmaps""Compiling emacps""Compiling gpiops""Compiling iicps""Compiling qspips""Compiling scugic""Compiling scutimer""Compiling scuwdt""Compiling ttcps""Compiling uartps""Compiling usbps""Compiling cpu_cortexa9"ERROR:EDK:369 - make failed for target "libs" ERROR:EDK:3418 - Error(s) while running make.make: *** [ps7_cortexa9_0/lib/libxil.a]

    I build a Planhead project using ISE14.3, and export the .bit file to SDK, so comes there two errors.

    The reason of the first error may be the 'DATA_SYNC',it is automatically generated, but I donot know why this error happened.Maybe inxaxidma_bdring.c: In function 'XAxiDma_BdRingToHw', there is something wrong.

    How about the second error?

    I found

    in the directory 'lib' filefolder, i cannot find 'libxil.a'.

    So thank you for your help.